ENEE 759H, Spring 2005 Memory Systems: Architecture and

Transcription

1 SLIDE, Memory Systems: DRAM Device Circuits and Architecture Credit where credit is due: Slides contain original artwork ( Jacob, Wang 005)

2 Overview Processor Processor System Controller Memory Controller DRAM Module DRAM Devices SLIDE

3 DRAM Device Architecture SLIDE 3 WE# CASL# CASH# addr bus 0 no. clock generator column address buffer refresh controller refresh counter row address buffer CAS# 0 row decoder 4096 column decoder 04 row select data out buffer 6 data in buffer 6 sense amp array I/O gating 04 x 6 DRAM Arrays 6 6 DRAM Device off chip I/O rows 04 columns 6 bits per col. RAS# no. clock generator

4 Storage Cells SLIDE 4 write bitline T capacitor T3 T storage node 3TC storage cell read bitline bitline access transistor Gate storage capacitor TC storage cell (classic DRAM) bitline read/ write read/ write bitline 6T storage cell (classic SRAM) DRAM: Dynamic Random Access Memory How long does memory storage last? Cell capacitance vs Leakage current

5 Storage Cell Structure I SLIDE 5 plate capacitor stacked capacitor bitline access transistor gate n+ p well above silicon in poly C = ε A d bitline gate n+ p well n+ Shrinking DRAM devices means reduced cross section (area) access transistor deep trench below silicon surface in trench

6 Storage Cell Structure II stacked capacitor poly poly 3 metal bitline bitline gate n+ p well access transistor poly bitline contact SLIDE 6 bitline gate n+ p well n+ bitline access transistor deep trench polystorage silicon insulating dielectric buried n + plate much deeper trench

7 Memory Systems DRAM Array I bitline contact storage capacitor unit cell SLIDE 7 8F bitline cell (F = feature size. 90nm etc) Polycide s Unlayered DRAM Cell Array

8 DRAM Array II SLIDE 8 row select DRAM Array bitline 04 x 6 sense amp array I/O gating V ref 0 0 V ref - Wordlines V ref + sense amp

9 DRAM Array III (folded bitline) bitlines Wordlines SLIDE 9 sense amps lanes through each cell (larger cell size) Cell size: typically 8 F Better noise tolerance (common mode rejection)

10 DRAM Array IV (Open ) bitlines Wordlines Dummy structures at array edges SLIDE 0 sense amps lane through each cell Cell size: typically 6 F sense amps pairs comes from different array segments Challenge: How to get good noise tolerance AND small cell size?

11 Sense Amplifier Wordlines sensing circuit voltage eq. circuit SLIDE SAN SAP EQ CSL WE Differential Control Signals

12 SLIDE Array Precharge Wordlines V ref 0 V ref SAN Precharge sensing circuit SAP voltage eq. circuit EQ CSL WE Assert equalize, Array precharged to V ref (typically /) V ref 0 V ref - V ref + Voltage color chart

13 SLIDE 3 Row Access I Wordlines V ref + 0 V ref V ref + SAN sensing circuit SAP voltage eq. circuit EQ CSL selected row () activated timeline WE +V t (V ref ) / Gnd 3 SAN SAP 4 5 CSL Access Sense Restore Precharge t RCD t RP t RAS

14 SLIDE 4 Row Access II (sense) V ref + V ref V ref + SAN sensing circuit SAP voltage eq. circuit SAN and SAP control signals active lower NFet more conductive, upper PFet more conductive. pairs slammed to opposite voltage rails, then upper NFet and lower PFet shut off completely. timeline EQ CSL WE 0 V - ref V ref V + ref Voltage color chart +V t (V ref ) / Gnd 3 SAN SAP 4 5 CSL Access Sense Restore Precharge t RCD t RP

15 SLIDE 5 Row Access III (Restore) 0 SAN sensing circuit SAP voltage eq. circuit Wordline kept open, now sensing circuit drives the full voltage level back into cell. If the column is selected, data is driven out to rest of the world. 0 EQ timeline CSL WE V ref 0 V ref - V ref + Voltage color chart +V t (V ref ) / Gnd 3 SAN SAP 4 5 CSL Access Sense Restore Precharge t RAS t RP

16 SLIDE 6 Write (over old data) SAN sensing circuit SAP voltage eq. circuit EQ CSL WE Wordline is still open, drives the full voltage level 0 into cell. V ref 0 V ref - V ref + Voltage color chart timeline +V t (V ref ) / Gnd 3 SAN SAP 4 5 CSL Access Sense Restore Precharge Write Recovery t WR t RP

17 Decoders and Redundancy SLIDE 7 row decoder n to n + m decode defect (hard error) spare columns (bitlines) n rows column select m spare rows (s) Challenge: How to get good yield and tolerate *some* defect?

18 Programmable Decoders I SLIDE 8 a 0, a 0 a, a a, a a 3, a 3 a 0 a 0 a a address valid Vcc address valid WL voltage standard decoder (each row has one) (laser) programmable link spare WL voltage spare decoder (each spare row has one) functionally equivalent to NOR gate with that can be disabled by laser (or fuse) functionally equivalent to NOR gate with s that can be selectively disabled

19 SLIDE 9 Programmable Decoders II a 3 a a a 0 4 address bits select of 6 rows. Suppose that row 0b00 is defective. blast it with laser other rows not shown spare rows replace standard decoder with spare row decoder blast it with laser spare rows a 3 + a + a + a 0

20 Device Control Logic SLIDE 0 WE# CASL# CASH# addr bus RAS# 0 no. clock generator column address buffer refresh controller refresh counter data in buffer row address buffer data out buffer no. clock generator 0 SDRAM Control Logic FPM +V t CKE CLK CS# WE# CAS# RAS# addr control logic command decode mode register bus address register row decoder refresh counter column address counter Remember SAN and SAP? Something has to control sequence and timing (V ref ) / Gnd 3 SAN 4 SAP 5 CSL Access

21 Mode Register CKE CLK control logic CS# WE# CAS# RAS# command decode mode register CAS Latency Burst Length Burst Type Burst Length =,, 4, 8, or Page mode CAS Latency =, 3 (4, 5, etc in special versions) SLIDE Burst Type = Sequential or Interleaved addr bus address register Modern DRAM devices (SDRAM, Direct RDRAM, DDRx SDRAM, etc. have programmable behaviour) Load value from address bus with special command.

22 Data I/O SLIDE 3 Internal data bus N bit width read latch write FIFO and drivers clk 6 6 MUX 4 3 mask 6 data DQS generator registers DLL drivers receivers clk 6 DQS External data bus N-bit width N Bit prefetch in DDR SDRAM devices 4N in DDR SDRAM devices, and 8N in DDR3 SDRAM devices Allows core to run at slower datarates while interface datarate cranks up. drawback - minimum burst lengths (loss of randomness )

23 SDRAM Device SLIDE 3 CKE CLK CS# WE# CAS# RAS# control logic command decode mode register addr bus address register refresh counter row addr mux column address counter row row address row address row latch & address latch decoder & address latch decoder & latch decoder & decoder bank control sense amp array sense amp array sense amp array sense amp array I/O gating / read data latch s column column column column decoder decoder decoder decoder DRAM Arrays data out register data I/O data in register Find bank 0, row 0x0F, column 0x0EA and get an A

24 Package and Pincount I SLIDE Semi Generation (nm) High Perf. device pin count High Perf. device cost (cents/pin) Memory device pin count Memory device pin cost (cents/pin) ITRS Roadmap DIP SOJ TSOP BGA Package Evolution (higher pin count, higher datarate) (higher costs, testing etc.)

25 Package and Pincount II SLIDE 5 VCC DQ0 VCCQ DQ DQ VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE# CAS# RAS# CS# A3(BA0) A(BA) A0(AP) A0 A A A VCC VCC DQ0 VCCQ DQ VSSQ DQ VCCQ DQ3 VSSQ VCC WE# CAS# RAS# CS# A3(BA0) A(BA) A0(AP) A0 A A A VCC VCC VCCQ DQ0 VSSQ VCCQ DQ VSSQ VCC WE# CAS# RAS# CS# A3(BA0) A(BA) A0(AP) A0 A A A VCC M x 6 3M x 8 64M x 4 54 pin TSOP VSS VSSQ NS DQ3 VCCQ VSSQ DQ VCCQ VSS RESERVED DQM CLK CLKE A4 A A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NS DQ6 VCCQ DQ5 VSSQ DQ4 VCCQ VSS RESERVED DQM CLK CLKE A4 A A9 A8 A7 A6 A5 A4 VSS VSS DQ5 VSSQ DQ4 DQ3 VCCQ DQ DQ VSSQ DQ0 DQ9 VCCQ DQ8 VSS RESERVED DQM CLK CLKE A4 A A9 A8 A7 A6 A5 A4 VSS SDRAM Same pinout, except for data bus

26 Process Technology SLIDE 6 Process Front End Process Back End layers of Al layer of Tungsten SiO 4+ layers: cell capacitance trench capacitors bulk silicon Metal Interconnections Inter-layer Dielectric Polysilicon 7+ layers of Cu low K or 3 layers: local interconnect Transistors high V t : low Vt : leakage optimized Drive current optimized DRAM Optimized Process Substrate BOX: Buried Oxide layer Logic Optimized Process