Semiconductor Memory Classification

Transcription

1 ESE37: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: November, 7 Memory Overview Today! Memory " Classification " Architecture " Memory core " Periphery (time permitting)! Project is on this Semiconductor Memory Classification Memory Architecture: Core M bits M bits Random Access SRAM DRAM RWM NVRWM ROM Non-Random Access FIFO LIFO Shift Register CAM EPROM E PROM FLASH Mask-Programmed Programmable (PROM) N Words S S S S N- S N_ Word Word Word Word N- Word N- Input-Output (M bits) Storage Cell N words > N select signals Too many select signals A A A K- Decoder S Word Word Word Word N- Word N- Input-Output (M bits) Storage Cell Decoder reduces # of select signals K logn Memory Architecture: Decoders Array-Structured Memory Architecture M bits M bits Problem: ASPECT RATIO or HEIGHT >> WIDTH S Word S Word L-K Bit Line Storage Cell N Words S S S N- S N_ Word Word Word N- Word N- Storage Cell A A A K- Decoder Word Word Word N- Word N- Storage Cell A K A K+ A L- Row Decoder Sense Amplifiers / Drivers Word Line M. K Amplify swing to rail-to-rail amplitude Input-Output (M bits) N words > N select signals Too many select signals Input-Output (M bits) Decoder reduces # of select signals K logn A A K- Column Decoder Input-Output (M bits) Selects appropriate word

2 Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks ROM Memories 7 8 MOS NOR ROM MOS NOR ROM [] [] [] [] [] [] [] [3] [] [] [] [3] MOS NOR ROM MOS NAND ROM [] [] [] [3] [] [] [] [] [] [] [] [3] All word lines high by default with exception of selected row

3 MOS NAND ROM MOS NAND ROM [] [] [] [3] [] [] [] [3] [] [] [] [] All word lines high by default with exception of selected row All word lines high by default with exception of selected row Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (5-6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (-3 transistors/cell) " Slower " Single ended Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks 6 Gate Based Latch 6T SRAM Cell! How many transistors in this latch?! Cell size accounts for most of array size " Reduce cell size at expense of complexity! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge, word " Raise! Write: " Drive data onto, " Raise 7 Penn ESE 37 Fall 6 - Khanna 8 3

4 6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell M M M M3 M M3 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Read) Assume is stored () Read Operation: - First bitlines get precharged high (Vdd) - Then wordline goes high (Vdd) M M M3 V M CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V M V M ( ) k n,m ( V Tn )ΔV ΔV k n, ΔV V Tn W k k n, V V DD DD V Tn k nm, ( V ) V n, L (V DD V Tn )ΔV ΔV 5 DD Tn k n,m W ( ΔV V Tn ) L (W/L)n, (W/L)n,M V DD (supercedes read constraint) 4

5 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V M Voltage Rise (V) W k n, L 5 k n,m W L ( V Tn )ΔV ΔV ( ΔV V Tn ) ΔV V Tn W L 5 W L (.5V Tn )V Tn V Tn ( ) Penn ESE 37 Fall 7 Khanna.5..5 Cell Ratio (CR).5 3 SRAM Read 6-transistor CMOS SRAM Cell! Precharge both bitlines high! Then turn on wordline,! One of the two bitlines will be pulled down by the cell word! Ex: A, A_b P P " discharges, stays high " But A bumps up slightly! Read stability " A must not flip " N >> N.5..5 word A_b N bit_b A N N3 A_b N4 Assume is stored () Write Operation: - Want to write a - First drive bitlines with input data - Then wordline goes high (Vdd) M M M3 A Penn ESE 37 Fall 6 - Khanna time (ps) 7 CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) M M k n, ( V ) Tn k p, ( V ) Tp (W/L) n, k.33 (W/L) p, n,m 6 ( V Tn ) k n,m 4 (V 8 DD V Tp )V V k n, V V DD DD V Tn kn, ( M ) V DD V VTn DD (W/L) n, (W/L) n,m 5

6 CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) PR W 4 L 4 W 6 L 6 M M k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V V k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V V V V Tn k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V Tn V Tn CMOS SRAM Analysis (Write) SRAM Write PR W 4 L 4 W 6 L 6! Drive one bitline high, the other low " Depending on write data! Then turn on wordline,! Bitlines overpower cell with new value! Ex: A, A_b,, " Force A_b low, then A charges high! Writability " Must overpower feedback inverter " N4 >> P word N word A A_b P N A P N time (ps) A_b N4 Penn ESE 37 Fall 7 Khanna Penn ESE 37 Fall 6 - Khanna 34 Memory Periphery Periphery! Decoders! Sense Amplifiers! Input/Output Buffers! Control/Timing Circuitry Penn ESE 37 Fall 7 Khanna 6

7 Array Architecture Array Architecture! n words of m bits each! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Good regularity easy to design! Very high density if good cells are used Penn ESE 37 Fall 7 Khanna 37 Penn ESE 37 Fall 7 Khanna 38 Array Architecture Array Architecture! n words of m bits each! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Good regularity easy to design! Very high density if good cells are used Penn ESE 37 Fall 7 Khanna 39 Penn ESE 37 Fall 7 Khanna 4 Decoders Decoders! n: n decoder consists of n n-input AND gates " One output needed for each row of memory " Build AND from NAND or NOR gates Static CMOS A A word 8 word word A 4 A word word3 Penn ESE 37 Fall 7 Khanna Penn ESE 37 Fall 7 Khanna 4 7

8 Large Decoders! For n > 4, NAND gates become slow " Break large gates into multiple smaller gates A3 A A A word Predecoding! Many of these gates are redundant " Factor out common A3 gates into predecoder A " Saves area " Same path effort A A predecoders word word of 4 hot predecoded lines word word word3 word word3 word5 word5 Penn ESE 37 Fall 7 Khanna 43 Penn ESE 37 Fall 7 Khanna 44 Row Select: Precharge NAND Row Select: Precharge NOR Penn ESE 37 Fall 7 Khanna 45 Penn ESE 37 Fall 7 Khanna 46 Array Architecture Column Circuitry & Bit-line Conditioning! n words of m bits each! Good regularity easy to design! Very high density if good cells are used Penn ESE 37 Fall 7 Khanna Penn ESE 37 Fall 7 Khanna 48 8

9 Column Circuitry Bitline Conditioning! Some circuitry is required for each column " Bitline conditioning " Precharging " Driving input data to bitline " Sense amplifiers " Column multiplexing (AKA Column Decoders)! Precharge bitlines high before reads φ Penn ESE 37 Fall 7 Khanna 49 Penn ESE 37 Fall 7 Khanna 5 Bitline Conditioning Bitline Conditioning! Precharge bitlines high before reads! Precharge bitlines high before reads φ φ! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip Penn ESE 37 Fall 7 Khanna 5 Penn ESE 37 Fall 7 Khanna 5 Sense Amplifiers Idea! Bitlines have many cells attached " Ex: 3-kbit SRAM has 8 rows x 56 cols " 8 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) V()! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down V PRE ΔV V() Penn ESE 37 Fall 7 Khanna Sense amp activated Word line activated t

10 Admin! Homework 7 due Monday /3! Project handout will be released on Monday " Work in pairs, start pairing off " Report (via ) pairs to me by Friday /7 " Milestone due Wednesday / before Thanksgiving " I will give feedback by Friday (night) /4 after thanksgiving " Submit COMPLETE milestone early and you ll get feedback early " Final report due /4 55