Design and Implementation of Memory Controller for Real Time Video Display Using DDR3 SDRAM

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1 Design and Implementation of Memory Controller for Real Time Video Display Using DDR3 SDRAM Syed kareem saheb, Research scholar, Dept. of ECE, ANU, GUNTUR,A.P, INDIA. D.Shalini Krishna PG student dept. of ECE (VLSI) ASIT, GUDUR, A.P, INDIA. B. Mallikarjuna Reddy Associate professor, Dept. of ECE, ASIT, GUDUR, A.P, INDIA. ABSTRACT: -The design of DDR3 SDRAM using FPGA technology play a very vital role on the integrated circuit area to minimize the time to market and cost. The advancement in the design of memory controller has lead to attain good favour for memory, device and I/O. This project incorporates reading the data which is stored on the FPGA and sending it to the VGA driver and to the VGA screen for the display of the video data. This project describes the designing of the memory controllers for the DDR3 SDRAM devices using with IP and reconfigured memory controller. The DDR3 SDRAM can transfer data at twice the rate. The main advantage of DDR3 is the capacity of I/O information exchange increases with eight times the speed of its internal memory arrays. This DDR3 gives higher rates than forward memory transfer rates. The results can be verified using simulation tool, chip-scope and real time display of the data stored. This project gives us a real report for the designing of DDR3 SDRAM controller using Xilinx tool. Key Words: Virtex-6 FPGA board, DDR4 SDRAM, Web Camera module, Monitor display. I.INTRODUCTION In modern years, there has been extensive progress in the sector of integrated circuit design. The improvement in the processing technology required memory devices operating at a high speed. The developing memory tools elaborated with improvement in the latency, speed etc. The exhaustive memory device developed was SDRAM, it is synchronized in favour of positive edge of the clock. The further approach includes exactness in designing a system. This includes designing a memory controller. The controller mostly focuses on the interaction of memory and processor with a goal of well refined memory designs. II.TYPES OF MEMORY: DDR1 SDRAM: Double data rate initially referred to as simple DDR and it was designed to restore SDRAM. The data transformation occurs at the both falling edges and rising edges of digital Pulse. DDR transfers the data 2 times to the SDRAM. DDR2 SDRAM: Following DDR1, DDR2 is next generation of memory device. The DDR2 SDRAM operates 2 times more than that of DDR SDRAM. DDR3 SDRAM: DDR3 is next generation of memory initiated after DDR2. DDR3 works two times more in speed to DDR2 SDRAM with a Pre-fetch buffer having size of 8-bits, also with increased frequency of operation which results in higher data rate than DDR2 DDR3 has memory reset option which other type of memories do not allows, memory to be void by software reset work which results in a more strong memory system. DDR4 is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface. DDR4 is not compatible with any earlier type of random access memory (RAM) due to different signaling voltages, physical interface and other factors.fpga design is extensively used and this technology plays a very vital role in order to minimize the time to market and cost. Design of the memory controller is important for well organized use of the memory. The graphic display for video is by VGA. It is a video display level that gives straight forward technique to interface any framework with a screen for display of data or pictures. VGA is widely utilized as standard display unit. Video graphic display is more important while presentation than the ISSN: Page 31

2 verbal voice. II. IMPLIMANTATION with less- complications as it requires timing crystals, external RAM DAC and video memory. VGA Principle It is a video interface standard and contains 640 x 480 of picture components namely pixel. The pixels are repeatedly tuned on and off to represent image. After the values are updated in horizontal row the pointer increments to the new column and repeat the same procedure. Screen must be refreshed for every 60seconds. Figure 1: Main Block diagram Camera module encapsulates images and images are then transformed to the DSP in the camera vc0706. The image is then transmitted above UART communication protocol to the FPGA and then it is stored on chip memory of FPGA. The block shown in fig 1 includes reading the data saved on the FPGA in order and then transformed to the VGA/TFT driver and then to the VGA screen for the display of the video data. Figure 3: Scanning pattern of VGA Controller III.GENERAL ARCHITECTURE OF VIRTEX-6 FPGA The given figure 4 displays memory interface using Vertex-6 FPGA MIS center. The construction contains key modules and interface with IP. Figure 2: Real time video display using ddr3 sdram memory controller The block shown in fig 2 includes reading the data saved on the FPGA in order and then sending it to the VGA/TFT driver and then to the VGA screen for the display of the video data. FPGA Generally in the FPGA design the most bit is determined deploying a HDL, like that used for an ASIC. FPGA advanced ICs contain logic blocks with configurable squares. It contains programmable segments known as logic elements. FPGA gives reconfigurable nature, which is powerful in reducing the registered cost of the design. This is the reason why FPGA are extensively used as the prototype development standard. VGA CONTROLLER VGA is a video display, technique that interface structures with screen to specify data and pictures. VGA analog interface is used as high definition video with higher aspiration. It is introduced as an array rather than adapter because it can be easily available as single chip VGA. It can be directly performed on PC mother boards USER DESIGN The IOB (client outline box) shown in Figure 4 is FPGA plan associated with DDR4 SDRAM. Client outline communicates with memory controller along the client interface. A client outline is provided with the core. User Interface/ Interface block The block discloses UI to the client plan block. It gives a basic differentiating option to local interface by displaying level location space with buffering read operation and write operation. Native interface and Memory Controller (MC) Front end of MC shows the local interface to UI square. The local interface allows client outline to appoint write information and read information as well as allows some elements to move data from outside memory to client outline and client outline to outside memory. The back end is related physical interface. MC throughput as well as latency can be improved by reordering. ISSN: Page 32

3 IV.IP DESIGN OF DDR3 MEMORY CONTROLLER Figure 4: The complete memory interface from the user design to the DDR3 SDRAM In the sketch of the DDR4 SDRAM controller voluntarily available IP the signals are initialized and applied as stated to the MIG (Memory Interface Generator) design and conduct the operation at the user design end, for either read or write. For write operation the addrs/cmd performs the address translation and Wr_Data/DM is later given to write data buffer and next these signals are applied to reordering controller following the physical layer. The complete flow of signal after the user interface block given to the native interface, and the data is proceeds finally to the physical interface and later to the external DDR4 SDRAM from the FPGA. Every phase includes illustrating of the signals. Reconfigured memory controllers: The memory controller is designed by using the equivalent signals given in the diagram which is shown below and every signal has an function connected with it ISSN: Page 33

4 Figure 5: Internal block diagram of the Memory controller V.RESULTS RESULTS AND OBSERVATIONS Figure 7: RTL schematic of reconfigurable device design. The signal dq gives the data either read or written depending on operation. The dqs specifies the data strobe is bidirectional pin, when the system is performing the write operation the controller issues the dqs command and vice versa in read command FSM for DDR3 SDRAM controller Fig:8 Tec schematic of Reconfigurable device Figure 6: FSM for DDR4 SDRAM memory The memory controller design flow can be described as follows: 1. The DDR4 SDRAM memory is initialized with initialization signals advance to any communication to allow the information respecting the status of the signal. 2. Behind initialization, pre-charge initialization is supplied to check and ensure that no row or entire bank is being used. 3. The pre-charge operations returns the bank to the idle state, the refresh is then compulsory to perform the required action. 4. Another refresh command as a backup option to stop failure. 5. The mode register mr0 is defined at this stage. 6. The operations performed till now are part of the initialization orders. 7. The design at the idle state is activate for the desired operation either in terms of read or write. 8. If write then the address where the data to be written or stored is been issued previously. Then the state machine gets terminated by returning to the idle state. 9. If read operation is to be performed the desired data is read and after the action the process terminates by returning to idle state. 10. If any further action is to be performed then the, repeat pre-charge following refresh and the operation Figure 9: detail RTL schematic with IP Figure 10: TEC schematic of with IP ISSN: Page 34

5 6] T.D. Manoj Kumar Reddy, Implementation and Customization of UART in Xilinx FPGA International Journal of Combined Research & Development (IJCRD) eissn: X; pissn: Volume: 2; Issue: 1; January ] Radi H.R, Caleb W.W.K., M.N.Shah Zainudin., M.Muzafer Ismail. The Design and implementation of VGA Controller. International journal of Electrical and computer Sciences, 2012, Vol.12, Issue 5, pp ] Prof. Arun.S.Tigadi1, Padmashree. G 2, Hansraj Guhilot3. Design and Implementation of Memory Controller for Real Time Video Acquisition using DDR3 SDRAM, 2016, Vol.5, Issue 8. 9] Xilinx, Virtex-6 FPGA Memory Interface Solutions User Guide ug ] Fangqin Ying, XiaoqingFeng, Design and Implementation of VGA Controller Using FPGA, International Journal of Advancements in Computing Technology (IJACT), Vol. 4, No. 17, pp , Sep 2012 BIOGRAPHY Figure 11: Simulation result of read signal Mr.Syed Kareem Saheb,Associate Professor,HOD,ECE Dept of Audisankara Institute of Technology,Gudur.He is a Research Scholar in Dept of Communication and Engineering at ANU College of Engineering and Technology,Guntur,A.p D. Shalini Krishna did his bachelor of Technology in ECE at Narayana Engineering college,nellore,andhrapradesh,india and doing Master of Technology in VLSI Design at Audisankara institute of Technology,Gudur, Andhrapradesh,India Mr.B. Mallikarjuna Reddy, Associate Professor,ECE Dept of Audisankara Institute of Technology,Gudur. He is Research in Low Power VLSI and Testing of VLSI Circuits. Figure 12: Simulation result of Write signal VI.CONCLUSION: The diagram elaborated for the real time video display and memory controller helps to provide systematic use of the memory with XillinxML-605(Virtex-6) FPGA.The project is engaged using Xilinx The controller is designed for the available IP and reconfigured controller. The controller presents the data and it is an attractive approach for various applications involving a display. The display used is VGA. The project is executed on ML605 evaluation board with on chip DDR4 SDRAM of 1GB.The designed system includes a display of data at the same time at different locations. The designed system can survey the in-built features such as error detection and correction and AXI interface etc. VIII.REFERENCES 1] Fabrizio Pece and Jan Kautz and Tim Weyrich. Adapting Standard Video Codecs for Depth Streaming, ] Raj kiran Addu and vinod Kumar Potuvardanam. Effect of Codec Performance on Video QoE for videos encoded with Xvid, H.264 and WebM/VP ] M.Rajendra and N.Suresh Babu. Speed and Area optimized Design of DDR3 SDRAM (Double Data Rate3 Synchronously Dynamic RAM) Controller for Digital TV Decoders, International Journal of Engineering Trends and Technology, 2013, Vol.06 Issue 4, pp ] Ms.Seema Sinha and Md.Tariq Anwar. design and verification of ddr3 memory controller.international Journal of Advanced Technology in Engineering and science, 2014, Vol.02, Issue 05,pp ] Renuka Wasu And Vijay R, Wadhankar. Review on design of VGA controller using FPGA International journal of Science and Research, 2015, Vol.4, Issue 2, pp ISSN: Page 35