Design and Implementation of Buffer Loan Algorithm for BiNoC Router

Transcription

1 Design and Implementation of Buffer Loan Algorithm for BiNoC Router Deepa S Dev Student, Department of Electronics and Communication, Sree Buddha College of Engineering, University of Kerala, Kerala, India Abstract- Novel BiNoC router architecture is presented that supports dynamic self-reconfiguration of channel direction and buffer reconfiguration. In conventional BiNoC architecture to accommodate heavy traffic, large buffer is needed. But the proposed router (BiNoC router with reconfigurable buffer) can support heavy traffic without the need of large buffer. In this case power dissipation is less and performance is better than conventional BiNoC router. The designing has been done using the hardware description language VHDL in XILINX ISE tool. Its FPGA implementation is done using Virtex-5 board. and the main function of this unit is ordering and reordering of packets. In BiNoC, unidirectional channels present in the general router are replaced by bidirectional channels. The main advantage of bidirectional channels is that we can transmit 2 packets simultaneously. But heavy traffic demands larger buffer in BiNoC. This results in power dissipation. To avoid this, buffer reconfiguration is adopted in BiNoC router. Keywords BiNoC, bidirectional channel. I. INTRODUCTION Network-on-Chip (NoC) is a communication subsystem for interconnecting various IP cores present in the System on a Chip (SoC). NoC architecture is proposed as a high performance, scalable and power efficient alternative to the bus based architecture. It solves scalability problem by providing multiple connections with various systems. As systems become more complex, more and more integration is possible to the existing system without any difficulties. The NoC is able to separate communication part from the computational part. It is ideally suitable for integrated systems. NoC can take care of the communication part easily without results in any interference in the computation part. Point to point links and shared buses are other interconnecting architectures present in NoC. In the case of point to point interconnecting architectures, increase in the number of processing elements results in the increase of number of wires. But, long wires result power dissipation. In the case of shared bus only one data transaction is possible at a time. But in NoC, power dissipation is small and several data transactions are possible at a time. Fig. 1 shows a basic NoC. A typical NoC consists of routers, links and network interface. Routers are used to find the destination by processing the data packets they received. It also finds the best path towards the destination. Links are wires which are used to interconnect various routers or it is used to connect router to network interface. Network interface separates the communication part from the computation part. It consists of a front end back end part. Front end part is connected to the network interface. It is unaware of communication part. Back end part is connected to the router Fig. 1 Basic NoC The rest of this paper is organized as follows. Section II, reviews the important contribution of researches in the field of NoC. Section III deals with motivation behind BiNoC router with reconfigurable buffer. Architecture of BiNoC router is presented in Section IV. In section V, CDC protocol is presented. Buffer loan algorithm is presented in section VI. Finally, in Section VII, experimental results are presented. In the last section, conclusion of the work is presented. II. RELATED WORK The performance of NoC architecture is better than bus based communication [1]. As compared to other interconnecting architectures such as bus and wires, power consumption of NoC architecture is very low. The router architecture usually consists of 5 input ports and 5 output ports. Power consumption generally depends on injection rate at the processor. Reconfiguration of channels results doubling of bandwidth in BiNoC router [6]. But heavy traffic demand needs large buffer size. Large buffer size results increase in ISSN: Page 87

2 power dissipation [7]. Based on application, a router can support different bandwidth. Buffer reconfiguration results improvement in router efficiency [5]. III. MOTIVATION In typical NoC, adjacent routers are communicated by using two unidirectional channels. But the channels are in opposite direction. In BiNoC, adjacent routers are interconnected by bidirectional channels. The use of bidirectional channel improves the bandwidth. In this architecture high priority port of one router is connected to the low priority port of adjacent router. Similarly low priority port is connected to the high priority port. This type of connection avoids deadlock and starvation. Data transmission in typical and BiNoC router is shown in Fig. 2.The performance of BiNoC router can be improved by buffer reconfiguration. directional channels present in the NoC by bidirectional channels. HP FSM of one router is connected to the LP FSM of adjacent router. This FSMS are communicated by using 2 handshaking signals, input_req and output_req. Fig.2 Channel direction in Typical NoC and propose BiNoC IV. BIDIRECTIONAL CHANNEL ROUTER ARCHITECTURE The backbone of NoC is router. In a packet switched network, the main function of the router is to receive the incoming packet, process it to find the destination and finally figure out the best path towards the destination. In the NoC, routers are classified into two, conventional router and the bidirectional router. In conventional or general router full duplex communication is implemented with the help of 2 unidirectional channels. But in BiNoC, full duplex communication is implemented using 2 bidirectional channels. The operation of bidirectional channels are controlled by CDC protocol. This protocol supports channel reconfiguration. Because of this channel reconfiguration, bandwidth is 2 times as that of general router. In this BiNoC architecture, XY routing algorithm is used. BiNoC architecture is shown in Fig. 3. V. CHANNEL DIRECTION CONTROL ALGORITHM The direction of channels is reconfigured by using channel direction control protocol. This protocol configures the channel direction based on the traffic demands. The control algorithm is implemented by using two finite state machines. For better routing efficiency, one of the FSM is assigned with higher priority and the other is assigned with lower priority.cdc protocol replaces the entire uni Fig.3 BiNoC Router architecture A. Bidirectional Channel Direction Control High priority and a Low Priority FSMS are shown in Fig.4 (a) and (b), respectively. High priority and low priority FSM has 3 states: free, wait, and idle sate. a) Free State: the channel is ready to send data to the adjacent router. b) Idle state: the channel is available to receive data from the adjacent router. c) Wait state: It is an intermediate state ready to transition from idle state to free state. The working of the HP FSM and the LP FSM are discussed below. 1) HP FSM Operations: The initial state of the high priority FSM is the free state. It will remain in this state as long as data packets are present with in the current router that has to be transmitted through the channel. The only condition that the HP FSM will ISSN: Page 88

3 leave the free State and enter in an idle state is when there is no data to transmit from the current router, and there is data to be sent from the adjacent router. In free state output request is equal to the channel request. Channel request signal is the output of routing computation module. Once the FSM enters the idle state, it will remain in that state as long as there is no data to be transmitted from current router (channel_req = 0). In this case, output signal output_req will be 0.When channel_req becomes 1, HP FSM switches to a wait state. When FSM is at wait state an internal counter will be activated and output_req will be equal to 1. As soon as the count reaches 2 HP FSM returns to free state and starts data transmission. Meanwhile the counter is reset to count= 0. 2) LP FSM Operations: Initial state of the low priority FSM is the idle state. In this state output_req=0. It will leave the idle state and switches to a wait state if the HP FSM of the other router yields the channel (input_req = 0) and a local RC module requests to use the channel (channel_req = 1). The LP FSM will remain in the wait state for four clock cycles. During any of these four cycles, if the HP FSM requests the channel (input_req = 1), the LP FSM will return to an idle state. Only after four cycles (count = 4) and if input_req = 0, the LP FSM will enter a free State and begins the data transmission. However, different from the HP FSM, an LP FSM may remain in the free state only if HP FSM does not have any data packet to transmit (input_req = 0). Once input_req = 1, the LP FSM will stops the data transmission immediately and go back to an idle state. Fig 4 (a) HP FSM Fig. 4(b) LP FSM V1. BUFFER LOAN ALGORITHM Buffer loan algorithm enables the use of buffer slots of one channel by the adjacent channels. When a channel fills its entire buffer slots it can borrow buffer slots from its left neighbour and right neighbour. First the channel asks buffer slots from its left neighbour. If it again needs buffer slots, then it asks for right neighbour. Each channel needs to know the number of buffer slots of that channel occupied by its own channel flits and also needs to know the number of buffer slots of left and right neighbour occupied by its own channel flits. Each channel also needs to know the number of buffer slots of its own channel occupied by left and right neighbours. Each input port has a control unit to store the flits and this control is based on pointers. Each input channel has six pointers to control the read and write operations. Out of these 6 pointers, two pointers are used to control the read and write operation of its own buffer slots, two pointers to control the read and write operation of left neighbour, and the remaining two pointers are used to control the read and write operations of right neighbour. Fig. 5 shows the original and reconfigurable buffer. In BiNoC architecture both high priority and low priority port consists of this reconfigurable buffer. In this design the reconfiguration of Local Channel is not considered, only the South, North, West, and East Channel reconfiguration is considered. Consider the example given in Fig. 5 (b). In this figure, inputs for south channel are, its own input (din_s), the right neighbour input (din_ E_S), and the left neighbour input (din_w_s). Assume that we are using a router with buffer depth equal to 4, and there is a router that needs to be configured as follows. East Channel needs a buffer depth equal to 3, North Channel needs a buffer depth equal to 4, South Channel needs a buffer depth equal to 6, and West Channel needs a buffer depth equal to 3. ISSN: Page 89

4 _W_ S (West flits stored in the East buffer) to send the flits stored in its channel but belonging to neighbour channel. Fig. 6 shows the architecture of BiNoC router with reconfigurable buffer. Fig. 5 (a) FIFO buffer in BiNoC Fig. 6 BiNoC router with reconfigurable buffer Fig. 5 (b) Reconfigurable FIFO buffer In this case, the south channel needs 6 buffer slots, but the buffer size available is 4. So the south channel has to borrow buffer slots from its right and left neighbours. As the west channel occupies only three slots, the remaining slot can be lent to the south Channel. As the east channel needs only three of its four slots, so the south channel can lend one slot to its neighbour. When the south channel has a flit stored in the east channel, then this flit must be passed from the east channel to the south Channel (d _S_ E). Then the flit is directly sent to the crossbar by a multiplexer. The south channel has the following outputs: the own output (dout_ S) and two more outputs (d _E_S (East flits stored in the south buffer and d VII. EXPERIMENTAL RESULTS A.Performance Evaluation Main performance evaluation parameters considered in this architecture are area and power. B. Simulation setup The proposed BiNoC router with reconfigurable buffer is designed using the hardware description language VHDL in XILINX ISE tool. In this architecture buffer size is 4. The design is simulated using Isim simulator. Simulation result of buffer loan algorithm is shown in Fig. 7. ISSN: Page 90

5 C. Implementation setup FPGA. The proposed router is implemented using Virtex-5 ACKNOWLEDGEMENTS Author wish to remark the great task carried out by the Xilinx and Virtex-5 user guide; and the author wish to thank Prof. Somi Sebastian for his contribution in the design process. REFERENCES [1] W. J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, in Proceedings of DAC, pages , [2] L. Benini and G. De Micheli, Networks on Chips: a New SoC paradigm, IEEE Computer, 35(1):70-78, Jan [3] Lionel M. Ni and Philip K Mckinley, A survey of wormhole routing techniques in direct networks,computer, Vol. 26, Issue 2, pp , Feb1993 [4] Rantala, V., T. Lehtonen, J. Plosila, Network on Chip Routing Algorithms, TUCS Technical Report, pp [5] M. A. Al Faruque, T. Ebi, and J. Henkel, Configurable links for runtime adaptive on-chip communication, in Proc. DATE, Apr. 2009, pp Fig. 7 Buffer loan algorithm D. Comparison of various routers [6] Y. C. Lan, S. H. Lo, Y. C. Lin, Y. H. Hu, and S. J. Chen, BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel, in Proc. NOCS, May 2009, pp [7] Debora Matos,Caroline Concatto, Marcio Kreutz Reconfigurable Routers for Low Power and High Performance, IEEE Trans. Very Large Scale integer (VLSI) Syst., vol. 19, no. 11, pp , November Comparison of various routers based on number of channels that can be reconfigured and the number of flits that can be stored is given below. Table I Comparison of Various routers Router No: of channels that can be reconfigured No: of flits that can be stored Basic router 1 Depends on buffer size BiNoC router 2 2*buffer size Basic router with reconfigurable buffer BiNoC router with reconfigurable buffer 1 buffer size 2 2*buffer size VII. CONCLUSION In this paper, I presented a buffer loan algorithm that supports real time buffer reconfiguration in the bidirectional channels while avoiding deadlock and starvation. In this paper an accurate hardware model for BiNoC router with reconfigurable buffer is implemented with VHDL. ISSN: Page 91