Freescale Healthcare Applications

Transcription

1 Freescale Healthcare Applications APF-HCR-T0460 David Chen MCU FAE APR.2014 TM External Use

2 Agenda Portable Healthcare Applications Development Tools and Reference Designs for Available Specifically for Healthcare Device Developers Energy Saving Architecture Measurement Engine External Use 1

3 It s a connected world fostering quality of life. Interaction/Context Personal Gateway Internet Services Motion Reaction Emotion Posture Biometrics Personal Vital Monitoring Fitness Tracker Trajectory Impact Velocity Power Feedback Entertainment Devices + objects low energy WLAN Cellular data Technique Coaching Weight-loss Manager Location Altitude Temperature Humidity Light Sound Ambient Elderly Monitoring Virtual Sports External Use 2

4 The Home Health Hub Platform i.mx53 Tablet With Medical User Interface Physician Social Networking Monitoring Center Loved Ones Social Network Ethernet HHH Ref Platform Gateway i.mx28 TELE-HEALTH HOME AUTOMATION HHH Ref Platform Expansion Capabilities Smart Plugs Smart Appliances Safety/Security Lighting Control Local Display 868MHz RF Bluetooth HDP Bluetooth SPP Bluetooth Low Energy USB PHDC HealthCare Wired connection Wireless connection HHH Panic Alarm MC12311 Blood Glucose Meter Nonin Pulse Ox MC9S08GP32 Thermometer Blood Pressure Monitors Weight Scale Medical monitoring WWW connection External Use 3

5 Healthcare device general architecture EEPROM Signal Conditioning LCD Driver Connectivity BT/LE Sensors ADC Wi-fi Actuators DAC MCU/MPU Zigbee Energy Harvesting RTC Vref Ethernet Power Mgmt. Audio Codec USB Touch Sensors Freescale Offer External Use 4

6 Comprehensive Portfolio powered by ARM Kinetis Microcontrollers Design Potential. Realized Vybrid Controller Solutions Rich Apps in Real Time. i.mx Application Processors Your Interface to the World. QorIQ Processors built on Layerscape Architecture Accelerating the Network s IQ Industry s most scalable ultra-low-power, mixedsignal MCU solutions based on the ARM Cortex -M4 and Cortex - M0+ architectures. Real-time, highly integrated solutions with best-in-class 2D graphics to enable your system to control, interface, connect, secure and scale. Industry s most versatile solutions for multimedia and display applications, with multicore scalability and market-leading power, performance & integration. Industry s first softwareaware, core-agnostic networking system architecture for the smarter, more capable networks of tomorrow end to end. Consumer Consumer Consumer Networking Industrial Automotive Automotive Industrial Industrial Industrial Freescale has the industry s broadest range of solutions built on ARM technology for automotive, industrial, consumer and networking applications. Find your ideal solution at the price, performance and power level you desire, and leverage the extensive software and tool bundles available to speed and ease your design process. External Use 5

7 Kinetis Portfolio (Now and in the Future ) Performance Available NOW! Kinetis L Series Ultra-low power/cost ARM Cortex-M0+ MCU families from 48MHz / 8KB with mixedsignal, connectivity & HMI features in low pin-count packages. Coming Available 2013 NOW! Kinetis E Series Robust, 5V ARM Cortex-M0+ & ARM Cortex-M4 MCU families for use in high electrical noise environments. Safety features for highreliability applications Available NOW! Kinetis K Series Industry-first ARM Cortex-M4 MCU families from 50MHz / 32KB with low power, FlexMemory, mixed-signal and broad connectivity, HMI & security features. Kinetis X Series High-performance ARM MCU families with advanced memory and feature integration for robust, networked industrial and consumer systems. General Purpose Coming 2015 Coming 2013 (samples now) Kinetis W Series Integrated wireless connectivity ARM Cortex-M4 MCU families with classleading sub-1 GHz and 2.4 GHz RF transceivers Kinetis M Series High accuracy metrology ARM Cortex-M0+ MCU families for single chip smart meter implementations. Coming 2013 (samples now) Kinetis V Series High efficiency, high speed peripherals ARM Cortex-M0+ & Cortex-M4 MCU families for use in motor control & power conversion. Coming 2014 Segment Focused Integration Leading Performance - Low Power - Scalability - Industrial-grade reliability & temp Freescale Bundled IDE, RTOS & Middleware - Rapid prototyping Platform - Broad ARM Ecosystem Support External Use 6

8 Unbound Scalability Smallest size CSP packaging technology - 75% smaller package than the STM32F Products Product breadth M0+ - M4 with 700+ product offerings, 60+ pin for pin compatible devices in each of 3 different packages that span 9 families Lowest power to highest functionality Energy efficient battery powered products to analog intensive medical products products (M0+) 500+ products (M4) External Use 7

9 Kinetis K-Series Product Roadmap ARM Cortex-M4 solutions for a wide range of embedded applications Kinetis K Series 180 MHz 150 MHz K70F K60F / K61F K70F K60F / K61F K70F K70F 120 MHz K64F K60F / K61F K63F / K64F K60F / K61F K24F Performance 100 MHz K10F / K20F K60D K60D K5xD K5xD K30D / K40D K30D / K40D K30D / K40D K10D / K20D K10D / K20D K10D / K20D Production K10F / K20F K70 Graphics K63/K64 Ethernet w/ optional Tamper K60/K61 Ethernet w/optional Tamper K5x Measurement( Medical ) K40 SLCD + USB K30 SLCD 72 MHz 50 MHz K10D / K20D K30D / K40D K30D / K40D K30D / K40D K12D / K22D K12D / K22D K11D / K21D K11D / K21D K10D / K20D K10D / K20D K12D / K22D K11D / K21D K24 USBs MCU w/ extended RAM K2x USB K11 Baseline w/tamper MCUs K1x Baseline 32KB 64KB 128KB 256KB 512KB 1MB Memory Density 2MB External Use 8

10 Kinetis L Series Kinetis L Series Product Roadmap Energy Efficiency, Scalable, Mixed-Signal 32-bit MCUs, Based on ARM Cortex-M0+ TM KL46 KL46 KL46 SLCD + USB w/ 16bit ADC, DAC, TSI, I2S KL36 KL36 KL36 KL34 KL36 w/ 16bit ADC, DAC, TSI, I2S KL34 SLCD Integration & Performance KL26 KL26 KL26 KL26 KL25 KL25 KL25 KL24 KL14 KL24 KL16 KL16 KL16 KL16 KL15 KL15 KL15 KL14 KL26 w/ 16bit ADC, DAC, TSI, I2S KL25 w/ 16bit ADC, DAC, TSI KL24 USB KL16 w/ 16bit ADC, DAC, TSI, I2S KL15 w/ 16bit ADC, DAC, TSI KL14 General Purpose KL05 KL05 KL05 KL04 KL04 KL04 KL02 KL02 KL02 KL05 w/ RTC, DMA, DAC, TSI KL04 w/ RTC, DMA KL02 Entry Level 8KB 16KB 32KB 64KB 128KB 256KB Memory Density External Use 9

11 Kinetis Family Compatibility K L Series 8/16-bit MCU I IIII I IIIIIII KL0 Family M0+ / 48MHz 8KB-32KB 24-48pin I I I I I I I I I I I I I I IIII + USB I IIIIIII K10 Family M4 / MHz 32KB-1MB I I I I I KL pin Family I I M0+ I I / I 48MHz I I I 32KB-256KB 32-80pin + Segment LCD + Ethernet + Encryption + Tamper Detect + DRAM Controller I IIII I IIIIIII I I M0+ I I / I 48MHz I I I I IIII K20 Family M4 / MHz 32KB-1MB I I I I I KL pin Family 32KB-256KB pin I IIIIIII K30 Family M4 / MHz KB I I I I I KL30 Family pin I I M0+ I I / I 48MHz I I I 64KB-256KB pin I IIII I IIIIIII I I I I I I I I I IIII + Graphics LCD K60 Family MHz 256KB-1MB pin I I I I I + Segment LCD I IIIIIII K40 Family M4 / MHz KB I I I I I KL pin Family I I I M0+ I I / 48MHz I I I 128KB-256KB pin + USB I IIII I IIII I IIIIIII K70 Family MHz 512KB-1MB pin I I I I I I I I I IIIIIII K50 Family MHz KB pin I I I I I I I I I I I I I I I I I I + Analog Engine + Ethernet + Encryption External Use 10

12 Kinetis Tools Freescale Microcontroller Enablement Bundle Hardware System + Processor Expert + CodeWarrior IDE + Freescale MQX + Freemaster Complimentary MQX RTOS MQX Core PSP & BSP Open source hardware platform for prototyping application development Create, configure, optimize, migrate, and deliver software components Visual and automated framework to accelerate development time Comprehensive solution for embedded control and connectivity Real-time debug monitor and data visualization tool External Use 11

13 egui: Free Graphics LCD Driver Lightweight software component allowing graphics LCD panels to be driven from small microcontrollers Structure of driver brings complete software solution for applications needing a color LCD screen Touch screen capability -- organization done by screen with high level objects Very light RAM and FLASH footprint egui version MQX RTOS Support Availability: Release 2.1, Available NOW! Full Kinetis support bare metal, MQX, CW10.X support Release 2.2, Available NOW! More low-level drivers (to cover more drivers) including some black & white driver(s) Support for external storage of fonts, texts, bitmaps (i.e. thru file system or ext. memory) External Use 12

14 Xtrinsic Touch-Sensing Software (TSS) 2.6 Freescale s Xtrinsic Touch-Sensing Software (TSS) 2.6 transforms human machine interfaces (HMIs) into robust designs with increased lifetime using expanded MCU cost-saving portfolio for consumer, industrial and medical applications. Features: Support for S8 TSI (for S08PT and S08RN families) MQX Support Kwikstik Support Shielding Memory usage optimization Benefits: Touch detection algorithm for reduced false touches with electrical noise Greater flexibility for product designers to select from more than 1,000 MCUs within Freescale's broad 8-bit to 32-bit portfolio Reliable touch detection using the Touch Sensing Input (TSI) module provides extremely high sensitivity User interface controllers manage multiple keypad layout configurations Simplifies user interface designs, enabling customers to develop an application within minutes using a broad range of tools and demonstration software Reduces overall system cost by simplifying mechanical design and assembly Enhances reliability by replacing mechanical button wear and tear, increasing device longevity Development & Evaluation Tools: TWRPI-TOUCH-PAK ColdFire+ TWR-MCF51QM and TWR-MCF51JF Kinetis KWIKSTIK-K40, TWR-K20D50M, TWR- K40X256, TWR-K53N512, TWR-K60N512, TWR- K60N512-IAR, TWR-K60N512-KEIL, TWR- K70F120M and TWR-K20D72M TWRPI-TOUCH-STR TSS 2.6 SW Specific Version Touch-Sensing Software TSS 2.6 Fact Sheet TSSFS Xtrinsic TSS HTML internal site: TSS CIA: External Use 13

15 Technical Support Tools, Operating Systems and Debuggers Worldwide Expert Support Applications & Reference Designs GNU Tools 1000 s of third party engineers sales people 113 software engineers 300 support engineers 181 applications engineers 74 TIC resources 100 engineers supporting the Community External Use 14

16 Healthcare Analog Front End (AFE) Reference Platform External Use 15

17 Specification Requirement for EKG App. 2x TRIAMP 1x OpAmp configurable as general purpose 1x OpAmp with configurable gain (optional) 2x ADC 16-bit ADC channels (12-bits can be enough) 1x VREF generator 1x DAC (optional for baseline adjust. It can be done by filtering) 1x Timer for sampling control Core supports DSP instructions (Highly recommended) Current project size is 16KB of Flash and 20KB of RAM. This considers filtering and USB communications. Code is not currently optimized for lowest footprint. External Use 16

18 EKG solution Block Diagram External H/W Freescale Chip Internal Module Software Vref Left Electrode Right Electrode VINP1/VINN1 VINP2/VINN2 TRIAMP1 TRIAMP2 TRIOUT1 TRIOUT2 OPAMP 1 OUT1 BandPass Filter (0.5 ~ 250Hz) OPAMP 2 OUT2 Analyze ECG Signal 12-bit 10 th FIR filter 16bits ADC EcgSignal AdcBaseLine Notch Filter 60Hz USB Stack CDC USB PC FIR filter : 8-bits MCU solution : 12-bit 10th order 32-bits MCU solution : 20-bit 51th order External Use 17

19 ZigBee Development Platform For Medical MC1322x GHz ARM7 SiP Full support for ZigBee Health Care with only certified ZHC Stack Variety of Hardware platforms for flexibility including Powerful and Flexible Software IDE 1322x-USB used as Continua Golden Units 2.4GHz 1322x-SRB 1322x-USB 1322x-NCB 1322x-LPB External Use 18

20 Sub 1-GHz Development Tools Sub-GHz MRB Modular Ref Board Feature Developer Kit Tower Kit MRB TWR 2 1 USB Multilink BDM 12311DSK-BDM No CodeWarrior IDE CW 10.x SE No BeeKit Yes No USB Cable Yes Yes Power Adapter Yes No Out of-box Application Range Test N/A TWR Tower Board MSRP USD - PART # TWR KIT $149 TWR $75 Part Number by region with default frequency North America MHz TWR NA TWR KIT-NA Europe MHz TWR EU TWR KIT-EU External Use 19

21 Energy Saving Architecture External Use 20

22 Energy Saving Architecture (1) 90nm Thin-Film Storage (TFS) Technology 1/3 dynamic power reduction vs. existing technologies Flash support for low power modes and fast program/erase times Flash disable option when executing from SRAM Flash doze option to disable during Wait mode (adds ~1us wakeup) Clock and Power Gating Peripheral clocks are disabled by default so there is no wasted power consumption LLS and VLLSx modes shutdown power to most logic maintaining power to energy-efficient peripherals and wake-up sources Automatic platform clocking control in Compute Operation and Partial STOP options further reducing dynamic power consumption External Use 21

23 Energy Saving Architecture (2) Low Power I/O Pin Configuration I/O pins default to a low power configuration disconnecting pin from digital logic eliminating need to configure un-used I/O pins to reduce pin leakage. Low Power Boot Option Configurable power on reset and low power recovery time to eliminate power spikes Bit Manipulation Engine (BME) Intelligent load and store capability for peripheral improved cycle count and smaller code size External Use 22

24 Energy Saving Architecture (3) Peripheral Bridge Crossbar (AXBS-Lite) Support for concurrent accesses from masters (Core and DMA) to slaves (memory and peripherals) Flash Memory Controller (FMC) 4-way, 4-set 32-bit flash cache for reducing flash accesses and eliminating wait states External Use 23

25 Energy Saving Low Power Modes Typical Power Modes in an embedded system Run Wait Cortex M Power Modes Run Sleep Kinetis Extended Power Modes Run VLP Run (VLPR) Wait VLP Wait (VLPW) Stop Freescale Adds Low Leakage Wake-up Unit EnWIC, further reducing leakage currents in all low power modes DeepSleep Supports 16 external input pins and 8 internal modules as wakeup sources Wakeup inputs are activated ables complete shutdown of core logic, including in LLS or VLLS modes Stop VLP Stop (VLPS) LL Stop (LLS) VLL Stop 3 (VLLS3) VLL Stop 1 (VLLS1) VLL Stop 0 (VLLS0) External Use 24

26 Breakthrough Power Efficiency Kinetis Power Modes Recovery Time KL25 Typical 3V and 25C Leading Dynamic Power RUN ma*/ 6.4 ma*** Innovative low power process technology (C90TFS) VLPR ua*/ 980 ua*** Low Power focused Platform Design WAIT 1.6us 48MHz Next Generation Cortex M0+ core VLPW 1.6us 4MHz Asynchronous DMA Wake-up (ADMA) STOP 4.0us 345uA Energy-saving peripherals are operational with ADMA feature that can wake-up DMA to perform transfer and return to current mode when complete VLPS 4.0us 4.4uA Low Leakage Wake-up Unit 4.0us 1.9uA Enables complete shut-down of core logic, including AWIC, VLLS3 further reducing leakage currents in all low power modes 42us 1.4uA Supports 8 external input pins and up to 8 internal modules as wakeup sources; extends the low power wake-up capability of some internal peripherals to all power modes. 93us 700nA Wake-up inputs are activated in LLS or VLLS modes VLLS0 95us 176nA / 381nA *Compute Operation enabled: 48MHz core / 24MHz bus) ** Compute Operation enabled: 4MHz core / 800kHz bus) *** Running Coremark algorithm, KEIL 4.54 optimized for speed LLS VLLS1 External Use 25

27 Kinetis L Series: Run Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Segment LCD 51x8/55x4 External Use 26

28 Kinetis L Series: Very Low Power Run Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 4MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator 16 MHz max LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input Most peripherals are available but may have Clock frequency restrictions. HMI Segment LCD 51x8/55x4 External Use 27

29 Kinetis L Series: WAIT Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Segment LCD 51x8/55x4 External Use 28

30 Kinetis L Series: Very Low Power Wait Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 4MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator 16 MHz max LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Segment LCD 51x8/55x4 External Use 29

31 Kinetis L Series: STOP Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Partial STOP modes allow additional peripherals to operate but with added current. Segment LCD 51x8/55x4 External Use 30

32 Kinetis L Series: Very Low Power STOP Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Segment LCD 51x8/55x4 External Use 31

33 Kinetis L Series: Low Leakage STOP Mode System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI Most peripherals are static but remain powered Segment LCD 51x8/55x4 External Use 32

34 Kinetis L Series: Very Low Leakage STOP Mode 3 System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input GPIO states are latched on VLLSx entry. GPIO must be manually released by software on VLLSx exit. Exit through reset flow, default FEI clock mode. Most peripherals are powered down. HMI Segment LCD 51x8/55x4 External Use 33

35 Kinetis L Series: Very Low Leakage STOP Mode 1 System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input RAM is powered down and voltage regulator is turned off. HMI Segment LCD 51x8/55x4 External Use 34

36 Kinetis L Series: Very Low Leakage STOP Mode 0 System Clock Management Energy Management ARM Cortex-M0+ Core Ultra-low power 48MHz core freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low & high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Communication Connectivity I/O Ports ADC (SAR w/ DMA) 12/16-bit, up to 16ch 12-bit DAC HSCMP PIT 2ch, 32bit RTC Temp. Compensated 16b LPTPM 6ch x1, 2ch x 2 LPTMR UART x2 LPUA RTx1 SPI x 2 I2C x 2 IIS x1 USB FS/LS Transceiver USB Controller V Regulator TSI x 1ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input HMI All clocks are disabled. CMP and slcd disabled. Segment LCD 51x8/55x4 External Use 35

37 Ultra-Low Power Modes Expands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applications RUN SLEEP DEEP SLEEP Mode Run VLP Run (VLPR) Wait VLP Wait (VLPW) Stop VLP Stop (VLPS) LL Stop (LLS) VLL Stop 3 (VLLS3) VLL Stop 1 (VLLS1) VLL Stop 0 (VLLS0) Definition MCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational. MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed. Allows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option. Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option. MCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active. MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU. MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up. MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode. Similar to VLLS3 with no RAM or register file retention. Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry. External Use 36

38 Measurement Engine External Use 37

39 Analog peripherals on Kinetis Common Features 16-bit ADC High-Speed Comparators VREF Family dependent PGA 24-bit OPAMP TRIAMP 12-bit DAC 24-bit ADC only available on Kinetis M OPAMPs and TRIAMPs only available on Kinetis K5x External Use 38

40 16-bit SAR ADC DMA support Single-Ended or Differential inputs Operation in low power modes Hardware conversion trigger Hardware average (4,8,16,32) Hardware compare (2 thresholds) External or internal voltage reference ENOB = 14.5 (16-bit differential) Self-calibration External Use 39

41 Comparator Rail to rail inputs 6-bit DAC for supply reference source Selectable interrupt: rising, falling or both edges Wide range of outputs: sampled, windowed, digital filter DMA transfer support Functional in all modes of operation [1] Window & Filter functions are not available on Stop,VLPS,LLS,VLLSx External Use 40

42 Programmable Gain Amplifier Designed to increase Dynamic Range Amplifies low-amplitude signals before they are feed to the 16-bit SAR ADC PGA ADC V mv pp mv mv 600 mv PGA_DP 0.7 V ADC16_DP 1.2 V LSB 0.2 V 0.7 V 0 V PPADC,DIF = mv pp Gain = V 0.2 V LSB mv 600 mv PGA_DM 0.7 V ADC16_DM mv mvpp V External Use 41

43 24-bit ADC 24-bit (after averaging) ADC with PGA Option to bypass the PGA PGA with 7 µa sensitivity Single ended or Differential mode ±250 mv (1 V pp differential, 0.5 V pp single ended) input range DMA request on conversion complete External Use 42

44 TRIAMPs & OPAMPs Signal conditioning OPAMPs provide internal gain options OPAMPs configurable inputs Spec. for limited temperature range ( 0 C to 50 C ) Electrical OPAMP TRIAMP Offset current ±3 mv ±3 mv Offset voltage ±500 pv ±300 pv Bias current ±500 pa ±300 pa Input range 0 to V DDA -0.1 to V DDA -1.4V External Use 43

45 12-bit DAC On-chip programmable reference generator output Voltage range from 1/4096 V IN to V IN V IN can be selected from two reference sources (internal, external) DMA support External Use 44

46 Sampling with the Best Current Consumption Sample 2 ADC inputs at 48ksps without CPU load INA INB 96 ksps ADC0 DMA0 Result 1A Result 1B Result 2A Result 2B RUN mode DMA1 INA INB 48 ksps ADC0 ADC1 48 ksps I DD DMA0 DMA1 I DDA Run 20.8 ma 186 ua VLPR 3.01 ma 488 ua Result Buffer A Result Buffer B VLPR mode External Use 45

47 Precision Analog Improves Accuracy The challenge Increase device accuracy without increasing cost. The FDA is requiring higher accuracy on most medical devices and changes to healthcare provide significant cost pressure. The solution Integrated precision analog. Integrating precise analog components such as Op Amps, Tri Amps, high resolution ADC, and DACs. Ideal solution Platforms w/ Flexible Analog Freescale offers customers fully integrated analog solutions that are pin compatible and scalable. Freescale solutions contain key analog peripherals needed to connect to a custom analog ASIC. External Use 46

48 Product Longevity Freescale has a product longevity program for the market segments that we serve. For the automotive and medical segments, Freescale has a broad range of devices available for a minimum of 15 years For all other segments in which Freescale participates, Freescale has a broad range of devices available for a minimum of 10 years Life cycles begins at the time of launch. A list of participant products is available at External Use 47

49 Freescale Semiconductor, Inc. External Use