Denis Cabrol. Kinetis Global Marketing Manager

Transcription

1 Denis Cabrol Kinetis Global Marketing Manager June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc..

2 Overview & positioning ARM Cortex-M0+ processor Energy efficiency, ease-of-use & scalability MCU Families Availability Enablement Summary 2 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

3 Feature rich Easy-to-use Connectivity Extended battery life Sleek design User expectations 3 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

4 8-/16-bit MCU 32-bit MCU Connectivity User Interface Power Consumption Computation Software/Cost of Ownership Ultra low sleep/ power-down currents + - Unique platforms, MCU dependent/$$$ Maximum energy-efficiency (CoreMark/mW) n x sin log n Scalable, reusable platforms with modern software techniques/$ Scalability Limited choice, single-source Broad MCU portfolios, multi-source 4 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

5 Productivity Large Ecosystem Stacks RTOS BSP Tool chains Libraries Easy to use 5 Ready-made Components Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

6 32-bit Energy-efficiency Class-leading Coremark/mW Scalability & Integration Kinetis L to K Series (Cortex M0+ to M4) Enablement Freescale bundle + ARM ecosystem Kinetis L Series The evolution of the entry-level MCU 8-bit Low Static Power <1uA power modes Low cost From <$0.50 Ease-of-use Freedom Platform, Processor Expert & MCU Solution Advisor 6 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

7 Freescale and ARM collaborated to develop a revolutionary processor that extends battery life by improving energy-efficiency, enables advanced peripherals and software by increasing processing performance and reduces system cost by improving code density Freescale s MCU experts helped define key 8-bit-like processor features including ease-ofuse ARM Cortex-M0+ processor successfully integrated into first Kinetis L Series MCU platform - now sampling to alpha customers Freescale MCU roadmap fully aligned with ARM Cortex architecture from entry-level Kinetis L series, to high-performance Kinetis K/X series with broad performance, memory and feature scalability 7 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

8 Performance 8-/16-bit Older, slower architectures & technology Increased code size/complexity when performing complex math operations Energy-Efficiency Low energy-efficiency Low Cost 6-35kgates Variable code density Ease-of-Development Limited addressable memory Simplistic interrupt controllers Limited scalability (MHz, flash, features) Limited ecosystem support Performance 8 32-bit ARM Cortex-M0+ 2x to 40x more than 8-/16-bit, 9% more than Cortex-M0 Fast 32-bit math processing Fast, single-cycle access to I/O Energy-Efficiency >2x CoreMark/mA than closest 8-/16-bit MCU, +30% / CM0 Low Cost 12-35kgates Excellent code density Ease-of-Development Linear 4GB address space no need for paging Full-featured interrupt controller simpler s/w architecture Huge scalability h/w and s/w reuse across end products Huge ARM ecosystem off-the-shelf software/tools/training Micro Trace Buffer lightweight, non-intrusive trace Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

9 Energy Efficiency 2-stage pipeline reduced cycles per instruction (CPI) enabling faster branch instruction and ISR entry Program memory access on alternate cycles Single-Cycle I/O Port 50% higher GPIO toggling frequency than standard I/O Improves reaction time to external events allowing bitbanding and software protocol emulation Save precious cycles, e.g. set faster peripherals for low-power access Access GPIO/peripherals while processor fetches the next instruction Processing Only 56 Instructions, mostly coded on 16-bit. Option for fast MUL 32x32 bit in 1 cycle Cortex-M0/3/4 compatible 1.77CM/MHz Best-in-class code density vs. 8-/16-bit architectures reduced cost, power consumption and pin-count Micro Trace Buffer Powerful, lightweight trace solution enabling fast debug Non-intrusive trace information stored in small area of MCU SRAM (size defined by programmer) Trace read over Serial Wire /JTAG (CPU stopped) 9 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

10 Ultra-efficient processing ARM Cortex-M0+ Processor 90nm low-power flash technology Bit Manipulation Engine <50uA/MHz, 3.8CM/mW Peripheral Bridge Crossbar Zero Wait State Flash Memory Controller Ultra low-power modes Energy-saving peripherals 90nm low-leakage flash technology Multiple RUN, WAIT and STOP modes 4us wake-up from deep sleep modes Clock & power gating, low-power boot options 2uA Deep Sleep Idd with register retention, LVD active and 4.3us wake-up Smart peripherals function in deep sleep modes and can make intelligent decisions and process data without waking up the core ADMA, UART, Timers, ADC, Segment LCD, Touch Sensing... Most Innovative Process Technology Kinetis ARM Cortex-M4 MCUs 10 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

11 NEW Freedom Platform Processor Expert MCU Solution Advisor Low -cost/power platform for entry-level developers ($12.95 / 10 SRP) Arduino form-factor compatible with multiple expansion options (shields) Open SDA new debug i/f for flash programming and run-control Free software generation tool for device drivers / startup code 7 steps from project creation to debug dramatically reduces development time Available standalone or as an IAR/Keil/GNU IDE plug-in Web-based interactive MCU product selector Selects MCU based on operating characteristics, packaging, memory configuration & peripherals. Verifies muxing compatibility Save, download and print summary reports and pin muxing configurations GNU 11 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

12 Feature Integration Kinetis X Series ARM Cortex M4 200MHz Kinetis K Series ARM Cortex M MHz Kinetis L Series ARM Cortex M0+ 48MHz K50 Family MHz, KB, Analogue, USB OTG (FS), E net, SLCD, Encryption K40 Family MHz, KB, USB OTG (FS), SLCD K30 Family MHz, KB, Segment LCD K20 Family MHz, 32KB-1MB, USB OTG (FS/HS) KL2 Family USB OTG (FS) KL0 Family 8-bit S08P compatible K10 Family MHz, 32KB-1MB, Low Power, Mixed Signal KL1 Family General Purpose KL4 Family USB OTG (FS), SLCD KL3 Family SLCD K60 Family MHz, 256KB-1MB, Ethernet, USB OTG (FS/HS), Encryption, Tamper Detect, DRAM Kinetis X Series K70 Family 120/150MHz, 512KB-1MB, Graphics LCD, Ethernet, USB (FS/HS) Encryption, Tamper, DRAM <=24pin 32pin 48pin 64pin 80pin 100pin 121pin 144pin 256pin Pin Count 12 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

13 HSCMP ADC DAC/ADC HSCMP GPIO etc. SWD TSI GPIO etc Digital Power HSCMP ADC VREFOUT Clock (32K) Vbat SWD JTAG TSI GPIO etc Digital Power ADC GPIO etc LLWU GPIO ADC GPIO etc LLWU GPIO Digital Power USB ADC DP Ch GPIO etc. 48 KL25 48-pin 37 ADC/TSI GPIO etc. Reset GPIO Fully Hardware Compatible Follow Same Pin Assignment Rule Digital Power USB ADC DP Ch 48 K20 48-pin 37 ADC/TSI GPIO etc. Reset GPIO Analog Power Clock GPIO etc Same Peripheral Register Setting for common features Analog Power Clock (3~32M) GPIO etc Software Compatible, C-Code Reusable Take 3 Steps for easy Migration: Step 1 Check Hardware difference Power Pin (Vbat) External Clock Input (32KHz/3~32MHz) Analog interface (DAC, Vref_Out) Debug Interface (JTAG) GPIO pinmux Step 2 Check Software difference DMA configuration Watchdog Service Routine Low Power usecase (New features added on L-Series) BME (new on L-Series) MTB (new on L-Series) GPIO Map (More on L-Series) Flexmemory (K-Series only) * Detail technical migration guide will be available on Freescale Launch Date Step 3 Optimize the Design Adopt new head file and reuse the C code by modifying the difference Add new features support in design that specific to L- Series or K-Series 13 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

14 System Unique ID Clock Management Energy Management CM0+Core Ultra-low power 48MHz bus freq. Debug (SWD) COP RST LPO (1KHz) Crystal Oscillator (low&high range) LS Osc (32KHz) Voltage Regulator Flash 8-256K RAM 1-32K DMA 4-ch FLL PLL ULP Osc (4MHz) Power On Reset Low Voltage Detector Peripheral Bus Analog Interfaces Timers Connectivity USB OTG I/O Ports 4chDP+ 8chSE 16-bit / 16chSE 12bit SAR ADC /w DMA 12-bit DAC HSCMP 2ch 32bit PIT SRTC w/ temperature compensation 16b LPTPM 6ch x1, 2ch x 2 LPR SCI x2 LPSCI x1 SPI x 2 I2C x 2 I2S x1 FS/LS Transceiver [5] USB Controller V Regulator TSI x 16ch Up to 80 GPIO (4 High Dive) w/ 25 interrupt RST/ Input Operation in: Run Wait Stop/ VLPS VLLS 3 VLLS 1 VLLS 0 Display 47x8/51x4 14 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

15 Available 2012, up to 128KB Available 2013, up to 256KB Common Features System ARM Cortex-M0+ Core, 48MHz Multiple low-power modes, Clock Gating, 1.71V - 3.6V Operating Temp: -40 to 105 C [1] Memory 90nm TFS Flash, SRAM Internal Memory Security/Protection Family Flash SRAM Optional Features USB OTG Seg. LCD DMA Cross- Bar Key Features ADC DAC I2S TSI KL KB 16-32KB 16-bit 12-bit KL KB 8-32KB 16-bit 12-bit KL34 64KB 8KB 12-bit Analog Peripherals 12/16-Bit ADC High-Speed Comparators Serial Interfaces KL KB 16-32KB 16-bit 12-bit KL KB 4-16KB 16-bit 12-bit KL KB 4-8KB 12-bit SCI (Including 1 LPSCI) SPI, IIC Timers Real Time Clock [2] KL16 256KB 16-32KB 16-bit 12-bit KL KB 4-16KB 16-bit 12-bit KL KB 4-8KB 12-bit 16bit Low Power TPMs (GP Timer/PWM) Low Power Timers 32bit Periodic Interrupt Timer KL KB 1-4KB 12-bit 12-bit KL KB 1-4KB 12-bit KL KB 1-4KB 12-bit [1] Feature not available on CSP packages [2] For KL02, use software to support 15 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

16 Flash Memory Flash Memory 256KB USB + Seg. LCD Segment LCD USB General Purpose Entry Level KL4x KL3x KL1x KL1x KL4x KL3x KL4x KL4x 128KB KL3x KL3x KL1x KL1x KL1x KL1x KL1x KL3x KL3x 64KB KL1x KL1x KL1x KL1x KL1x 32KB KL1x KL1x KL1x KL1x KL1x KL0x KL0x KL0x KL0x KL0x 16KB KL0x KL0x KL0x KL0x KL0x 8KB KL0x KL0x KL0x KL0x <24 pin* * Under Proposal 24 QFN 25 WLCSP* 32 LQFP/ QFN 35 WLCSP* 16 Package 48 LQFP/QFN 64 LQFP / MBGA 80 LQFP 100 LQFP/ 121 MBGA Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

17 Common Packages Kinetis K Series Package Kinetis L Series Package *Proposed *Proposed 32QFN 5 x 5 mm 0.5mm pitch (K10/20) (KL0/1/2) 48QFN 7 x 7 mm 0.5mm pitch (K10/20) (KL1/2) 32LQFP 7 x 7 mm 0.8mm pitch (K10/20) (KL0x) 48LQFP 7 x 7 mm 0.55mm pitch (K10/20) (KL0) 64LQFP 10 x 10 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2/3/4) 80LQFP 12 x 12 mm 0.5mm pitch (K10/20/30/40/50) (KL1/2) 100LQFP 14 x 14 mm 0.5mm pitch (K10/20/30/40/50/60) (KL2/3/4) Kinetis K Series only 64MAPBGA 5 x 5 mm 0.5mm pitch (K10/20) (KL1*/2*/3*/4*) 121MAPBGA 8 x 8 mm 0.65mm pitch (K1/2/30/40/50/60) (KL2/3/4) Kinetis L Series only New 56CSP 3 x 3 mm 0.4mm pitch (K10*/20*) New 90CSP 4 x 4 mm 0.4mm pitch (K10*/20*) New 121CSP 5 x 5 mm 0.4mm pitch (K10/20/60) New 143CSP 6 x 6 mm 0.4mm pitch (K61) New New New 25CSP 2.35 x 2.88 mm 0.4mm pitch (KL0*) 35CSP <3 x 3 mm 0.4mm pitch (KL1*/2*) 24QFN 4 x 4 mm 0.5mm pitch (KL0) 144LQFP 20 x 20 mm 0.5mm pitch (K10/20/30/40/50/60) 144MAPBGA 13 x 13 mm 1.0mm pitch (K10/20/30/40/50/60) 256MAPBGA 17 x 17 mm 1.0mm pitch (K60/70) 17 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

18 Pricing from $ ,000 units Product Family Public Announcement Flash Memory General Market Availability Volume Production KL KB Q KL1 KL KB KB Q Q KL1 19 June KB KL2 KL3 256KB KB Q Q KL KB 18 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

19 ARM Cortex-M0+ Processor 2-stage pipeline, reduced interrupt latency, industry-leading CoreMark/mA 90nm TFS low-power Flash 1/3 dynamic power reduction vs. other flash technologies, high-reliability charge storage Full flash & analog operation from 1.71V Bit Manipulation Engine Offloads CPU from Read-Modify-Write ops. <50uA/MHz VLPR RUN mode processing capability with sleep mode power consumption Peripheral Bridge Crossbar Concurrent accesses from masters (Core/DMA) to slaves (memory/peripherals) New Compute Operation Feature Power Mode Recovery Time Typical Idd Range est. Leading Dynamic Power RUN - 84uA/MHz* Very Low Power Run VLPR - 50uA/MHz** * All Modules Off enabled: 48MHz core / 24MHz bus) ** All Modules Off enabled: 4MHz core / 1MHz bus) 19 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

20 Power ENERGY SAVINGS Very Low Active and Standby Power Consumption Energy Saving Peripherals Reduced Processing Time Initialization Collect Data Compute DEEPSLEEP Modes support Functionality during DEEPSLEEP Transmission and reception of UART signals Kinetis L-Series Generation of PWM signals and/or input capture functionality Triggered Comparator and or ADC conversions All Deep with Sleep the Mode capability of triggering Asynchronous DMA request that can transfer data with minimal latency and return to 48 MHz 84 ua/mhz DEEPSLEEP 4 MHz 50 ua/mhz Tx/RX IC/OC Analog Time VLLS0 Deep LLS Deep UART TIMER Analog and More 150 na 1.4 ua CORE, Interrupts RESET System User CLK Control Peripheral Bus Standard peripherals CoreMark/MHz 1.77 LLS Wake-up Time RAM FLASH DMA 4-ch 4.6 us 20 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

21 Low-leakage 90nm TFS Flash Multiple, flexible power modes Precise control of peripherals and wake-up sources/times to suit power budget Ultra-fast recovery time Rapid, 4us transition time from Deep Sleep to Run modes Minimize average power consumption in frequent power mode change applications Low Leakage Wake-up Unit Full shutdown of core logic extends low power wake-up capability of some peripherals to all power modes Power Mode Recovery Time Typical Idd Range est. LLS 4.6us From 1.4uA VLLS3 53us From 1uA VLLS1 115us From 640nA VLLS0 115us From 150nA Asynchronous DMA 21 Allows peripherals to trigger asynchronous DMA requests in STOP/VLPS without CPU intervention Communications UART, SPI, IIC, USB support wake-up function down to STOP/VLPS modes Mixed-Signal ADC single conversions in STOP/VLPS modes with hardware averaging and automatic compare ACMP triggered compare mode for lower average power compares DAC static reference in all modes Timing Low Power Timer input capture, output compare and PWM in STOP/VLPS modes RTC low power operation with temperature & voltage compensation User Interface Segment LCD & Touch Sensing Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

22 Benchmark Results Ultra-low Active Current Fast Processing Kinetis L Series energy efficiency: Ultra-efficient Cortex-M0+ core Energy-saving architecture Flexible ultra-low power modes Kinetis L Series x Microchip PIC24 MCU CoreMark/mA TI MSP430 Renesas RL78

23 Ultra low -cost/power development platform Quick, simple development experience Easy access to MCU I/O Battery-ready, power-measurement access points Form factor compatible with Arduino platform New, sophisticated OpenSDA Debug interface Mass storage device flash programming interface (default) no tool installation required to evaluate demo apps P&E Multilink interface provides run-control debugging and compatibility with IDE tools Open-source Data Logging application provides an example for customer, partner and enthusiast development on the OpenSDA circuit Loaded with software: Processor Expert: stand-alone or IDE integrated MQX Lite RTOS (via Processor Expert) Ecosystem partner support IAR, Keil, Code Red, Atollic, Rowley, Free GNU commandline tools with GDB server Features: MKL25Z128VLK4 MCU 48MHz, 128KB Flash, 16KB SRAM, USB OTG (FS) OpenSDA sophisticated USB debug interface Capacitive touch slider, MMA8451QR1 accelerometer, Tri-color LED Flexible power supply options USB, coin cell battery, 3.3/5V Available: 25 Sept 2012 $12.95/ 10 SRP GNU 23 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

24 1 Create Project 3 Configure Components Use Inspector to set all component settings 5 Generate Code Processor Expert generates components 7 Steps 7 Build & Debug Build the application Debug the application Software Development Timeline 2 4 Add Components Add components to the project from Components Library Verify Settings Verify no design-time errors in the project 24 6 Write Application Code Write application code using code generated for components Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

25 Features: Web-based application that features an interactive MCU product selector. Identify the best MCU by applying dynamic filters based on: Operating characteristics Packaging options Memory configuration Peripheral hardware library Verify pin muxing compatibility Identify compatible and relevant Tower System modules Save, restore an share sessions for reviewing and critiquing design possibilities View, download and print summary reports and pin muxing configurations 25 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

26 Summary Freescale is leading the development of next generation ARM-based MCUs in the embedded market Kinetis L Series Cortex M0+ MCUs offer a game-changing combination of energyefficiency, ease-of-use and value as well as scalability into the existing Kinetis K Series ARM Cortex-M4 MCU portfolio Freescale is demonstrating the Kinetis L Series at FTF June 2012 and has started its global alpha customer program Devices within the Kinetis L Series MCUs will be launched to the mass market in September and in full production by the end of Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

27 Thank you Facebook.com/Freescale Tag yourself in photos and upload your own! Tweeting? Please use hashtag #FTF2012 Session materials will be Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter 27 Ready Play, SafeAssure, the SafeAssure logo, SMAROS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

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