Hardware Implementation of StrongARM Processor Interface Using Verilog and FPGA

Transcription

1 Hardware Implementation of StrongARM Processor Interface Using Verilog and FPGA Toufiq.Rahman, Rifat. Zaman, Syeda. Nowreen and Iqbalur. Rahman Abstract In this paper, the design of StrongARM processor interface and its hardware implementation are described. A target device FIFO is connected to the bridge/interface to perform read/write operation through the designed interface. All the major signals of StrongARM protocol are used in this design. First, a block diagram is shown with some sub-blocks. Then a flow of interaction of sub-blocks is presented. Afterwards, the flow of design of the testbench, StrongARM interface, and FIFO is shown starting from the top level. Next, hand-drawn waveforms of all associated signals are given. Then comes the heart of the design the state machine. After that, simulation results are shown and in the end, conclusion is drawn discussing some areas of possible improvement in the future. T Keywords-StrongARM Protocol, FIFO, FPGA, Verilog. I. INTRODUCTION HE StrongARM was a collaborative project between DEC and Advanced RISC Machines to create a faster ARM microprocessor. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistants and set-top boxes [1]. StrongARM offers a low cost, low power, elevated performance processor that will permit more multifaceted applications to work in handheld devices. The SA-110 also grants a new level of performance for low cost embedded processors. Past designs have emphasized performance without major concern for power dissipation. Since it was intend for the portable market, this design needed the maximum performance possible for 0.5W or less.sa-110 can perform in 160 MHz at 1.5V and below 0.5W. SA-110 needs an interface to connect every single slave device. This interface will create the communication between master and slave devices. The Intel SA-1111 companion chip, a highly integrated and power efficient component, brings a new level of integration to portable applied computing devices and enables key attributes such as reduced component count, low power dissipation and high performance [2].The SA-1111 also enables direct memory access to SDRAM system memory, reducing SA-1110 processor intervention and increasing I/O performance. To provide maximum design flexibility, reduce design time and lower cost, the Intel SA-1111 companion chip integrates a broad spectrum of I/O interfaces. The advanced interfaces and features of the Intel SA- 1111companion chip offer broad flexibility to support multiple cost-effective handheld configurations while minimizing time-to-market constraints [3]. The selective clock-gating feature and three power-down modes (idle, doze, and sleep) of the Intel SA-1111 minimize system power requirements [4]. The SA-1111 can power down individual functional blocks that are not in use and power them up quickly when they are needed. The SA-1111 is packaged in a 256-pin mbga and supported by a rich suite of Intel and third-party hardware and software development tools. II. INTERFACE TOP BLOCK DIAGRAM Toufiq. Rahman studied at North South University, Electrical ullash_nsu@yahoo.com Rifat. Zaman studied at North South University, Electrical Engineering & Computer Science department, Dhaka, Bangladesh. rzaman00@gmail.com Syeda. Nowreen Studied at North South University, Electrical stnprioom@yahoo.com Iqbalur. Rahman lecturer at North South University, Electrical irahman@northsouth.edu Fig.1 Block diagram A. State Machine This is a vital block for the interface. It determines when different output/inout signals will come in effect. Two most significant signal of this block is nextstate and currentstate 136

2 both of which are 3 bit signals. To generate nextstate some other signals are needed like nwe, registered version of nwe (rgswrite), ncs and currentstate as well. nextstate and currentstate are used as internal input signals in other blocks. IV. DESIGN FLOW B. Data Bus Controller This block handles the data bus signal D which is a 32-bit signal. It receives the input from D during write operation and drives D with proper value during read operation. This block is affected by the state machine and internal signal generator as well. Asynchronous reset is used here. C. Address Bus Controller This block deals with the 26-bit address bus A. This block affects control output/inout signal generator section as the value of noe depends on the signal A. D. Internal Signal Generator This is an important section that deals with generating the internal signals like Dreg, rgswrite, noereg, wdata, rdata etc. These signals contribute to generate the final outputs/inouts and also to switch states. This block is directly affected by the state machine. E. Control Output/Inout Generator This section is in the charge of generating inout signal noe (while acting as output), and two other control output signals RDY and MBREQ. This block is affected by almost all other blocks. Fig.3 Design flow V. HAND-DRAWN TIMING DIAGRAM III. FLOW OF INTERACTION OF SUB-BLOCKS Fig. 4 Hand-drawn waveforms Fig.2 Interaction-flow of sub-blocks 137

3 This state is indicated by the binary value 000 in the code. B. READ State During this state, the control inout signal noe is kept low. The READ state is entered from IDLE, READOK, WRITEOK or PNDWRITEOK during a valid read transfer. The next state will always be READOK. This state is indicated by the binary value 001 in the code. VI. Fig.4 continued STATE MACHINE DETAILS C. WWRITE State This state is required due to the pipelined structure of StrongARM protocol transfers. This state is entered from IDLE, READOK or WRITEOK during a valid write transfer. The next state will be: - WRITE if there is no more transfer request for the interface. - PNDWRITE if there is another valid transfer request for the interface. This state is indicated by the binary value 010 in the code. Fig.5 State machine A. IDLE State This is the initial state of operation. - nreset = 0 when the system is initialized. - READOK, WRITEOK or IDLE, when there are no peripheral transfers to - READ for a read transfer when the bridge contains a valid read transfer request. - WWRITE for a write transfer when the bridge contains a valid transfer request. D. WRITE State During this state, noe is driven high. - WWRITE when there is no further peripheral - PNDWRITEOK when the currently pending peripheral transfer is a write and there is no further transfer to - WRITEOK when there is no further peripheral - PNDWRITEOK when there is a further peripheral write This state is indicated by the binary value 011 in the code. E. PNDWRITE State During this state, noe is driven high. - WWRITE when there is a further peripheral transfer to - PNDWRITEOK when the currently pending peripheral transfer is a write, and there is a further transfer to The next state will always be PNDWRITEOK. This state is indicated by the binary value 100 in the code. 138

4 F. READOK State During this state the control output signal RDY is driven high enabling the current StrongARM transfer. noe remains the same as the previous cycle. The READOK state is always entered from READ. - READ when there is a further peripheral read - WWRITE when there is a further peripheral write - IDLE when there is no further peripheral transfer to This state is indicated by the binary value 101 in the code. G. WRITEOK State During this state, RDY output is driven high, enabling the current StrongARM transfer. noe remains the same as the previous cycle. This state is always entered from WRITE. - READ when there is a further peripheral read - WWRITE when there is a further peripheral write - IDLE when there is no further peripheral transfer to This state is indicated by the binary value 110 in the code. H. PNDWRITEOK State During this state RDY output is driven high, enabling the current StrongARM transfer. noe remains the same as the previous cycle. - WRITE when there is a valid transfer request from the ASB side. - PNDWRITE. - READ when the pending transfer is a read. - WRITE when the pending transfer is a write and there is no further - PNDWRITE when the pending transfer is a write and there is a further This state is indicated by the binary value 111 in the code. VII. SIMULATION ENVIRONMENT Fig.6 Simulation environment It should be noted that Verilog HDL is used to implement the interface and to generate proper output/inout signals from different input/inout signals [5]. VIII. SIMULATION RESULTS Fig.7 Simulation results Fig.7 Continued 139

5 IX. CONCLUSION This paper presents an efficient design of StrongARM processor interface. The authors are really satisfied with it. They learnt a lot of things regarding basic StrongARM bus, different features and signals associated with StrongARM protocol, and learnt more in-depth about the verilog HDL coding. Still, there is some room for improvement in this paper. To name a few: burst transfers are not shown here. The size of StrongARM data bus and the size of FIFO data bus are same (32 bits). In future the authors are interested to develop the interface for burst transfers. Also, they want to use memory storage elements (RAM, register, FIFO etc.) with different data bus size in comparison with StrongARM data bus size. ACKNOWLEDGMENT At first, the authors would want to thank the Almighty Allah for giving them the strength and courage to begin and complete this paper. Then they would like to mention their parents who supported them with mental and financial support. They also convey their gratefulness to Dr. Abdul Awal, the Chairman of the EECS Department of NSU, for helping them with his wise advice. They also thank all those people who helped them in anyway regarding this paper and enriched them with different ideas and a lot of support. REFERENCES [1] StrongARM [2] Intel StrongARM SA-1111 Microprocessor Companion Chip (ADVANCE INFORMATION Brief Datasheet) [3] Intel SA-1111 Companion Chip- Integrated Technology for Full- Featured, Versatile Designs [4] Intel StrongARM Processor, Companion Chip Optimized for Handheld Computing Devices [5] Palnitkar, S. (2006). A Guide to Digital Design and Synthesis (2 nd ed). India: Dorling Kindersley Pvt. Ltd. 140