Bus Interfaces and Standards. Zeljko Zilic

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1 Bus Interfaces and Standards Zeljko Zilic

2 Overview Principles of Digital System Interconnect Modern bus Standards: PCI, AMBA, USB Scalable Interconnect: Infiniband Intellectual Property (IP) Reuse Reusable Design

3 System Buses/Backplanes Systematic way to create extendible and open hardware systems Also: to reduce prices, reuse designs, reach market Standardization: the key Industry associations (USB, PCI) Standardization bodies (IEEE488, Firewire) Standard content: Physical, Mechanical, Electrical and Logical Example: PC Platform PCI, ISA, USB, RS232, SCSI, IDE, Ethernet, V.52, VGA, Rambus, Infiniband, AGP

4 Bus Principles Quick and fair access to shared resources Bus (Interconnect), Memory, IO, Processors Example: PC Platform

5 Bus Realizations Shared interconnect Bus, Crossbar, Ring Signalling lines used for exchanging info, control of the access Arbitration: fair bus access Handshake: managing transfers Address, data lines Error, reset, watchdog

6 Synchronous vs. Asynchronous Original buses: asynchronous handshake VME, IEEE 488, SCSI 1 (but not SCSI 3) Example of async. handshake

7 Synchronous bus Virtually all modern buses Transactions relative to positive clock edge

8 Arbitration Arbitration for accessing bus Centralized Decentralized

9 PCI Bus Dominant standard Not only PCs, but also communication systems, embedded systems Organization:

10 PCI Signalling Lines 32-bit multiplexed Address/Data bus 4-bit command field transaction type/byte enable Handshaking Error, reset, clock Extension: 64 bits Testing interface (JTAG)

11 PCI Transactions Read: Send address Turn around the bus Get data Write: Send address Send data Notice use of RDY and SEL signals Single-cycle turnaround

12 AMBA Overview AMBA Bus Basics AMBA Signals AMBA High Performance (AHB) Specification Timing Diagrams Testing Interface

13 Introduction to AMBA Bus Acorn RISC Machine ARM Processor for Acorn home computer Acorn filed for bankruptcy ARM reinvented ARM leading embedded microprocessor Licensed to all ASIC houses for SoC Produced by Intel (formerly by DEC) - StrongARM Advanced Microcontroller Bus Architecture Specification by ARM, open to others Several bus standards

14 AMBA Concepts 3 Ways of creating buses: Tri-state (internal tri not available in some ASICs) Multiplexer-bus OR-bus (with AND gate enablers) 3 Standards Advanced High Performace Bus (AHB) Advanced System Bus (ASB) Advanced Peripheral Bus (APB) Recommendations: use AHB

15 AHB AMBA Bus No physical level standard (any voltage/technology) Suited for SoC synthesized designs from HDL High clock rate Pipelined access Multiple bus masters Burst transfers Split transactions Separate read and write buses

16 AMBA Implementation Arbiter and global decoders: standalone Add-on components: master or slave Interface: added to add-on components M_IN S_IN MAIN BUS CONTROLLER: ARBITER AND DECODER MAIN BUS CLOCK DOMAIN MASTER INTERFACE MASTER DEVICE #1 MASTER DEVICE #1 CLOCK DOMAIN SLAVE INTERFACE SLAVE DEVICE #1 M_OUT S_OUT SLAVE DEVICE #1 CLOCK DOMAIN

17 AMBA Signals Input: HGRANT HREADY HRESP[1:0] HRDATA[15:0] Comment: A master gets control of bus when HGRANT is high and HREADY is high. Receives HREADYOUT signal from active slave indicating wait states or completion. Response from slave indicating status of transfer. Read data to master. Output: HBUSREQ HTRANS[1:0] HADDR[15:0] HWRITE HSIZE[1:0] HBURST[2:0] HWDATA[15:0] Comment: Must be maintained high during a burst of undefined length. Transfer state, must give IDLE if nothing to transfer: a master may be selected if no masters want the bus. Target address for transfer. Write transaction when high and read when low. Size of transfer: 01 is 16 bits. Only 16 bits supported. Burst type: 000 is single, 001 is unspecified length burst, others are 4, 8 and 16 beat bursts (wrapping or non-wrapping). Write data from master.

18 Bus Signals - Master type AHB_Mst_In_Type is record HGRANT HREADY HRESP[1:0] HRDATA[15:0] end record; type AHB_Mst_Out_Type is record HBUSREQ HTRANS[1:0] HADDR[15:0] HWRITE HSIZE[1:0] HBURST[2:0] HWDATA[15:0] end record;

19 Bus Signals - Slave type AHB_Slv_In_Type is record HSEL HADDR[15:0] HWRITE HTRANS[1:0] HSIZE[1:0] HBURST[2:0] HWDATA[15:0] HREADY end record; type AHB_Slv_Out_Type is record HREADYOUT HRESP[1:0] HRDATA[15:0] end record;

20 Bus Transactions- Single SINGLE TRANSACTION (MASTER SIGNALS) HCLK HBUSREQ HGRANT HADDR HTRANS CONTROL* A NONSEQ Control for A HRDATA A HWDATA A HREADY HRESP OKAY * CONTROL: HBURST, HWRITE, HSIZE

21 Single Transaction Clock 1: Master has a transfer to accomplish so the HBUSREQ is asserted. Also note that the address and control info has to be driven as well. Clock 2: Bus controller sees the request and is able to grant the bus. Clock 3: Master sees the grant and knows that the next cycle will clock address to slave. The HBUSREQ is deasserted because grant was seen. Also note that the bus controller uses this sampling point to determine the transaction type and control. Clock 4: This is the edge on which the slave samples the address and prepares for the data phase. The bus controller deasserts the HGRANT because it is given to another master. On the bus controller side, the 2 nd masters address phase would go out to the slaves between clock 6 and 7. Clock 5: The slave is not ready to give read data or accept write data so it deasserts the HREADY signal (wait state). It is not a problematic situation so the HRESP is OKAY. Clock 6: HREADY is asserted so the data is sampled.

22 Back-to-Back Transaction SINGLE TRANSACTIONS BACK-TO-BACK (MASTER SIGNALS) HCLK HBUSREQ HGRANT HADDR HTRANS CONTROL* A NONSEQ CONTROL FOR A B NONSEQ CONTROL FOR B HRDATA HWDATA HREADY HRESP * CONTROL: HBURST, HWRITE, HSIZE A A OKAY B B OKAY

23 Burst Transaction FIXED LENGTH BURST TRANSACTION (MASTER SIGNALS) HCLK HBUSREQ HGRANT HADDR A A+2 A+4 A+6 HTRANS NONSEQ SEQ SEQ SEQ CONTROL* CONTROL FOR BURST HRDATA A A+2 A+4 A+6 HWDATA A A+2 A+4 A+6 HREADY HRESP * CONTROL: HBURST, HWRITE, HSIZE OKAY OKAY OKAY OKAY

24 Undefined Length Burst UNDEFINED LENGTH BURST TRANSACTION (MASTER SIGNALS) HCLK HBUSREQ HGRANT HADDR A A+... A+n-1 A+n HTRANS NONSEQ SEQ SEQ SEQ CONTROL* CONTROL FOR BURST HRDATA A A+... A+n-1 A+n HWDATA A A+... A+n-1 A+n HREADY HRESP * CONTROL: HBURST, HWRITE, HSIZE OKAY OKAY OKAY OKAY

25 Single Transaction - Slave SINGLE TRANSACTION (SLAVE SIGNALS) HCLK HSEL HREADY HADDR HTRANS CONTROL* A NONSEQ CONTROL FOR A HRDATA A HWDATA A HREADYOUT HRESP OKAY * CONTROL: HBURST, HWRITE, HSIZE

26 AMBA Test Interface Standardized test interface Allows testing of modules in isolation Test using only bus transfers Requires no interaction with other system elements IO pins are not directly connected to bus

27 Test Interface Controller (TIC) 3 Control signals Test request A/B Test Acknowledg ement 16 bit test bus

28 Test Control Signals During test mode TREQA TREQB TACK Description Test mode entered Enter Test mode request Current access incomplete Address vector or turnaround vector Write vector Read vector Exit test mode

29 TIC Operation TREQA used to initialize the test TACK should remain High throughout the test Read vectors are followed by two turnaround vectors to ensure the completion of the transfer

30 Writing Test Vectors

31 Reading Test Results

32 Infiniband Overview New switched fabric proposal: trade association (PC) Goal: provide extensive IO bandwidth for servers Scalability Performance Reliability, Availability, Serviceability

33 Infiniband - Concepts A System Area Network (SAN) Unified Fabric for use between elements of computer systems Independent of the Host Operating System (OS)

34 The Switched Fabric Links Switches Routes packets based on destination Local ID and service level within a subnet Routers Routes packets based on Global ID to different subnets

35 Infiniband Architecture Model

36 Infiniband Host Architecture Connects memory controller to fabric through one or more links Provides work queues for posting work requests Manages transport functions Supports memory translation and protection

37 Communication Queuing: - Foundation of IBA operations - Ability of a consumer to queue up a set of instructions that the hardware executes.

Communications Stack Overview 1. Host sends a request to the remote consumer 2. Request translated into WQE by the CA and it is put into send stack of QP 3.

38 Communications Stack Overview 1. Host sends a request to the remote consumer 2. Request translated into WQE by the CA and it is put into send stack of QP 3. Request packet passes through transport, network, link & physical layers 4. Request reaches the receive stack of the remote consumer where packets are reassembled & checked for validation 5. Depending on QoS, the remote can either send or not send an ACK signal back to the host

39 IBA Layered Architecture

40 Conclusions System buses: means to realize open and extendible systems Bus basics Modern standards: PCI, AMBA, Infiniband Design and test issues

AMBA 3 AHB Lite Bus Architecture

AMBA 3 AHB Lite Bus Architecture 1 Module Syllabus What is a Bus Bus Types ARM AMBA System Buses AMBA3 AHB-Lite Bus Bus Operation in General AHB Bus Components AHB Bus Signals AHB Bus Basic Timing AHB