ECE 354 Introduction to Lab 1. February 5 th, 2003

Transcription

1 ECE 354 Introduction to Lab 1 February 5 th, 2003

2 Lab 0 Most groups completed Lab 0 IDE Simulator Questions? ICD Questions? What s the difference? ECE Spring

3 Addition to Honesty Policy It will be considered an honor code violation if you look at / use / copy files from other teams. Lab computers are shared stick to your own files. ECE Spring

4 Miscellaneous Grad TA: Ramaswamy Ramaswamy Undergrad TAs: Dave Thomas Dustin Marceau Darren Maczka Lab times: Monday: lab open 2:30-7:00 TAs: Dave 2:30-4:00, Dustin 4:00-7:00, Darren 5:30-7:00 Tuesday: lab open 4:30-7:00 (typo on syllabus) TAs: Darren 4:30-6:30, Dustin 5:30-7:00 Wednesday: lab open 2:30-7:00 TAs: Dave 2:30-5:30, Dustin 5:30-7:00 Thursday: lab open 4:00-7:00 (type on syllabus) TAs: Darren 4:00-6:30, Dave 5:30-7:00 Text on reserve Have to find a copy ECE Spring

5 Overview 16F877 Architecture Overview Memory Organization Special purpose registers Instruction Set Lab 1 USART Reset ECE Spring

6 PIC 16F877 Microcontroller with Harvard architecture 14 bit instructions 8 bit data values Byte addressed Storage capacity: Program storage: 8k x 14 bit Flash EPROM Data storage: 256 x 8 bit EEPROM 368 x 8 bit SRAM Universal Asynch./Synch. Receiver/Transmitter (UART) 8 channel, 1-bit A/D converter Up to 20 MHz clock, 200ns instruction cycle Much more (see data sheet p.1) ECE Spring

7 16F877 Block Diagram Main processor components: ALU Program counter Program memory Register file Status register Clock I/O ports Timers A/D converter USART ECE Spring

8 16F877 Block Diagram 8 bit data (ALU/registers) 13 bit PC 14 bit instructions 9 bit register address ECE Spring

9 Program Memory Location 0 is first instruction executed after reset Interrupt vector executed when interrupt occurs Why is it called vector? Program Stack: 8 levels deep ECE Spring

10 Data Memory Data memory split into banks Why? 4 banks of 128 registers Bit 5 and 6 of STATUS register are bank select bits Important registers are in all banks STATUS, FSR ECE Spring

11 Special Purpose Registers See data sheet Table 2-1 (pp ) Important special purpose registers: Status Program counter INDF and FSR for indirect addressing PORTA PORTD USART Tx and Rx Many more Some registers only available in particular banks E.g., USART ECE Spring

12 Status Register Bit 0: Carry Bit 1: Digit carry Bit 2: Zero result Bits 3&4: Use at power-up and sleep Bit 5&6: bank select Bit 7: bank select for indirect addressing ECE Spring

13 16F877 Instruction Format ECE Spring

14 16F877 Instruction Set 35 instructions See datasheet pp See Peatman pp. 25,27 28 ECE Spring

15 16F877 Assembler Nobody wants to code binary values of op-codes and operands adds 135 to working register Assembler translates readable code into binary ADDLW 135 means add literal 135 to working register Assembler converts this to Other convenient features Labels for branches and jumps (e.g., bug and start ) Register addresses can be named (e.g., c1 equ 0x0c ) Tutorial on Monday 2:30 Elab 303 ECE Spring

16 Reset Two main instances of reset Power applied to 16F877 MCLR (master clear) asserted active low PC reset to 0000h Various vectors occupy 0000h 0004h Program can start at 0005h More at tutorial on Monday ECE Spring

17 Lab 1 Connect PIC to terminal PIC in stand-alone mode using USART interface Mostly software development Required functionality: Four bits of port A connected to switches, value shown on LED on port B PIC sends Start (Y or N)? to terminal User presses key, value is sent to PIC and echoed If user presses Y, PIC sends ASCII character corresponding to hex value of bits on port A (e.g., 1100 should display C on terminal) Send character every time switch values change ECE Spring

18 UART/USART Universal Synchronous/Asynchronous Receiver/Transmitter Serial data communication between PIC and Terminal Two cables (receive and transmit) Each 1-byte character is transmitted separately Start, 8 data bits, 1 parity, Stop We use asynchronous mode Sender uses local clock Baud rate specifies speed of transmission ECE Spring

19 Synchronization ECE Spring

20 UART on 16F877 Several registers involved Control/status registers: TXSTA (transmit status and control register) RCSTA (receive status and control register) Configure: enable bit, 8/9 bit, buffer full, etc. Baud rate generator: SPBGR Data sheet table 10-3 shows value for different clock rates and baud rates Data registers: TXREG and RCREG Interrupt registers: PIR1 (flag bits for peripheral interrupts) Set when TXREG clears and RCREG is filled PIE1 (enable bits for interrupts) ECE Spring

21 UART Tx on PIC (1) ECE Spring

22 UART Tx on PIC (2) ECE Spring

23 UART Tx Signals ECE Spring

24 UART Rx on PIC (1) ECE Spring

25 UART Rx on PIC (2) ECE Spring

26 UART Rx Signals ECE Spring

27 Hardware Setup Need MAX232 driver PIC: 0/+5V RS-232 interface: ±10V See Peatman Ch. 11 ECE Spring

28 Lab 1 BEFORE YOU START: READ! Lab Assignment Data sheet pp (port I/O) Data sheet pp (UART) Peatman, chapter 11 (UART) MAX232 data sheet Think about how you want to split work Think about steps to take to get it working Start working early! Lab schedule starts Monday, Feb 10 ECE Spring

29 Next Start with Lab 1 Deadline: demo by 2/19, report by 2/26 Assembly tutorial Monday 2:30, Elab 303 Lab will be open ECE Spring