ISA96/AT96 SER4-FIFO. Technical Description

Transcription

1 Computertechnik GmbH ISA96/AT96 SER4-FIFO Technical Description Order numbers: SER4-FIFO SER2-FIFO Your contact: 1994 by Janich & Klass Computertechnik GmbH, Wuppertal Zum Alten Zollhaus Wuppertal Germany Tel. +49 (0) Fax +49 (0) BBS +49 (0)

2 Technical Description Rev. 1.0 ISA96/AT96 SER4-FIFO Table of Contents 1. Short Description Address Position Adjusting the Address Position Interrupts Adjusting the Interrupt Channels ISA96/AT96 Switch-Over Standard Adjustments for Addresses and Interrupts Possible Problems during Address- and Interrupt Selection FIFO-Operation Arrangement of the Interfaces Assignment of the Opto-Decoupled RS-232C Interfaces ISA96/AT96-BUS-Interface ISA96/AT96-Bus Signals Power Consumption Mechanical Data Operating Conditions Assembly Print Parts List Schematics...14 ( ) Page 2

3 1. Short Description The ISA96/AT96 SER4-FIFO is an adapter componentry with 4 serial interfaces 1. Its operation is possible at an ISA96- or an AT96-Bus. Features: Four serial PC-compatible interfaces On each interface, a 16Byte wide FIFO can be activated (compatible to NS16550). The FIFO-selection is supported by many standard software packages. Two serial interfaces of type RS232C, galvanically decoupled Two serial interfaces can be realized via SUB-Inserts as follows: SUB-Insert RS232C, corresponding V24/V.28 (9pole D-bushing) SUB-Insert RS232C, galvanically decoupled (9pole D-bushing) SUB-Insert RS422, galvanically decoupled (9pole D-bushing) SUB-Insert RS485, galvanically decoupled (9pole D-bushing) SUB-Insert 20mA, galvanically decoupled (9pole D-bushing) Further modules on request Baud rates from 50 to Baud Full 16-Bit I/O-addressing Address range adjustable to standard addresses (COM1, COM2...) and some other fixed values. Up to 4 SER4-FIFO componentries can be driven simultaneously in a computer system (16 serial interfaces) Interrupt operation possible via all free IRQ lines of the ISA96/AT96-Bus. Common interrupt possible for all interfaces of one card. 1 Alternatively, also a version with only 2 serial interfaces is available, where the SUB-Inserts are void. Otherwise, the cards are identical. ( ) Page 3

4 2. Address Position The basic address of each serial interface can be selected from 16 addresses. The following addresses are available: COM1 3F8H COM9 BF8H COM2 2F8H COM10 AF8H COM3 3E8H COM11 BE8H COM4 2E8H COM12 AE8H COM5 7F8H COM13 FF8H COM6 6F8H COM14 EF8H COM7 7E8H COM15 FE8H COM8 6E8H COM16 EE8H Kindly observe that only interfaces COM1 - COM4 2 are normed and will be recognized by your BIOS resp. operating system. For all other interfaces you will require specific drivers or software, where you can freely enter the address of the used interface. Each serial interface assigns 8 I/O-addresses from the basic address on. So, COM1 e.g. assigns the address range from 3F8H to 3FFH. The meaning of the individual registers within this address range can be taken from the data sheets of the serial chips NS16552 resp. NS Adjusting the Address Position The address position can be adjusted for each interface with the jumper fields J7 (SER1) - J10 (SER4). There, 2 jumpers must be set for each interface as per the following scheme: Y/ZXX 2/3XX 6/7XX A/BXX E/FXX YE8 YF8 ZE8 ZF8 Y/ZXX 2/3XX 6/7XX A/BXX E/FXX YE8 YF8 ZE8 ZF8 3F8H 2F8H 3E8H 2E8H 7F8H 6F8H 7E8H 6E8H COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 BF8H AF8H BE8H AE8H FF8H EF8H FE8H EE8H COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 If an interface shall be fully deactivated, both jumpers must be removed 2 COM3 and COM4 are not recognized by every BIOS! ( ) Page 4

5 3. Interrupts All serial interfaces can be driven by interrupts. It is also possibile to arrange an own interrupt to each serial interface, as also to drive all interrupts of a card from one common interrupt. This could be of special interest, when several SER4-FIFO cards are used within a system. In the second case, you can however not fall rely on standard software. In this case, the interrupt routine must run all interfaces in question, until no further interrupt is left. This is usually not supported by standard software packages Adjusting the Interrupt Channels Interrupt arrangement is made by jumpers J1 to J5. If each interface shall be driven with its own interrupt, an interrupt must be arranged to each interface, using jumpers J1-J4 (SER1 - SER4). If an interface shall not be operated in interrupt, the corresponding jumper must be removed. If all interfaces shall get one common interrupt, jumpers J1-J4 must be removed, and the common interrupt is to be adjusted with jumper J5 (ALL). SERX/ALL IRQ Set a jumper at the corresponding position in order to select interrupts (3,4,5,7,10,11,12,15). In the example, interrupt 10 was selected ISA96/AT96 Switch-Over The SER4-FIFO can be used as well in an ISA96 as also in an AT96 industrial PC. As some interrupts are lying at different connections in these two bus systems, the desired bus system must be selected in jumper field J6: ISA96 ISA96 The left figure shows the assignment of J6, as required for the ISA96-Bus. The right figure shows the corresponding assignment for the AT96-Bus. AT96 AT96 ISA96-BUS AT96-BUS ( ) Page 5

6 4. Standard Adjustments for Addresses and Interrupts On delivery, the following values are adjusted: Bus system: ISA96 Interface Address e Interrupt SER1 3E8H (COM3) 10 SER2 2E8H (COM4) 11 SER3 7E8H (COM7) 12 SER4 6E8H (COM8) 5 This corresponds to the following jumper arrangement: SER1 SER2 SER3 SER4 ALL IRQ J1 J2 J3 J4 J5 J6 ISA96 ADR Y/ZXX AT96 2/3XX 6/7XX A/BXX E/FXX YE8 YF8 ZE8 ZF8 SER1 SER2 SER3 SER4 J7 J8 J9 J10 ( ) Page 6

7 5. Possible Problems during Address- and Interrupt Selection You should observe the following items when selecting the addresses and interrupts in order to prevent eventual problems: Generally, please observe that there may be no address- resp. interrupt intersections with other cards. Please consider that many cards will evaluate only the lower 10Bits of the I/O-address. If your system already has serial interfaces, which you intend to further use (e.g. COM1 and COM2 on the CPU-card), you may adjust no addresses differing only in the upper address Bits (Bit 10 and 11). So, if you want to further use the interfaces COM1 (3F8H) and COM2 (2F8H) on the CPU-card, only the following addresses for the interfaces of the SER4-FIFO are allowed: 3E8H (COM3), 2E8H (COM4), 7E8H (COM7), 6E8H (COM8), BE8H (COM11), AE8H (COM12), FE8H (COM15), EE8H (COM16) If you want to drive more than 2 SER4-FIFO cards in your system, you must deactivate all other serial interfaces, which decode only 10 address Bits! Should interrupt 15 not work properly when using a Janich & Klass ISA96 CPU-card with ECB-Bus interface, please check whether this interrupt eventually is arranged to the ECB-Bus. Should you require no ECB-interrupts, you can remove the corresponding jumper on the CPU-card. Though the following problem will not arise with the SER4-FIFO, as it completely decodes the address bus, it may however arise at other serial interfaces and shall therefore be mentioned here: Some VGA-cards (e.g. an older version of the Video 7 VRAM VGA) assign the address 46E8H, which - in the lower 10 Bits - corresponds to the COM 4 address (2E8H). Analogously, this interface will then not work. Should the problem arise with a Janich & Klass Video 7 VRAM VGA, you can ask for a modification instruction, which will solve this problem. ( ) Page 7

8 6. FIFO-Operation Each interface on the SER4-FIFO has a 16 Byte wide FIFO-memory for transfer and receipt data. By this, if you have the correct software, the system is considerably releaved at receipt and transfer of data in interrupt. At interfaces without FIFO, an interrupt must be generated for each character. Here, the largest time amount is required for the overhead of the interrupt routine. Receiving or transfering the character itself takes only a very little portion of the time. By the FIFO, several characters can be run within an interrupt, which considerably releaves the system. Furthermore the danger is drastically reduced to lose a character, because the interrupt routine could not be called early enough in time. Thus, also high Baud rates (e.g Baud) can be driven in interrupt without problems. After a reset, however, the FIFOs are deactivated, so that the interface behaves fully PCcompatible. In order to use the FIFO, it must initially be activated. Furthermore, special routines are required which correctly handle the FIFO. A number of standard software packages support this. If you wish to write your own programs which use the FIFO, the required information required can be taken from the data sheets for the chips NS16550 resp. NS Here, we want to just shortly mention how you can switch the FIFO on resp. off and how you can find out whether the FIFO is active. For this, the register on address BASISADRESSE+2 (at COM1 this e.g. would be address 3FAH) must be read resp. written. If you read this register 3 and the Bits are 1, the FIFOs are active. If both Bits are 0, the FIFOs are deactivated. For switching on the FIFOs, please write the value 01H into this register, and for switch off the value 00H. Further details are found in the already mentioned data sheets. As the activation of the FIFOs is effected by a write access, which will have no effect at a standard-pc-interface, it may, though seldom, happen that a software unintentionally switches on the FIFO, which may lead to difficulties. If you have this assumption, you can easily find out whether the FIFO has been activated, using the method described above. 3 For this, you have to use the DOS-program DEBUG. With command <I adr>, you can read a register, and with <O adr,wert> you can write a register. ( ) Page 8

9 7. Arrangement of the Interfaces The 4 interfaces of the SER4-FIFO are arranged on the front panel as follows: Tx Rx Tx Rx SER1 SER3 Tx Rx Tx Rx SER2 SER4 SER4-FIFO 8. Assignment of the Opto-Decoupled RS-232C Interfaces The interfaces SER1 and SER2 are designed as opto-decoupled RS-232C interfaces. All connections are galvanically separated from the computer via opto-coupler and a DC/DCconverter. The voltage sustaining capability is at 500V. Both interfaces are decoupled also reciprocally. The plugs have the following assignment: DSR - 6 RTS - 7 CTS - 8 RI DCD 2 - RxD 3 - TxD 4 - DTR 5 - GND The assignment of the plugs on the SUB-Inserts can be taken from the corresponding Technical Descriptions. ( ) Page 9

10 9. ISA96/AT96-BUS-Interface 9.1. ISA96/AT96-Bus Signals a b c 1 GND 1 2 RESET SD V SD6 3 4 SD5 4 5 SD4 5 6 IRQ10 5 SD V 4 SD2 7 8 IRQ11 5 SD V 4 SD IRQ AEN IRQ /IOW /IOR SA SA SA SA SA IRQ7 SA SA IRQ5 SA IRQ4 SA IRQ3 SA SA SA IRQ15 6 SA V SA IRQ12 6 SA IRQ11 6 SA IRQ The voltages +12V and -12V are reqiored only for the SUB-Inserts. 5 Assignment of the interrupts 10,11,12 and 15 on the AT96-Bus (also refer J6) 6 Assignment of the interrupts 10,11,12 and 15 on the ISA96-Bus (also refer J6) ( ) Page 10

11 Interrupt Lines Selectable are: IRQ3, IRQ4, IRQ5, IRQ7, IRQ10, IRQ11, IRQ12, IRQ15 DMARQ Lines none Bus Load Signal Meaning LS Fan-out LS Fan-in SD0... SD7 System Data Bus 60 1 SA0... SA15 System Address Bus - 1 AEN Address enable - 1 /IOR, /IOW I/O read / write - 1 RESET System Reset - 1 IRQx interrupt-request Power Consumption +5V: 300mA (max.) +12V: - (required only for SUB-Inserts) -12V: - (required only for SUB-Inserts) Please take the power consumption of the SUB-Inserts from the corresponding Technical Description. ( ) Page 11

12 10. Mechanical Data Dimensions of the printed board: 160mm x 100mm (Euro-size card) Installation width: SER4-FIFO mm (8HP) SER2-FIFO mm (4HP) Design of the printed board: Weight: Installation position: 4-layer multi-layer, material FR4 290g (without SUB-Inserts) preferably upright 11. Operating Conditions Supply voltages: Operating temperature: 5-65 C Cooling: Relative humidity: Storage temperature: C Storage period: 4,85V - 5,25V, max. 100mVss Ripple +12V, -12V refer description SUB-Inserts at upright installation convection cooling with at least 1m/min air speed 10-90%, non-condensing unlimited ( ) Page 12