EECS 598: Integrating Emerging Technologies with Computer Architecture. Lecture 2: Figures of Merit and Evaluation Methodologies

Transcription

1 1 EECS 598: Integrating Emerging Technologies with Computer Architecture Lecture 2: Figures of Merit and Evaluation Methodologies Instructor: Ron Dreslinski Winter

2 Measuring performance 2 2

3 Performance Two definitions Latency (execution time): time to finish a fixed task Throughput (bandwidth): number of tasks in fixed time Very different: throughput can exploit parallelism, latency can t Baking bread analogy Often contradictory Choose definition to matches measurement goals Example: move people from A to B, 10 miles Car: capacity = 5, speed = 60 miles/hour Bus: capacity = 60, speed = 20 miles/hour Latency: car = 10 min, bus = 30 min Throughput: car = 15 PPH (count return trip), bus = 60 PPH 3 3

4 Performance Improvement Processor A is X times faster than processor B if Latency(P,A) = Latency(P,B) / X Throughput(P,A) = Throughput(P,B) * X Processor A is X% faster than processor B if Latency(P,A) = Latency(P,B) / (1+X/100) Throughput(P,A) = Throughput(P,B) * (1+X/100) Car/bus example Latency? Car is 3 times (and 200%) faster than bus Throughput? Bus is 4 times (and 300%) faster than car 4 4

5 Averaging Performance Numbers I You can add latencies, but not throughput Latency(P1+P2, A) = Latency(P1,A) + Latency(P2,A) Throughput(P1+P2,A)!= Throughput(P1,A) + Throughput(P2,A) E.g., 1 30 miles/hour miles/hour Average is not 60 miles/hour hours at 30 miles/hour hours at 90 miles/hour Average is only 47 miles/hour! (2 miles / ( hours)) 5 5

6 Averaging Performance Numbers II Latency(P1+P2, A) = Latency(P1,A) + Latency(P2,A) Throughput(P1+P2,A) = 1 / [(1/ Throughput(P1,A)) + (1/ Throughput(P2,A))] Three averaging techniques: Arithmetic : (1/N) * P=1..N Latency(P) For times: units proportional to time (e.g., latency) Harmonic : N / P=1..N 1/Throughput(P) For rates: units inversely proportional to time (e.g., throughput) Geometric : N P=1..N Speedup(P) For ratios: unitless quantities (e.g., speedups) 6 6

7 The Iron Law of Processor Perf. Time Processor Performance = Program Instructions Cycles Time = X X Program Instruction Cycle (code size) (CPI) (cycle time) Architecture --> Implementation --> Realization Compiler Designer Processor Designer Chip Designer 7 7

8 Danger: Partial Performance Metrics Micro-architects often ignore dynamic instruction count Typically work in one ISA/one compiler treat it as fixed Iron law reduces to seconds / instruction = (cycles / instruction) * (seconds / cycle) MIPS (millions of instructions per second) Instructions / second * 10-6 Cycles / second: clock frequency (in MHz) Example: CPI = 2, clock = 500 MHz, what is MIPS? 0.5 * 500 MHz * 10-6 = 250 MIPS Problems: compiler removes instructions, program faster However, MIPS goes down (misleading) 8 8

9 Danger: Partial Performance Metrics II Micro-architects often ignore instructions/program but general public (mostly) also ignores CPI Equates clock frequency or core count with performance!! Which processor would you buy? Processor A: CPI = 2, clock = 500 MHz Processor B: CPI = 1, clock = 300 MHz Probably A, but B is faster (assuming same ISA/compiler) Classic example 800 MHz Pentium III faster than 1 GHz Pentium 4 Same ISA and compiler 9 9

10 Performance Key Points Amdahl s law S overall = 1 / ( (1-f) + f/s ) Iron law Time Program = Instructions Program Cycles Instruction Time Cycle Averaging Techniques 1 Arithmetic Time n i = n 1Time i Harmonic Rates n i = 1 n 1 n Ratei Geometric Ratios n Ratio i i =

11 Power and Energy 11 11

12 Why is power a problem in a µp? Power used by the µp, vs. system power Dissipating Heat Melting (very bad) Packaging (to cool à $) Heat leads to poorer performance. Providing Power Battery Cost of electricity 12 12

13 Where does the juice go in laptops? Others have measured ~55% processor increase under max load in laptops [Hsu+Kremer, 2002] 13 13

14 What about servers? SunFire T2000 DRAM >20%; growing 20% CPU <25%; shrinking 23% 20% 4% 10% 9% 14% AC to DC only 60-90% efficient Processor Memory I/O Disk Services Fans AC/DC Conversion Need whole-system approaches to save energy 14 14

15 Why worry about power dissipation? Battery life Thermal issues: affect cooling, packaging, reliability, timing Environment 15 15

16 Total Power Dissipation Trends Power Density (W/cm 2 ) Nuclear Reactor Pentium 4 (Prescott) Pentium 4 Hot Plate Pentium 3 Pentium Pentium 2 Pentium Pro

17 Spot Heat Issues in Microprocessors 17 17

18 Packaging cost Complex and expensive (note heatpipe) Source: H. Xie et al. Packaging the Itanium Microprocessor Electronic Components and Technology Conference

19 Power-Aware Computing Applications Temperature/di-dt-Constrained Energy-Constrained Computing 19 19

20 Power vs. Energy 20 20

21 Small Group Discussion Work in small groups (3-5 people) to discuss the following: Consider the applications below and describe why they might be energy constrained and/or power constrained Handheld Ultrasound plugged into the wall Medical Implant Device (i.e. pacemaker) Mobile Phone playing a movie Server farm calculating impact of global warming 21 21