EE141- Spring 2007 Introduction to Digital Integrated Circuits

Transcription

1 - Spring 2007 Introduction to Digital Integrated Circuits Tu-Th 5pm-6:30pm 150 GSPP 1 What is this class about? Introduction to digital integrated circuits.» CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn?» Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 2

2 Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates; timing Arithmetic building blocks Interconnect: R, L and C Memories and array structures Design methods 3 Interludium: Administrativia Instructor The TAs Kenny Duong Discussion + lab keduong@berkeley.edu Office Hours: TBD Andrei Vladimirescu andrei@eecs.berkeley.edu Office hours: 511 Cory Tu 2:45-4:45pm TBD Discussion + lab???@eecs.berkeley.edu Office Hours: TBD Reader TBD 4

3 The Web-Site The sole source of information Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies Save a tree! 5 Class Admission No enrollment issues. Everyone will be accommodated (hopefully)! Make sure your name is on the class roll! 6

4 Discussions and Labs Discussion sessions» Mo 2-3pm, 293 Cory» We 3-4pm, 521 Cory» Pick any of the two (they are covering the same material) Labs (353 Cory)» Mo 1-4pm» We 11am-2pm» F 2-5pm» Pick the one that fits you the best (pending availability) and STICK TO IT! 7 Your Week At a Glance M Lab (?) 353 Cory DISC* () 293 Cory T TA mtng OH (Andrei) 511 Cory Lec (Andrei) GSPP W Lab () 353 Cory DISC* () 521 Cory Problem Sets Due R Lec (Andrei) GSPP F Lab () 353 Cory * Discussion sections will cover identical material 8

5 Class Organization 10 Assignments A couple of design projects (1 term project) Labs: 6 software, 1 hardware 2 midterms, 1 final» Midterm 1: Tu February 20, 6:30-8:00pm, or Th February 22, 5-6:30pm» Midterm 2: Tu April 3, 6:30-8:00pm» Final: Currently Th May 17, 5-8pm, to be changed to Mo May 14, time TBA 9 Grading Policy Homeworks: 10% Labs: 10% Projects: 20% Midterms: 30% Final: 30% 10

6 Class Material Textbook: Digital Integrated Circuits A Design Perspective, 2 nd Edition, by J. Rabaey, A. Chandrakasan, and B. Nikolic Lab Reader: Available on the web page! Selected material will be made available from Copy Central Check web page for the availability of tools 11 Software Cadence software only!» Phased out the Micromagic software.» Online documentation and tutorials HSPICE and IRSIM(?) for simulation 12

7 Getting Started Assignment 1: Getting SPICE to work» see web-page» also The SPICE Book, by A. Vladimirescu NO discussion sessions or labs this week. First discussion sessions in Week 2 First Software Lab in Week 3 13 Introduction Why is designing digital ICs different today than it was before? Will it change in future? 14

8 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17, ENIAC - The first electronic computer (1946) 16

9 The Transistor Revolution First transistor Bell Labs, The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola

10 Intel 4004 Micro-Processor 19 Intel Pentium (II) microprocessor Intel Mil. Transistors 20

11 Intel Pentium 4 21 Intel Core 2 Microprocessor 22

12 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 23 Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19,

13 Evolution in Complexity 25 Moore s law in Microprocessors Transistors (MT) X growth in 1.96 years! P6 Pentium proc 486 S. Borkar Year Transistors on Lead Microprocessors double every 2 years 26

14 Moore s Law - Logic Density 1000 Logic Transistors/mm 2 Logic Density i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend 1.5µ 1.0µ Source: Intel 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Shrinks and compactions meet density goals New micro-architectures drop density 27 Die Size Growth 100 Die size (mm) P6 486 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law S. Borkar 28

15 Transistor Count 29 Frequency Prediction ~2004 Frequency (Mhz) Doubles every 2 years P6 Pentium proc S. Borkar Year Lead Microprocessors frequency doubles every 2 years 30

16 Frequency (Today) 31 Power will be a problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive S. Borkar 32

17 Power Dissipation 33 Processor Power 100 Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? 1.5µ 1µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Lead processor power increases every generation Compactions provide higher performance at lower power Source: Intel 34

18 Power density will increase Power Density (W/cm2) Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year S. Borkar Power density too high to keep junctions at low temp 35 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 36

19 Productivity Trends 10,000,000 10,000 1,000,000 1,000 Complexity Logic Transistor per Chip(M) 100, , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity 37 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! 38

20 Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ 39 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x How to design chips with more and more functions? Design engineering population does not double every two years Need to understand different levels of abstraction 40

21 2010 Outlook 1B transistors on a chip GHz operation 1T operations/s Most formidable challenges» Power» Design complexity P. Gelsinger, ISSCC Next Class Introduces basic metrics for design of integrated circuits how to measure delay, power, etc. Brief intro to IC manufacturing and design 42