EECS 470 Lecture 1. Computer Architecture. Winter 2019 Prof. Ron Dreslinski h6p://

Transcription

1 Computer Architecture Winter 2019 Prof. Ron Dreslinski h6p:// Slides developed in part by Profs. Austin, Brehob, Falsafi, Hill, Hoe, Lipasti, Martin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar, and Wenisch of Carnegie Mellon University, Purdue University, University of Michigan, University of Pennsylvania, and University of Wisconsin. Slide 1

2 Announcements HW # 1 due Thursday 1/17 at 6:00pm q Mostly review from 270/370 Programming assignment #1 due Friday 1/18 (by 11:59pm) More details in lab Slide 2

3 Readings For Monday: Electronic copy of H&P 5 th ed. linked from course homepage H & P Chapter 1 H & P Appendix B Slide 3

4 What Is Computer Architecture? The term architecture is used here to describe the awributes of a system as seen by the programmer, i.e., the conceptual structure and funcyonal behavior as disynct from the organizayon of the dataflow and controls, the logic design, and the physical implementayon. Gene Amdahl, IBM Journal of R&D, April 1964 Slide 4

5 Architecture, Organization, Implementation Computer architecture: SW/HW interface instrucyon set memory management and protecyon interrupts and traps floayng-point standard (IEEE) OrganizaYon: also called microarchitecture number/locayon of funcyonal units pipeline/cache configurayon datapath connecyons ImplementaYon: low-level circuits Slide 5

6 What Is 470 All About? High-level understanding of issues in modern architecture: Dynamic out-of-order processing Memory architecture I/O architecture MulYcore / mulyprocessor issues Lectures, HW & Reading Low-level understanding of criycal components: Microarchitecture of out-of-order machines Caches & memory sub-system Project & Reading Slide 6

7 Class Info Instructor: Professor Ronald Dreslinski GSIs: Jielun Tan James Connolly Class info: URL: hwp:// Piazza for discussing HW & projects Gradescope for HW submissions Canvas for reporyng grades Slide 7

8 Meeting Times Lecture TuTh 12:00pm 1:30pm (1670 BBB) Lab (a0endance mandatory!) Th 4:00pm 6:00pm (1620 BBB) F 10:30am 12:30pm (1620 BBB) Office Hours TBD Slide 8

9 Who Should Take 470? Seniors (ambitious Juniors) & Graduate Students 1. Computer architects to be 2. Computer system designers 3. Those interested in computer systems Required Background Basic digital logic (EECS 270) Basic architecture (EECS 370) Verilog experience helpful (covered in discussion) Slide 9

10 Grading Grade breakdown Midterm: 20% Final: 25% Homework: 8% (total of 5, drop lowest grade) Verilog assignments: 10% (total of 3) In-lab assignments: 2% Project: 35% Open-ended (group) processor design in Verilog Median will be ~80% (so is a disynguisher!) ParYcipaYon + discussion count toward the Project grade Slide 10

11 Grading (Cont.) No late homeworks, no kidding Group studies are encouraged Group discussions are encouraged All homeworks & verilog must be results of individual work There is no tolerance for academic dishonesty. Please refer to the University Policy on chea;ng and plagiarism. Discussion and group studies are encouraged, but all submi0ed material must be the student's individual work (or in case of the project, individual group work). Slide 11

12 Hours (and hours) of work AWend class & discussion ~4 hrs / week Read book & handouts ~2-3 hrs / week Do homework 5 ~4 hrs each / 15 weeks ~1-2 hrs/week 3 Programming assignments 6, 6, 20 hrs = 32 hrs / 15 weeks ~2 hrs/week Project ~100 hrs / 15 weeks = ~7 hrs / week Studying, etc. ~2 hrs/week Expect to spend ~20 hours / week on this class!! Slide 12

13 Fundamental concepts Slide 13

14 Amdahl s Law Speedup= Yme without enhancement / Yme with enhancement Suppose an enhancement speeds up a fracyon f of a task by a factor of S Yme new = Yme orig ( (1-f) + f/s ) S overall = 1 / ( (1-f) + f/s ) time orig orig (1 - f) (1 - f) 1 f f time new (1 - f) (1 f/s - f) f/s Slide 14

15 Parallelism: Work and Critical Path Parallelism - the amount of independent sub-tasks available Work=T 1 - Yme to complete a computayon on a sequenyal system CriYcal Path=T - Yme to complete the same computayon on an infinitelyparallel system x = a + b; y = b * 2 z =(x-y) * (x+y) Average Parallelism P avg = T 1 / T For a p wide system T p max{ T 1 /p, T } P avg >>p T p T 1 /p Slide 15

16 Locality Principle One s recent past is a good indicayon of near future. Temporal Locality: If you looked something up, it is very likely that you will look it up again soon SpaYal Locality: If you looked something up, it is very likely you will look up something nearby next Locality == PaWerns == Predictability Converse: An;-locality : If you haven t done something for a very long ;me, it is very likely you won t do it in the near future either Slide 16

17 Memoization Dual of temporal locality but for computayon If something is expensive to compute, you might want to remember the answer for a while, just in case you will need the same answer again Why does memoiza;on work?? Examples Branch predictor Trace cache Slide 17

18 Amortization & Speculation overhead cost : one-yme cost to set something up per-unit cost : cost for per unit of operayon total cost = overhead + per-unit cost x N high overhead OK if distributed over many units lower the average cost average cost = total cost / N = ( overhead / N ) + per-unit cost SpeculaYon make educated guesses to avoid expensive operayons if you can be right most of the Yme Make the common case fast Make the uncommon case correct Slide 18

19 Trends in computer architecture Slide 19

20 A Paradigm Shift In Computing Transistors (100,000's) Power (W) Performance (GOPS) Efficiency (GOPS/W) IEEE Computer April 2001 T. Mudge Limits on heat extracyon Limits on energy-efficiency of operayons Slide 20

21 A Paradigm Shift In Computing Transistors (100,000's) Power (W) Performance (GOPS) Efficiency (GOPS/W) IEEE Computer April 2001 T. Mudge Limits on heat extracyon Stagnates performance growth Limits on energy-efficiency of operayons Era of High Performance CompuYng c Era of Energy-Efficient CompuYng Slide 21

22 Four decades of Dennard Scaling Dennard et. al., 1974 P = C V 2 f Increase in device count Lower supply voltages Constant power/chip Robert H. Dennard, picture from Wikipedia Slide 22

23 Leakage Killed Dennard Scaling Leakage: ExponenYal in inverse of V th ExponenYal in temperature Linear in device count To switch well must keep V dd /V th > 3 V dd can t go down Slide 23

24 The Memory Wall %/yr. Performance %/yr. Processor Memory 7%/yr Source: Hennessy & Patterson, Computer Architecture: A Quantitative Approach, 4 th ed. Today: 1 mem access 500 arithmeyc ops Slide 24

25 Multicore: Solution to Power-constrained design? Wenisch 2011 Power = CV 2 F F V Scale clock frequency to 80% Now add a second core EECS 570 Performance Same power budget, but 1.6x performance! But: Must parallelize applicayon Remember Amdahl s Law! Power Slide 25

26 Reliability Wall Transient faults E.g, high-energy parycle strikes Manufacturing faults E.g., broken connecyons Wearout faults E.g., ElectromigraYon interconnect via Source Gate N+ N Drain P transients Testing burn-in Future: device variability (not all transistors created equal) Slide 26

27 Measuring performance Slide 27

28 Performance Two definiyons Latency (execuron Rme): Yme to finish a fixed task Throughput (bandwidth): number of tasks in fixed Yme Very different: throughput can exploit parallelism, latency can t Baking bread analogy Ozen contradictory Choose definiyon to matches measurement goals Example: move people from A to B, 10 miles Car: capacity = 5, speed = 60 miles/hour Bus: capacity = 60, speed = 20 miles/hour Latency: car = 10 min, bus = 30 min Throughput: car = 15 PPH (count return trip), bus = 60 PPH Slide 28

29 Performance Improvement Processor A is X Ymes faster than processor B if Latency(P,A) = Latency(P,B) / X Throughput(P,A) = Throughput(P,B) * X Processor A is X% faster than processor B if Latency(P,A) = Latency(P,B) / (1+X/100) Throughput(P,A) = Throughput(P,B) * (1+X/100) Car/bus example Latency? Car is 3 Ymes (and 200%) faster than bus Throughput? Bus is 4 Ymes (and 300%) faster than car Slide 29

30 Averaging Performance Numbers I You can add latencies, but not throughput Latency(P1+P2, A) = Latency(P1,A) + Latency(P2,A) Throughput(P1+P2,A)!= Throughput(P1,A) + Throughput(P2,A) E.g., 1 30 miles/hour miles/hour Average is not 60 miles/hour hours at 30 miles/hour hours at 90 miles/hour Average is only 47 miles/hour! (2 miles / ( hours)) Slide 30

31 Averaging Performance Numbers II Latency(P1+P2, A) = Latency(P1,A) + Latency(P2,A) Throughput(P1+P2,A) = 1 / [(1/ Throughput(P1,A)) + (1/ Throughput(P2,A))] Three averaging techniques: ArithmeRc : (1/N) * P=1..N Latency(P) For Rmes: units proporyonal to Yme (e.g., latency) Harmonic : N / P=1..N 1/Throughput(P) For rates: units inversely proporyonal to Yme (e.g., throughput) Geometric : N P=1..N Speedup(P) For raros: unitless quanyyes (e.g., speedups) Slide 31

32 The Iron Law of Processor Performance Time Processor Performance = Program Instructions Cycles Time = X X Program Instruction Cycle (code size) (CPI) (cycle time) Architecture --> Implementation --> Realization Compiler Designer Processor Designer Chip Designer Slide 32

33 Danger: Partial Performance Metrics Micro-architects ozen ignore dynamic instrucyon count Typically work in one ISA/one compiler treat it as fixed Iron law reduces to seconds / instrucyon = (cycles / instrucyon) * (seconds / cycle) MIPS (millions of instrucyons per second) InstrucYons / second * 10-6 Cycles / second: clock frequency (in MHz) Example: CPI = 2, clock = 500 MHz, what is MIPS? 0.5 * 500 MHz * 10-6 = 250 MIPS Problems: compiler removes instrucyons, program faster However, MIPS goes down (misleading) Slide 33

34 Danger: Partial Performance Metrics II Micro-architects ozen ignore instrucyons/program but general public (mostly) also ignores CPI Equates clock frequency with performance!! Which processor would you buy? Processor A: CPI = 2, clock = 500 MHz Processor B: CPI = 1, clock = 300 MHz Probably A, but B is faster (assuming same ISA/compiler) Classic example 800 MHz PenYum III faster than 1 GHz PenYum 4 Same ISA and compiler Slide 34

35 Performance Key Points Amdahl s law S overall = 1 / ( (1-f) + f/s ) Iron law Time Program = Instructions Program Cycles Instruction Time Cycle Averaging Techniques Arithmetic Time Harmonic Rates Geometric Ratios 1 n i = n 1Time i n i = 1 n 1 n Ratei n Ratio i i=1 Slide 35