What is this class all about?

Transcription

1 EE141-Fall 2007 Digital Integrated Circuits Instructor: Elad Alon TuTh 3:30-5pm 155 Donner 1 1 What is this class all about? Introduction to digital integrated circuit design engineering Will describe models and key concepts needed to be a good digital IC designer Models allow us to reason about circuit behavior Allow analysis and optimization of the circuit s performance, power, cost, etc. Understanding circuit behavior is key to making sure it will actually work Teach you how to make sure your circuit works Do you want your transistor to be the one that screws up a 1 billion transistor chip? 2 2

2 Detailed Topics CMOS devices and manufacturing technology CMOS inverters and gates Propagation delay, noise margins, power Combinational and sequential circuits Timing and clocking Arithmetic building blocks Interconnect Memories Design methodologies 3 3 What will you learn? Understanding, designing, and optimizing digital circuits for various quality metrics: Performance (speed) Power dissipation Cost Reliability 4 4

3 Practical Information Instructor Prof. Elad Alon 565 Cory Hall, , Office hours: TuTh 11am-12pm TAs: Eric Chin, (OH: Wed. 4-5pm) Kenny Duong, (OH: Wed. 3-4pm) Adam Abed (OH: Tues. 2-3pm) Kevin Chao (OH: Tues. 2-3pm) Web page: Discussions and Labs Discussion sessions F 2-3pm, Kenny M 5-6pm, Eric F 9-10am, Adam Same material in all sessions! Labs (353 Cory) M 10am-1pm W 12-3pm F 3-6pm Tu 12-3pm (most likely will be cancelled) Please choose one lab session and stick with it! 6 6

4 Your EECS141 Week M Lab (Kevin) 353 Cory DISC* (Eric) 293 Cory T OH (Elad) 565 Cory Lab (TBD) 353 Cory OH (Adam, Kevin) TBD Cory Lec (Elad) 155 Donner W Lab (Kenny) 353 Cory OH (Kenny) TBD Cory OH (Eric) TBD Cory R OH (Elad) 565 Cory Lec (Elad) 155 Donner Problem Sets Due F DISC* (Adam) 293 Cory DISC* (Kenny) 293 Cory Lab (Eric) 353 Cory * Discussion sections will cover identical material 7 7 Class Organization 10 Assignments One design project (with a few phases) Labs: 5 software, 1 hardware 2 midterms, 1 final Midterm 1: Thurs., October 4, evening (TBD) Midterm 2: Thurs., November 1, evening (TBD) Final: Thurs., December 20, 12:30-3:30pm (TBD) 8 8

5 Some Important Announcements Please use the newsgroup for asking questions (ucb.class.ee141) Can work together on homework But you must turn in your own solution Please don t bring food/drinks to 353 Cory Lab reports due 1 week after the lab session Project is done in pairs No late assignments Solutions available shortly after due date/time Don t even think about cheating! 9 9 Grading Policy Homeworks: 10% Labs: 10% Projects: 20% Midterms: 30% Final: 30% 10 10

6 Class Material Textbook: Digital Integrated Circuits A Design Perspective, 2 nd ed, by J. Rabaey, A. Chandrakasan, B. Nikolic Class notes: Web page Lab Reader: Web page Check web page for the availability of tools The Web Site The sole source of information Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies Print only what you need: Save a tree! 12 12

7 Software Cadence Widely used in industry Online tutorials and documentation HSPICE for simulation Getting Started Assignment 1: Getting SPICE to work see web-page Due next Thursday, September 6, 5pm NO discussion sessions or labs this week. First discussion sessions in Week 2 First software lab in Week

8 Introduction Why is designing digital ICs different today than it was before? Will it change in future? The First Computer The Babbage Difference Engine 25,000 parts cost: 17,

9 ENIAC - The First Electronic Computer (1946) The Transistor Revolution First transistor Bell Labs,

10 The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola Intel 4004 Microprocessor Intel, ,300 transistors (12mm 2 ) 740 KHz operation (10µm PMOS technology) 20 20

11 Intel Pentium 4 Microprocessor Intel, ,000,000 transistors (112mm 2 ) 3.8 GHz operation (90nm CMOS technology) Intel Core 2 Microprocessor Intel, ,000,000 transistors (143mm 2 ) 3 GHz operation (65nm CMOS technology) 22 22

12 Moore s s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months Moore s s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19,

13 Evolution in Complexity Transistor Counts Transistor Counts in Intel's Microprocessors 1000 Itanium II Transistors [in millions] DX DX Pentium II Itanium Pentium Pro Pentium Pentium III Pentium MMX 486DX4 Pentium 4 Doubles every 2 years Core2

14 Frequency Frequency Trends in Intel's Microprocessors Frequency [MHz] DX 386DX Pentium II Pentium Pro Pentium 486DX4 Pentium III Pentium MMX Pentium 4 Itanium II Itanium Has been doubling every 2 years, but is now slowing down Core2 Power Dissipation Prediction (2000) Power (Watts) Pentium proc Courtesy, Intel KW 5KW 1.5KW 500W Year Did this really happen?

15 Power Dissipation Data Power Trends in Intel's Microprocessors Power [W] Has been > doubling every 2 years 486DX 386DX Pentium Pro Pentium Pentium III Itanium II Itanium Pentium II Pentium 4 Has to stay ~constant Core 2 Cause: Power Density Power Density (W/cm2) Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Power density too high for cost-effective cooling S. Borkar

16 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity 32 Courtesy, ITRS Roadmap 32

17 Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Complexity Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 34 34

18 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE D n Next Lecture Introduce basic metrics for design of integrated circuits how to measure delay, power, cost, etc