Student Workbook Mentor Graphics Corporation All rights reserved.

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1 Eldo Platform Essentials Student Workbook 2018 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

2 This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. U.S. GOVERNMENT LICENSE RIGHTS: The software and documentation were developed entirely at private expense and are commercial computer software and commercial computer software documentation within the meaning of the applicable acquisition regulations. Accordingly, pursuant to FAR 48 CFR and DFARS 48 CFR , use, duplication and disclosure by or for the U.S. Government or a U.S. Government subcontractor is subject solely to the terms and conditions set forth in the license agreement provided with the software, except for provisions which are contrary to applicable mandatory federal laws. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the owner of the Mark, as applicable. The use herein of a third- party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: The registered trademark Linux is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of the mark on a world-wide basis. End-User License Agreement: You can print a copy of the End-User License Agreement from: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon Telephone: Toll-Free Telephone: Website: SupportNet: supportnet.mentor.com/ Send Feedback on Documentation: supportnet.mentor.com/doc_feedback_form Part Number:

3 Module 1: Introduction to Eldo Objectives Design New Challenges Due to Nanometer Effects Simulation New Challenges Eldo Platform Industry Proven Circuit Verification Platform for Analog-Centric ICs Impractical Without Eldo Platform Quality & Reliability Verification Tools Environment Integrations Course Objectives Module 2: DC Convergence Objectives DC Analysis DC Partitioning Formulation of Network Equations Circuit Example Corresponding Final Matrix Kirchhoff Current Law Newton-Raphson Algorithm Local Minimum High Impedance Node Low Impedance Node Discontinuity in Device Objectives DC Convergence Aid Introduction DC Convergence Aid Algorithms I

4 DC Convergence Aid Mechanisms GMIN Stepping [Simplified] DC Ramping [Simplified] Transient Ramping [Damped] Pseudo Transient Objectives Improve DC Convergence IC Command NODESET Command Simulation output with.nodeset GUESS Command Initial Condition Precedence Saving Simulation State SAVE Command (Basic) SAVE Command (Advanced) Loading Simulation Information USE /.LOAD vs.restart SAVE /.USE /.RESTART Examples DC No-convergence Causes Options to Solve DC Convergence Problems Check for Circuit Connectivity Problems Solving DC Non - Convergence Problems Strange DC Results Introduction Multiple DC Operating Points How are Voltage Sources Used? II

5 Set up Your Own VMIN/VMAX OPTION VMIN and VMAX Effects Solving Wrong DC Results Lab Time Summary Module 3: Eldo Classic Objectives Three Different Algorithms for Transient Finding the Solution of a DAE System TRAP GEAR Backward Euler What Is Local Truncation Error (LTE)? Control of Local Truncation Error RELTOL, VNTOL, ABSTOL and CHGTOL Role Global Tuning of Accuracy EPS TUNING Accuracy and Time Step Control Changing Accuracy During Simulation Optimize Performance/ Accuracy Compromise Local Sub-circuit Tolerance Digital Cell Characterization New Algorithm for Digital Cell Characterization option DCC_tuning Syntax Accelerate Small Simulations III

6 Eldo Classic Summary Objectives Traditional Debug Information Which Diagnosis Mode For Your Needs? Speed/Convergence Bottleneck Analysis Learn About Nodes/Devices impacting Time-Step (Perf Mode) Diagmode Perf Output Diagmode Tstep Output Learn About the Characteristics of Devices Connected to Problematic Nodes (tstep mode) Error Code 2 Causes Error Code 6 Causes Error Code 6 Solutions Lab Time Summary Module 4: Simulation Speed up Objectives Simulation of Large Circuits Information About Memory and Circuit Size in.chi File Collapse the Intrinsic MOS Transistor Nodes Options to Limit the Size of.chi File Options to Limit the WDB Size Options to Limit the WDB Size In Transient Dynamic Plots Programmable Plots Objectives IV

7 Efficient Multi-Threading in ELDO Introduction to Multi-Threading Technology Licensing for Multi-Threading Eldo 勃 se_proc Multi-Threading Conditions Multi-Threading on a Loaded Machine Check Machine Configuration Importance of Cache Memory Eldo 膨 ntthread Objectives CPU Time versus Simulation Type MPRUN Basic Vocabulary MPRUN Mechanism MPRUN Parallelization of Multi-Run Simulations MPRUN HOST MPRUN MAX_NBJOBS=val Licensing Mechanism for.mprun MPRUN NBLICENSES=val Number of Jobs with.mprun Simulation Speedup and Other Interesting Features Remove Elaboration Bottleneck External Dispatchers Running a Single Run Simulation with LSF Running Multiple Run Simulation with LSF Summary V

8 Module 5: Eldo Premier Power and Current Analyses Objectives Premier Use Model Allows Quick Adoption Eldo Premier Licensing in MT Context: Eldo Classic x Accuracy Eldo Continuous Performance Improvement Speedup Multithreading Scalabity Improvement Speedup Even Better With Large Designs Performance Gain With Multi-threading & Multi-processing Netlist Support Monte Carlo in Premier Objectives Key Technology Concept: HR Eldo Classic Multi-Threading Eldo Premier Multi-Threading Eldo Premier: Linear Algebra Revisited Eldo Classic Interpreted Code Eldo Premier Compiled Optimized Code Eldo Premier Temporary Files Automatic Activation of Premier Objectives PREMIER_MODE and Other Accuracy Options Device Model Optimization Small R and C Simplification Reduction is Done by Default in Premier VI

9 RC Reduction in Premier Objectives Performance Improvements between 13.1 and 14.1 releases Circuits Using BCD Processes Large Dense SoC Premier_HiSpeed Option Eldo Premier Functional Mode Benefits Eldo Premier Functional Mode New in AMSV Objectives Introduction to Power Consumption Analysis Performing Power Analysis Power Analysis Window Running the Analysis Power Table Introduction to Current Analysis Current Analysis Syntax Use Model A New Interface in EZwave Current Debugging Example Lab Time Summary Module 6: Post Layout Objectives Introduction What Is a Net After Extraction? Coupling Further Complicates Reduction VII

10 Coupling Plus Intrinsic Objectives DSPF File Overview DSPF File Net Parasitic Section Schematic Inverter Schematic Inverter With Parasitics DSPF_include DEV=SCH Schematic Mode Summary Applies to Mode DEV=SCH Only What is a Post Layout MOS After Extraction? DSPF_include DEV=DSPF Layout Mode Summary Mixed Mode Why Keeping 3 different Modes? Multi Simulations Are Supported Example using AMS How to Deal With Non-Existing Nodes Standard Parasitic Exchange Format Objectives Extracting Multiple Parasitic Netlists From One Parasitic Networks Database Apply DSPF_INCLUDE Filters Remove Components By Threshold Setting No Convergence During Post-Layout Simulation Lab Time Summary VIII

11 Module 7: Extract Essentials Objectives Eldo Post-Processing Generalities EZwave Measurement Tool Eldo Post-Processing Capabilities Wave Definition With.DEFWAVE Wave Expression Usage Maximum of Long List of Waveforms Macro Definition and Use Using Macros for DEFWAVE and Controlled Sources Simulation Outputs Objectives Measurements in Eldo YVAL, AVERAGE, MIN and MAX Functions EXTRACT YVAL Syntax LABEL Y-axis Value of a Waveform Errors in Extract Statements Extract Outputs Results Browsing for Extract AVERAGE MIN and MAX Usage Display Yval Extracted Data as a Waveform Expression Parameter EXTRACT With Wildcards Recursive EXTRACT for Subcircuits Recursive and Wildcard Example IX

12 Large Scope of Application Objectives Fall/Rise Time, Period, Frequency Measurements Occurrences / Which Value is Returned? Returns X-axis value at a Crossing Point Returns a X-axis value with EZwave Extract the Number of Edges Settling Time Definition Settling Time Extraction Overshoot/Undershoot Measurement Overshoot/Undershoot Extract Propagation Delay Measurement Launching an OP Analysis at a Time Determined by an Extract Lab Time Summary Module 8: Extract Syntax Objectives AC Extract Examples Extract Frequency at Which Maximum y-value Occurs Opamp: Trade-off Between Bandwidth and Stability Gain and Phase Margin with EZwave Gain Margin Calculation XYCOND Function CROSSING & XTHRES Functions Gain and Phase Margin with EXTRACT X

13 Gain and Phase Margins Results Objectives DC Extract Generalities P() Extracting Global Parameter Value M() Extracting Model Parameter Value Extract Device and Model Parameters Extracting BJT Characteristics Extract the Computed Value of a Dipole Operation Region of a Transistor in a Subckt Objectives Sweep Analyses Generalities Sweep Analysis Example Min and Max of an Extract over Multiple Sweeps Removing an EXTRACT from an ALTER Objectives Number of EXTRACTs Side Effects Post-Simulation Extraction Reduce the Simulation Time with Autostop Using Autostop with VECT Extract Vector Size versus Number of Runs General Extraction Language Summary (GEL) Transient Extraction Language (TEL) Functions TEL versus GEL before AMS TEL: AFTER, BEFORE, OCCUR Examples Reduce the Measurement Window XI

14 MEAS Generalities Fundamental Measurements with.meas One Possible.MEAS Definition Summary of Best Performance Settings Objectives Tcl Concept Recommended Flow Extending Eldo With Tcl Tcl Usage Macros versus Post-Processing USE_TCL Command Creating Macro-Like UDFs With Tcl wfc Function More Complex Example of wfc Usage Extract Time When Duty-Cycle is Greater Than Threshold Creating an Extract with Tcl Lab Time Summary Module 9: Automate Design Checking Objectives Use SOA for Automatic Design Checking Safe Operating Area (SOA) Simple Example Results Browsing for SOA Violations AMS Results Browser Objectives XII

15 Reduce the CPU Time CHECKSOA Other Syntax Objectives Check Syntax for Devices SOA Device Examples Check Syntax for Models Checkable Parameters Check Syntax for Expressions Conditions in SETSOA SOA IF/ELSE Examples SOA Report AMSRB & SOA Report Plotting Safe Operating Area Limits SOA Identifier Format SETSOA Static_Check Syntax SETSOA Static_Check Example Objectives Introduction to High Impedance High Impedance Node Checks Algorithm Details High Impedance Slow Down Factor HiZ R HiZ TWINDOW HiZ TWINDOW Effect HiZ TYPE XIII

16 .HiZ SCOPE HIZ SCOPE Effect High Impedance Detection Configuration Example Pass Gate HiZ Plots with EZwave Make the HiZ Report Reading Easy How to Start? Lab Time Summary Module 10: Conclusion Objectives Eldo Platform Summary Release Conventions What About the Next Releases? Mentor Graphics Support Documentation Search Results Example Stemming Support Available DSM Courses on Appendix A: Models Objectives Model Libraries Introduction Model Library Syntax MOS Model - Binning More and More Effects are Included XIV

17 Model File Selection Library Overview INCLUDE Command INCLUDE and Monte Carlo Simple Definition With.LIB Library Definition With.LIB KEY Delete Library With.DEL Basic Library Encryption Advanced Library Encryption IP Protection for the Foundry IP Protection for the User Objectives Using Behavioral Verilog-A Models Within Eldo Use of a Verilog-A Model in a Netlist Example - Verilog-A Model in a Netlist Hierarchical Verilog-A Model Example Verilog-A Model Example Generic and Param Usage Compilation Case of Compiled Library Not in the Current Directory CommLib QuickStart Verilog-A HDL Command for VerilogA as X-Statements Objectives Spectre Compatibility Working with Multiple Languages XV

18 Objectives EldoD_sp Generalities EldoD_sp Procedure EldoD_sp Outputs Objectives HSPICE Compatibility HSPICE Compatibility Mode Hybrid Compat Mode Device Models Compatibility Objectives Introduction Library/Cell/View Basics More on Views CDF Concepts CDF : Description of SimInfo Fields CDF as an ASCII File Access to Conversion Tools Simple Conversion Complex Conversion Conversion Tool Overview Importance of the Cell Type Conversion Flow Appendix B: EZwave Objectives Basic EZwave Features XVI

19 Advanced EZwave Capabilities EZwave Elements of the Interface Joint Waveform Database (JWDB) wdb and.swd Files Invoking EZwave EZwave Integration in Artist Link How to Start EZwave in Artist Link Documentation Color Scheme Memory & Disk Space Shortage Detection EZwave Memory Management Improvement (AMS15.1) Module Objectives Toolbar Mouse Strokes The Find Capability for Plotted Waveforms Find Button Waveform List EZwave Additional Tools EZwave Video Tutorials Module Objectives Pick-Point Tool New in AMS13.2 Release Pick-Point Mode Pick Points Capabilities Pick Points Default Settings Pick Points Specific Behavior Module Objectives XVII

20 Measurement Tool Plotting All the Waveforms with the Same Name Tandem Mode Example Tandem Mode vs Iterative Simulation Module Objectives Waveform Calculator Using the Waveform Calculator Module Objectives Waveform Compare Tool Waveform Compare Wizard Comparison Method Selection Viewing Waveform Comparison Results Algorithm X_min, x_max, y_min, y_max Tolerance Area Tolerance Tube Module Objectives Performing Power Analysis in EZwave Power Analysis Window Running the Analysis Power Table Module Objectives File > Save Menu Tcl File Example Getting Help XVIII

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