Introduction. SDIO Bus

Transcription

1 In this Application Note we discuss the SDIO Protocol, the challenges involved in Protocol breakdown and PGY-SSM comprehensive Protocol Analysis solution for decode and analysis. Introduction. SDIO offers extended capability to what the SD Card offers by providing High Speed Data I/O Functions separately or combined with memory capability with in the Card. Host devices supporting SDIO can connect the SD Slot with I/O devices like Bluetooth, Wireless LAN, GPS Receiver, Digital Camera etc. As many as seven Functions can be mapped into the SDIO I/O s. SDIO is widely used Bus for interfacing modem (device) to application processor (Host). SDIO is used for Data exchange between host and device. Initially, SDIO bus used operate at 50MHz (SD2.0) Specification. Current generation system use 200MHz (UHS I) SD3.0 bus. Like SD, SDIO capable host generates the Clock Signal at 400 KHz and scales up to the specific frequency as per the standard supported by the device. The Host issues specific commands over the CMD line and decides the next course of action based on the Response received by the Device. SDIO uses either 1-bit or 4-bit data transfer between host and device. SDIO Bus SDIO Bus has clock, command and 4-bit data bus wide. SDIO provides the flexibility to switch at different speeds ranging 25MHz to 200MHz, bus mode in SDR /DDR and bus width at 1-bit or 4-bit. This offers application to use the bus appropriate mode without consuming many system resource and power. 1

2 SDIO Interfaces. SDIO supports multiple card types with different Data Rates and Signaling Modes. The below Table provides a detailed comparison of different SDIO Interfaces along with Maximum Data Rates supported and Signaling Levels. SDIO Card Type Mode Non UHS Low Speed Non UHS Full Speed Non UHS High Speed Full Speed UHS-I UHS-II * High Speed SDR12 SDR25 SDR50 DDR50 SDR104 FD156 HD312 Interface SPI 1-Bit SD Optional SPI 1-Bit SD SPI 1-Bit SD Clock Range Maximum Data Rate KHz 200 KB/s Signaling Mode 3.3 V 0-25 MHz 12.5 MB/s 0-50 MHz 25 MB/s 0-25 MHz 12.5 MB/s 3.3V 0-25 MHz 25 MB/s 12.5 MB/s 25 MB/s 50 MB/s 50 MB/s 104 MB/s 156 MB/s 312 MB/s 3.3V MHz 0-52 MHz 1.8V 0.4V LVDS * UHS-II is backward compatible with UHS-I. * Prodigy supports up to UHS-I Protocol Analysis with PGY-SSM and UHS-II Protocol Analysis with PGYUHS II Protocol Analyzer. The Command Set. SDIO introduces IO_SEND_OP_COND (CMD5) to inquire the Voltage Range needed by the I/O Card. SDIO also adds two more data transfer Command instructions to support the I/O functionality. These Commands are IO_RW_DIRECT (CMD52) is a Fast I/O access command and IO_RW_EXTENDED (CMD53) allows Fast access with Byte or Block addresses. CMD5: IO_SEND_OP_COND 2

3 CMD5 is identified by 6-bit Command Index set at b. The supported minimum and maximum values of VDD are set in the I/O OCR Register which is a 24-bit Register in CMD5. S18R is the Switching to 1.8V request bit R4: Response to IO_SEND_OP_COND I/O Functions is a 3-bit field and indicates the number of I/O Functions supported by the Card. S18A is set indicating switching to 1.8V is accepted by the device. I/O OCR indicates the supported Range of Voltages supported. CMD52: IO_RW_DIRECT The following operations are accomplished by CMD52 in SDIO by writing into specific bits in Common Command Code Register in Common I/O Area (CIA), which otherwise uses separate Commands in SD. I/O Reset Abort Block Transfer Set Block Length in Function Basic Register (FBR) Set Bus Width. CMD53: IO_RW_EXTENDED CMD53 provides the option to Read and Write multiple I/O Registers with a Single Command. The Read and Write Single/Multiple Blocks is accomplished with CMD53 command unlike SD Card that uses multiple commands to accomplish this. Protocol Analysis requirements & Challenges. IP development cycle would include IP RTL design and verification, Prototyping, tape out, electrical and Protocol Validation, driver software validation and reliable system operation. At different stages design and test/verification engineers face different types of bugs in product. These are caused due to design, manufacturing process, Operating System and interoperability problems. A Firmware validation team would require the Protocol Analyzer to verify the effectiveness of the SDIO Controller Driver for a 3

4 specific Operating System. To locate and identify these design bugs, testing tool such as Protocol Analyzer plays a significant role. In case of SDIO, based on electrical characteristics and Protocol, it offered significant challenges to debug SDIO Protocol. Some of these challenges are: Voltage and Frequency Switching Capture. The Protocol Analyzer should be able to capture the switching of Voltage form 3.3 Volts to 1.8 Volts based in the capability of the card and the associated events. More over the Frequency of operation starts at 400KHz and then switches to higher speeds like 25 MHz and higher up to 200MHz in SDR104 mode. The Protocol Analyzer should be able to exactly decode the frequency of operation and the associated commands and Response from the Host and Device respectively that is responsible for the switch in frequency of operation. SDIO Register Decode & Data Block Capture. Now we know that SDIO accesses the information in Common I/O Area s Card Common Control Registers (CCCR) and Function Basic Registers (FBR) Registers to communicate with the device using CMD52 & CMD53. It s important that the Protocol Analyzer supports the complete decode and breakdown of these Registers with specific Arguments as applicable. The I/O section of the Card has the OCR Register that determines the Voltage Range supported and is accessed by CMD5. Different Functions in the Card support different Voltage Range. The Voltage Range supported by each function should be able to be accessed by decoding the CIS of the Card. SDIO Function Mapping. SDIO Cards may have up to seven I/O Functions with a total of over one Lakh Registers possible for each function. For a better visibility the Protocol Analyzer should support mapping of these Functions to specific Function Types like Bluetooth, Wireless LAN etc. Protocol Error Reporting. For an easy analysis and debug, the Protocol Analyzer should support the decoding the amount of errors and Error types obtained for the Capture. This should cover CMD CRC Error, RES CRC Error, Data CRC Error, Flag set Error, No Response to the Command and Reserved Command Error. SDIO Event Capture. All SDIO Hosts Support Level Sensitive Interrupts issued by multiple Functions within the Device. Interrupt generation by the Cards is an important feature in SDIO as the Cards expects faster Response from the Host to interrupt conditions. The Protocol Analyzer should have the capability to access these Interrupt conditions and the exact timing of its occurrence on the Bus. Skew Adjustment and Voltage Tuning. Clk, Cmd, Data signals have different path from Probe Tip to Protocol Decoding Logic in FPGA. At 200MHz it is essential to adjust Skew between these signals. SDIO Communication in burst mode also causes DC imbalance at Protocol Analyzer's input. This is due to unequal transitions affecting threshold Voltage for identifying Logic 1's & 0's. Voltage Tuning is essential in these scenarios to adjust the threshold voltages to identify Logic 1 s and Logic 0 s. Probing Challenges. Probing is one of the critical challenges in capturing SDIO protocol at higher speeds. The single ended SDIO signals causes Crosstalk and Ground Bounce at 200 MHz that results in the receiver incorrectly 4

5 identifying 1 s and 0 s. The signal is also prone to reflections at these speeds affecting the overall signal integrity of the DUT under consideration. Care must be taken so that the probe doesn t load at the tip connected to the DUT with reduced impedance. This affects the rise time of the signal thereby degrading the waveform shape and making it uncertain for the Analyzer to properly decode 1 s and 0 s. A well designed anti-reflective active probe with close coupling to Ground for all signals is required to avoid issues that might arise from Signals at higher frequency. PGY-SSM SD/SDIO/eMMC Protocol Analyzer addresses the above challenges effectively with Unlimited Protocol Capture Memory and a simple and easy to use GUI that provides a Listing Window of the decoded Protocol along with important features to locate specific User Events, Custom views, Advanced Triggers, Pin-Point Errors, Statistical analysis and Pictorial Protocol information with Histograms and Trend plots. This coupled with Offline Trace analysis capability makes PGY-SSM a versatile solution for multiple teams in different locations. SDIO Function Mapping Specific Functions as defined by the Protocol can be mapped to the Function types. This provides a clear visibility to the designer of the Functions available in the device and mapped to specific Function # for easy analysis. Register Decoding with PGY-SSM PGY-SSM Listing Window decodes and breaks down the Registers to specific fields & Arguments as defined by the Protocol along with Bus Mode, Timing and Error conditions. The search and Filter functions helps in locating specific events to easily access the events of interest with search function and isolate specific events with Filter Function. 5

6 SDIO Mode & Frequency Switch Protocol Error Reporting PGY-SSM provides a direct report of the amount of errors within the data captured. These errors can be pin-pointed in the Analysis View with the Search Function. Errors Covered: CMD CRC Error, Data CRC Error, Flagset Error, Reserved Commands, Response Mismatch & Missing Response. 6

7 SDIO Event Capture & Reporting The GUI provides a Separate Event Viewer to track specific events such as Interrupts with duration information. This has the flexibility to Locate specific events in the Listing Window. 7

8 Skew Adjustment and Voltage Tuning. PGY-SSM(Lite) provides advanced settings to De-skew delays Up to 2.3 ns that is sufficient to compensate delays at 200 MHz for accurate decoding without CRC Errors. Voltage Tuning provides option to adjust Threshold Voltage to identify 1's & 0's. SDIO Probing. The active Probes supplied with PGY-SSM offers very minimal Probe Loading to the DUT for analysis. The probes are specifically designed to address challenges in Probing emmc/sd/sdio signals. A passive circuit in the Probe takes care of the Reflection at higher frequencies keeping the Signal Integrity offered by the Protocol Analyzer intact. The probes support 200 MHz DDR bandwidth to capture the signals Error Free. The Probes come with Flying Lead set with Berg Connection option as well as Solder-able tips to conveniently connect to the DUT. 8

9 Example PGY-SSM Probe setup with DUT 9