Survey of Circuit Board Warpage During Reflow
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1 Survey of Circuit Board Warpage During Reflow Michael J. Varnau Delphi Electronics & Safety 8/20/07
2 Table of Contents Overview of Goals & Objectives Overview of uct Initial Circuit Board Characterization (Screening Experiment) Detailed Circuit Board Characterization Sampling / Conditioning Methodology Warpage by Condition» Whole Board» PBGA only Area (30 mm square) Multivariate Analysis: Temperature / Lot / Condition» Whole Board» PBGA only Area Statistical Prediction of Warpage Conclusions Future Directions
3 Overview Goal: Understand typical warpage characteristics of ECM Circuit Board during production solder reflow process Measurement Methodology Tool: Akrometrix Thermal Shadow Moiré Interferometer PS400 Simulate production reflow profile» IR Heating from bottom side of device being measured» Requires step height changes to be less than for continuity of measurement Board Asm / Substrate lightly coated with white paint to minimize contrast variation Results The board assembly is too dense to get a meaningful measurement of board warpage» Not possible to find a straight line across any part of board without crossing a component» Step height changes are typically greater than causing computational artifacts Analysis Refocused on unpopulated Circuit Boards Results are summarized for various conditions
4 2007 Engine Control Module Board Assembly TC 3 TC 1 (Btm) TC 2 (Top)
5 Typical Reflow Profile Process 1 = TC Bottom of Board Process 2 = TC Top of Board Process 3 = TC Top of PBGA
6 3 D Surface Plot of Board Assembly at 30 C Computational Artifacts due to large step changes in component heights
7 ECM Bare Circuit Board BGA Mounting Location Thermocouple Location both sides Board suspended on notched rail each end FR-4, type E67 Circuit Board 1.2 mm (0.047 ) thick 6 layer Plated-Thru-Hole 120 mm x 100 mm ENiAu Pad Finish
8 Screening Assessment 3 Boards Board Warpage vs Reflow Temperature 1000 Board Warpage vs Reflow Temperature Warpage = Max - Min Warpage (microns) Board K Board L Board M Reflow Temperature (C) Estimated value, due to Computational artifact Board K 30 C Diagonal Plot Board K 220 C Diagonal Plot Board K 30 C Diagonal Plot
9 Board K Surface Profile During Reflow 27 C 117 C 147 C 180 C 208 C 224 C
10 PBGA Pad Area Warpage vs Reflow Temperature 100 PBGA Area Warpage During Reflow Warpage = Max - Min Warpage (microns) Board K Board L Board M Reflow Temperature (C) Board K - PBGA 30 C Diagonal Plot Board K - PBGA 220 C Diagonal Plot Board K - PBGA 30 C Diagonal Plot
11 Board K PBGA Pad Area Warpage During Reflow 27 C 117 C 147 C 180 C 208 C 224 C
12 Warpage of Circuit Board Initial Assessment Based on 3 Circuit Boards Warpage is Significant Variation is Large Changes Run to Run (Gets Worse with Subsequent Runs) Warpage vs Reflow Run Average of 3 Boards Warpage (microns) Data Average at 30 C Average at 220 C Reflow Run
13 Sampling Methodology Circuit Boards were Sampled from uction 7 Different days (Nov 29 thru Jan 19, 2007) Taken directly off of Loader for Screen Printer 9 Boards pulled sequentially from input stack Boards were lightly coated with high temperature white paint Rustoleum: White - High Heat Paint Air dried 5 minutes Oven dried C 3 Boards were run within 1 hour of production sampling 3 Boards were baked dry: C 3 Boards were moisture soaked for 168 hours Time is MSL Level 3 maximum condition for IC packages 4 Groups at 26 C / 75% RH (Manufacturing Required Practices for Facilities worst case) 3 Groups at 30 C /60% RH (J-STD-033B MSL Handling Requirements for IC Packages)
14 Analysis Methodology Boards were subjected to Nominal Mfg Best Practices SnPb Reflow Profile Warpage measured / calculated at 13 temperatures Data for PBGA Pad Area was adjusted by 22 microns Remove variation due to topology from solder resist / marking Inherent measurement noise Consistent with standard PBGA warpage analysis methodology
15 Boards Sampled Directly from uction 2000 Board Warpage vs Reflow Temperature (Sampled Directly from uction - 24 Bds from 8 lots) 1500 Warpage (microns) Reflow Temperature ( C)
16 uction Sample - PBGA Pad Area Only Adjusted Warpage of PBGA Pad Area During Reflow Sampled Directly from uction - 24 Bds from 8 Lots Warpage (microns) Reflow Temperature (C)
17 Circuit Boards Baked Circuit Board Warpage - Baked 21 Bds from 7 Lots 2500 Warpage (microns) Reflow Temperature ( C)
18 Adjusted PBGA Area - Baked 80 Adjusted Coplanarity of PBGA Pads - Baked 21 Boards from 7 Lots Warpage (microns) Reflow Temperature
19 Circuit Board Wet Condition 2000 Circuit Board Warpage vs Reflow Temperature After168 hrs at 26C /75% RH or 30C/60% RH 1500 Warpage (microns) Reflow Temperature
20 PBGA Bd Area Wet Condition 80 Adjusted Warpage of PBGA Area of Board After 168 hrs at 26 C/ 75% RH or 30C/60% RH 60 Warpage (microns) Reflow Temperature
21 Multi-Variate Summary of Board Warpage Warpage of Circuit Board versus Moisture Conditioning 3 Samples per Condition H Data -500 Max of Warpage Average of Warpage Min of Warpage TemperatureLotCondition AreaBoard Warpage (microns)
22 Multi-Variate Summary of PBGA Area Warpage PBGA Area of Board vs Moisture Conditioning 3 Samples each Condition Area PBGA H 220 Data Max of Warpage Average of Warpage Min of Warpage Temperature Lot Condition Warpage (microns)
23 Statistical Prediction of PBGA Area Warpage Statistical Prediction of 30 mm sq PBGA Area Board Warpage - SnPb Reflow Profile Solder above Liquidus Warpage (microns) Bd+4.5 Stdev Bd+3 Stdev Bd-4.5 Stdev Bd-3 Stdev Bd Data Max Bd Avg Bd Data Min + 0.7% Spec - 0.7% Spec +0.5% Spec -0.5% Spec -250 Reflow Temperature ( C)
24 Conclusions of Circuit Board Warpage Analysis Warpage Varies Significantly by Lot Board Moisture Content Reflow Pass (Starting in uction Condition) Effect of Moisture Content Is Not Consistent Effect is Significant within a Lot Optimal Condition Varies by Lot, but generally baked dry is worse Warpage of PBGA Area is Large Enough to Impact PBGA Assembly Yields of Large BGAs Pb-Free Reflow profiles will cause more warpage This study was only single part number / single supplier
25 Future Work Develop Standardized Characterization Methodology Sampling Methodology» Random versus Panel / Position» # Lots» # Samples per Lot Moisture Conditioning? Conditions Characterization Temperatures Characterize Additional Part Numbers Characterize Pb-Free Reflow Profile Determine Acceptable Warpage Specifications Solder Reflow Assembly Process Capability» SnPb» SAC Allocate Total Warpage Allowance Between Board and BGA» Optimize Board Cost / Supply / Industry Standards» BGA Cost / Supply / Industry Standards
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