Design and Assembly Process Implementation for BGAs

Transcription

1 ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Design and Assembly Process Implementation for BGAs Developed by the Device Manufacturers Interface Committee of IPC October 25, 2000 Users of this standard are encouraged to participate in the development of future revisions. Contact: IPC 2215 Sanders Road Northbrook, Illinois Tel Fax

2 August 2000 Table of Contents 1 SCOPE Purpose Selection Criteria (Determination of Package Style and Assembly Processes) Technology Comparison APPLICABLE DOCUMENTS IPC JEDEC MANAGING BGA IMPLEMENTATION Description of Infrastructure Land Patterns and Circuit Board Considerations Assembly Equipment Impact Stencil Requirements Inspection Requirements Test Time to Market Readiness Methodology Process Step Analysis BGA Limitations And Issues Visual Inspection Moisture Sensitivity Rework Cost Availability Voids in BGA Unsettled Standards Reliability Concerns COMPONENT CONSIDERATIONS Component Packaging Comparisons and Drivers Package Feature Comparisons Package Drivers Cost Issues Component Handling Thermal Performance Real Estate Electrical Performance Die Mounting in the BGA Package Wire Bond Flip Chip Standardization Ball Pitch Body Size Ball Size Relationships Coplanarity Component Packaging Style Considerations Pin Grid Arrays (PGA) Plastic Ball Grid Arrays (PBGA) Ceramic Ball Grid Arrays (CBGA) Ceramic Column Grid Arrays (CCGA) Tape Ball Grid Arrays (TBGA) BGA Connectors Assembly Considerations for BGA Connectors Material Considerations for BGA Connectors BGA Construction Materials Types of Substrate Materials Properties of Substrate Materials BGA Package Design Considerations Power and Ground Planes Signal Integrity Heat Spreader Incorporation Inside the Package BGA Package Acceptance Criteria and Shipping Format Missing Balls Voids in Solder Balls Solder Ball Attach Integrity Package Coplanarity Moisture Sensitivity (Baking, Storage, Handling, Re-baking) Shipping Medium (Tape and Reel, Trays, Tubes) PCBS AND OTHER MOUNTING STRUCTURES Types of Mounting Structures Organic Resin Systems Inorganic structures Layering (Multilayer, Sequential or Build-Up) Properties of Mounting Structures Resin Systems Reinforcements Thermal Expansion Glass Transition Temperature Moisture Absorption iii

3 August Surface Finishes Hot Air Solder Leveling Organic Surface Protection Noble Platings/Coatings Solder Mask Wet Versus Dry Film Solder Masks Photoimageable Solder Masks Registration Tenting And Capping Thermal Structure Incorporation (e.g., Metal Core Boards) Lamination Sequences Heat Transfer Pathway PRINTED CIRCUIT ASSEMBLY DESIGN CONSIDERATION Component Placement and Clearances Pick and Place Requirements Repair/Rework Requirements Global Placement Alignment Legends (Silkscreen, Copper Features, Pin 1 Identifier) Attachment Sites (Land Patterns and Vias) Big Vs. Small Land and Impact on Routing Solder Mask Vs. Metal Defined Land Design Conductor Width Via Size and Location Escape and Conductor Routing Strategies Via-in-Pad and Impact on Reliability Impact of Wave Solder on Top Side BGAs Top Side Reflow Impact of Top Side Reflow Methods of Avoiding Top Side Reflow Testability and Test Point Access Component Testing Damage to the Solder Balls During Test and Burn-In Bare Board Testing Assembly Testing Other Design for Manufacturability Issues Panel/Sub-Panel Design In-Process/End Product Test Coupons Thermal Management Conduction Radiation Convection Documentation Drawing Requirements Electronic Data Transfer Specifications ASSEMBLY OF BGAS ON PRINTED CIRCUIT BOARDS SMT Assembly Processes Solder Paste and Its Application Package Standoff Vision Systems for Placement Reflow Soldering and Profiling Cleaning Vs No Clean Post-SMT Processes Conformal Coatings De-Paneling of Boards And Modules Inspection Techniques X-Ray Scanning Acoustic Microscopy Feeler Gauge BGA Standoff Measurement Destructive Analysis Methods Assembly Accept/Reject Criteria Voids Solder Bridging Opens Cold Solder Defect Correlation/Process Improvement Insufficient/Uneven Heating Component Defects Repair Processes Rework/Repair Philosophy Removal of BGA (Bake if BGA to be re-used, impact on surrounding components) Replacement RELIABILITY Damage Mechanisms and Failure of Solder Attachments Solder Joints and Attachment Types Global Expansion Mismatch Local Expansion Mismatch Internal Expansion Mismatch Solder Attachment Failure Critical Factors Reliability of Solder Attachments of Ceramic Grid Array Design-for-Reliability (DfR) Process iv

4 August Validation and Qualification Tests Screening Procedures Solder Joint Defects Screening Recommendations GLOSSARY/ACRONYMS BIBLIOGRAPHY AND REFERENCES Figures Figure 1 Area Array I/O Position Comparisons... 2 Figure 2 Area Array I/O Position Patterns... 3 Figure 3 Plastic Ball Grid Array, Chip Wire Bonded... 4 Figure 4 Ball Grid Array, Flip Chip Bonded... 4 Figure 5 Top Surface Including Vias... 5 Figure 6 BGA Construction Figure 7 Top of Molded BOC Type BGA Figure 8 Bottom of Molded BOC Type BGA Figure 9 Cross-Section of A Plastic Ball Grid Array (PBGA) Package Figure 10 Cross-Section of A Ceramic Ball Grid Array (CBGA) Package Figure 11 Cross-Section of A Ceramic Column Grid Array (CCGA) Package Figure 12 Cross-Section of A Tape Ball Grid Array (TBGA) Package Figure 13 BGA Connector Figure 14 Example of Missing Balls on A BGA Component Figure 15 Example of Voids in Eutectic Solder Balls Figure 16 Examples of Solder Ball/Land Surface Conditions Figure 17 Examples of Different Build-Up Constructions Figure 18 Work and Turn Panel Layout Figure 19 Distance from Tented Land Clearance Figure 20 BGA Alignment Marks Figure 21 Solder Lands for BGA Components Figure 22 Good/Bad Solder Mask Design Figure 23 Square Array Figure 24 Rectangular Array Figure 25 Depopulated Array Figure 26 Square Array with Missing Balls Figure 27 Interspersed Array Figure 28 Cross Section of 0.75 mm Ball with Via-in-Pad Structure Figure 29 Cross Section of Via-in-Pad Design Showing Via Cap and Solder Ball Figure 30 Example of Top Side Reflow Joints Figure 31 Example of Wave Solder Temperature Profile of Top-Side of Mixed Component Assembly Figure 32 Heat Pathways to BGA Solder Joint During Wave Soldering Figure 33 Methods of Avoiding BGA Topside Solder Joint Reflow Figure 34 An Example of a Side Contact Made with a Tweezers Type Contact Figure 35 Pogo-Pin Type Electrical Contact Impressions on the Bottom of a Solder Ball Figure 36 Area Array Land Pattern Testing Figure 37 Board Panelization Figure 38 Comb Pattern Examples Figure 39 High Lead and Eutectic Solder Ball and Joint Comparison Figure 40 Effect of Having Solder Mask Relief Around the BGA Lands of the Board Figure 41 Example of Reflow Temperature Profile Figure 42 Breakaway Tabs Figure 43 Standard Scoring Parameters Figure 44 X-Ray Can Be Used to Detect BGA Package Popcorning (Pincushion Distortion) Figure 45 Scanned-Beam X-Ray Laminography Figure 46 X-Ray Laminography Images of CBGA Solder Joints Figure 47 Transmission Example Figure 48 Corresponding Cross-Sections of CBGA Solder Joints Figure 49 Scanning Acoustic Microscopy Figure 50a A Solder Ball Cross Sectioned Through A Void in the Solder Ball Figure 50b Cross-Section of A Crack Initiation at the Ball/Pad Interface Figure 50c A Broken Tab On A TAB Bonded-BGA Package Figure 51 X-Ray Image of Solder Balls with Voids at 50 kv (a) and 60 kv (b) Figure 52 X-Ray Film Image of Voids Figure 53 Example of Voided Area at Land and Board Interface Figure 54 X-Ray Image Showing Uneven Heating Figure 55 X-Ray Image at 45 Showing Insufficient Heating in One Corner of the BGA Figure 56 X-Ray Image of Popcorning Figure 57 X-Ray Image Showing Warpage in a BGA Tables Table 1 Number of Escapes Vs. Array Size on Two Layers of Circuitry... 3 Table 2 Examples of Required Conductor and Space Widths... 3 Table 3 Semiconductor Cost Predictions... 9 Table 4 Ball Diameter Sizes for PBGAs Table 5 Future Ball Size Diameters for PBGAs v

5 August 2000 Table 6 Land Size Approximation Table 7 Future Land Size Approximation Table 8 Typical Properties of Common Dielectric Materials Table 9 Moisture Classification Level and Floor Life Table 10 Environmental Properties of Common Dielectric Materials Table 11 Key Attributes for Various Board Surface Finishes Table 12 Number of Conductors Between Solder Lands for 1.27 mm Pitch BGAs Table 13 Number of Conductors Between Solder Lands for 1.0 mm Pitch BGAs Table 14 Effects of Material Type on Conduction Materials Table 15 Emissivity Ratings for Certain Materials Table 16 Particle Size Comparisons Table 17 Tolerance of Profiles, Cutouts, Notches, and Keying Slots, as Machined, mm Table 18 Standard Scoring Parameters Table 19 Voids in Ball at Interface Table 20 Repair Process Temperature Profiles for FR 4 Material vi

6 August 2000 Design and Assembly Process Implementation for BGAs 1 SCOPE This document describes the design and assembly challenges for implementing Ball Grid Array (BGA) and fine pitch BGA (FBGA) technology. The effect of BGA and FBGA on current technology and component types is also addressed. This document focuses on critical inspection, repair, and reliability issues associated with BGAs. 1.1 Purpose The target audience for this document are managers, design and process engineers, and operators and technicians who deal with the electronic assembly, inspection, and repair processes. The intent is to provide useful and practical information to those who are using BGAs and those who are considering BGA implementation. 1.2 Selection Criteria (Determination of Package Style and Assembly Processes) Every electronic system consists of various parts: interfaces, electronic storage media, and the printed board assembly. Typically, the complexity of these systems is reflected in both the type of components used and their interconnecting structure. The more complex the components, as judged by the amount of input/output terminals they possess, the more complex is the interconnecting substrate. Cost and performance drivers have resulted in increased component density, and a greater number of components attached to a single assembly, while the available mounting real estate has shrunk. In addition, the number of functions per device has increased and this is accommodated by using increased I/O count and reduced contact pitch. Reduced contact pitch represents challenges for both assemblers and bare board manufacturers. Assemblers encounter handling, coplanarity and alignment problems. The board manufacturers must deal with land size issues, solder mask resolution and electrical test problems. Based on industry predictions one would believe that all component packages have over 200 I/Os and are increasing in I/O count. Actually, components with the highest usage have I/O counts in the 16 to 64 I/O range. Over 50% of all components fall into this category, while only 5% of all components used have over 208 I/Os, which may be the threshold for determining the cross-over point between peripheral leaded component style packages and array type formats. Many peripherally leaded, lower I/O count devices, such as memory and logic devices, are being converted to area array packaging formats as either BGAs or Fine Pitch BGAs. Although the percentage of high I/O components used on an electronic assembly is small, they play a big part in driving the industry infrastructure for both bare board and assembly manufacturing. These high I/O components determine the process for bare board imaging, etching, testing and surface finishing. They determine the materials used for fabrication and drive assembly process improvements in a similar manner. The electronics industry has evolved from using throughhole assembly technology in which the component leads went into the printed board substrate and were either soldered to the bottom side of the board or into a platedthrough hole. Surface mounting technology (SMT) has advanced to a stage where the majority of electronic components manufactured today are only available in SMT form. Manufacturing products with SMT in any significant volume requires automation. For low volume, a manually operated machine or a single placement machine may be sufficient. High volume SMT manufacturing requires special solder paste deposition systems, multiple and various placement machines, in-line solder reflow systems and cleaning systems. The heart of surface mount manufacturing is the machine that places the components onto the printed board land areas prior to soldering. Unlike through-hole (TH) insertion machines, surface mount placement machines are usually capable of placing many different component types. As design densities have increased, new SMT package styles have evolved. Examples are fine pitch technology (FTP), ultra fine pitch technology (UPT), and array surface mount (ASM). This latter category consists of the many families of ball or column grid arrays and the chip scale packages (CSP) and Fine Pitch BGAs. These parts are all capable of being placed by machines provided that the equipment has the required positioning accuracy. Increased device complexity has been a primary driving factor for SMT. In order to keep the component package size down, component lead spacing was decreased (e.g., 1.27 mm to 0.65 mm). Further increases in semiconductor integration requiring more than 196 I/Os can drive packages to even closer perimeter lead spacings such as 0.5 mm, 0.4 mm, 0.3 mm, and 0.25 mm. However, the array package format has become the favorite for high I/O count devices. Area array component package styles have a pitch that is much larger than the equivalent peripherally leaded device and is therefore more forgiving during the assembly processes. Ball and column grid arrays were standardized in 1992 with 1.5, 1.27 and 1.0 mm pitch. Fine Pitch BGA array packages standards have established pitches of 1.0 mm, 0.8, 0.75, 0.65, and 0.5 mm. There are proposals for the future to go to 0.4, 0.3 and 0.25 mm. The via pattern for 1