ASSEMBLY YIELD MODEL FOR AREA ARRAY PACKAGES

Transcription

1 ASSEMBLY YIELD MODEL FOR AREA ARRAY PACKAGES SanJay Sharma Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Industrial and Systems Engineering Subhash C. Sarin, Chair Robert H. Sturges Peter Borgesen March 6 th, 2000 Blacksburg, VA Keywords: CSP, BGA, PCB, OPENS, JOINT, PACKAGES, YIELD, DEFECTS ii

2 Copyrights by Sanjay Sharma (MARCH 2000) All Rights Reserved ii

3 ASSEMBLY YIELD MODEL FOR AREA ARRAY PACKAGES SanJay Sharma (ABSTRACT) The traditional design of printed circuit board assembly focuses on finding a set of parameter values (that characterizes the process), such that the desired circuit performance specifications are met. It is usually assumed that this set of values can be accurately realized when the circuit or the assembly is built. Unfortunately, this assumption is not realistic for assemblies produced in mass scale. Fluctuations in manufacturing processes cause defects in actual values of the parameters. This variability in design parameters, in turn, causes defects in the functionality of the assemblies. The ratio of the acceptable assemblies to total assemblies produced constitutes the yield of the assembly process. Assembly yields of area array packages are heavily dependent on design of the board as much as package and process parameters. The economics of IC technology is such that the maximization of yield rather than the optimization of performance has become the topic of prime importance. The projected value of yield has always been a factor for consideration in the advancement of Integrated Chip technology. Due to considerable reduction in the package size, minimum allowable tolerance and tight parameter variations, electronic assemblies have to be simulated, characterized and tested before translating them to a production facility. Also, since the defect levels are measured in parts per million, it is impractical to build millions of assemblies for the purpose of identifying the best parameter. A mathematical model that relates design parameters and their variability to iii

4 assembly yield can help in the effective estimation of the yield. This research work led to the development of a mathematical model that can incorporate variability in the package, board and assembly related parameters and construction of an effective methodology to predict the assembly yield of area array packages. The assembly yield predictions of the model are based on the characteristics of input variables. By incorporating the tail portion of the parameter distribution (up to ±6 standard deviation on normal distribution), a higher level of accuracy in assembly yield prediction is achieved. An estimation of the interaction of parameters is obtained in terms of the expected number of defective joints and/or components and a degree of variability around this expected value. As an implementation of the mathematical model, a computer program is developed. The software is user friendly and prompts the user for information on the input variables, it predicts the yield as expected number of defective joints per million and expected number of defective components (assemblies) per million. The software can also be used to predict the number of defects for a userspecified number of components (less or more than one million assemblies). The area array assembly yield model can be used to determine the impact of process parameter variations on assembly yields. The model can also be used to assess the manufacturability of a new design, represent the capability of an assembly line for bench marking purposes, help modify designs for better yield, and to define the minimum acceptable manufacturability standards and tolerances for components, boards and designs. iv

5 ACKNOWLEDGEMENTS First and foremost, I would like to thank my parents for their everlasting encouragement and help. They have been a constant source of inspiration, this never-ending Master s Degree would not have been possible without their support. My deepest gratitude goes to my advisor, Professor Subhash C. Sarin, for his valuable assistance, guidance and expertise, not to mention the numerous pep talks. I commend him for his academic achievement and his affable personality. Working with Prof. Sarin has been a great learning experience for me. I thank him for this excellent opportunity (to work in CSP/DCA Consortium ) and wish to continue working with him in near future. I would like to extend my thanks to Dr. Peter Borgesen, who invested a great deal of his time in guiding me through this research. I appreciate the opportunity to be involved in the consortium work, which led to this research. Dr. Borgesen has been my strongest critic, I thank him for his frank opinions and expert advises. My sincere thanks also goes to Dr. Robert H. Sturges, for his comments and interest in my research. I take this opportunity to thank all my friends: Vinayak, Mahesh, Aishwarya, to name a few, for their help and patience. And last, but not the least, I am grateful to Lovedia Cole for her assistance in my successful completion of this program, she is the best. v

6 TABLE OF CONTENTS Abstract iii Acknowledgement.v List of Figures.x List of Tables.xii 1.0. CHAPTER 1: INTRODUCTION AND PROBLEM STATEMENT 1.1. Surface Mount Technology Component Flip Chip Devices Chip Scale Package Ball Grid Array Package Flip Chip CSP & Flip Chip BGA Printed Circuit Board Assembly Material Preparation Flux Application / Solder Paste Deposit Component Placement Solder Reflow Inspection Reliability Testing Problem Statement and Research Objective Thesis Overview.19 vi

7 1.7. Conclusion CHAPTER 2: LITERATURE REVIEW 2.1. Introduction Component Related Issues Board Related Issues Assembly Related Issues Assembly Defects Review of Yield Models Mixed Technology Assembly Process Monte Carlo Method for Area Array Device Conclusion CHAPTER 3: MODEL DEVELOPMENT 3.1. Introduction Model Concept Assumptions Variables Considered in the Mathematical Model Mathematical Expressions / Formulae Notations Determination of Probabilities Yield Determination Methodology for Yield determination...71 vii

8 3.10. Discussion on the number of data points to be considered on an input distribution Conclusion CHAPTER FOUR: SOFTWARE DEVLOPMENT / USER'S MANUAL 4.1. Introduction Install / Un-install Instruction Overview of yield model computer program Error / Information Messages System Input Empirical / Experimental / Non-Normal Distribution Format of Data in Input Text File File Preparation for Empirical / Experimental Distribution Processing of Data Run Time Yield Calculation Modules System Output Conclusion CHAPTER 5: YIELD PREDICTIONS 5.1. Introduction Monte Carlo Approach Yield Prediction.130 viii

9 5.4. Yield estimation: Package Type Yield estimation: Package Type Run time comparison of the New Methodology and Monte Carlo method The use of proposed methodology to study the effect of Design Parameters Conclusion CHAPTER 6: CONCLUSION REFERENCES APPENDIX VITA 237 ix

10 LIST OF FIGURES FIG Representative diagram of Through-Hole & Surface Mount Assembly.. 4 FIG Diagram of a Generic Flip Chip Package.6 FIG Diagram of a Generic Chip Scale Package..8 FIG Diagram of a Generic Chip Size Package 8 FIG FIG FIG FIG FIG Diagram of a Generic Ball Grid Array Package...9 Diagram of a Generic Flip Chip CSP/BGA Package.10 Process Flow Diagram of a SMD Assembly..13 Generic Reflow Profile for a CSP/BGA Assembly 16 Schematic of Bump Height Calculation..26 FIG Digital Image of a Flat / Damaged Bumps 49 FIG Sample image of Warped package FIG Sample image of Warped package FIG Schematic of joint height, bump height and distance of separation (flat boards and components...58 FIG Schematic of joint height, bump height and distance of separation (for an assembly of warped components on flat board. 59 FIG Schematic of Warpage Calculation. 61 FIG FIG Schematic for generating the bump heights Schematic for generating distance of separations...76 FIG Representation of monotonically increasing probability value vs. the number of data points on density functions...94 FIG Introductory Screen of Assembly Yield Model Software 104 x

11 FIG Input screen for bump height as a direct input 109 FIG Input screen for bump height from solder volume and component pad diameter variation FIG FIG FIG Input screen for solder paste deposit on board and board pad details 111 Input screen for selecting warpage or no warpage.113 A sample input file representing the bump location on package..115 FIG Input Screen for Board Warpage in both X & Y directions 117 FIG Input Screen for Component Warpage in both X & Y directions..117 FIG Input screen for entering the total number of components FIG FIG Sample input file representing an experimental distribution..121 An example representing file preparation for empirical / experimental distribution.124 FIG FIG FIG FIG FIG Yield Prediction for a user defined total number of components..128 Yield Prediction at the level of one million packages (ppm)..128 Schematic of solder bump location on Package Schematic of solder bump location on Package D Surface plot of board pad size vs. bump volume variation FIG D Surface plot of board pad size vs. component pad size variation 170 FIG D Surface plot of component pad size vs. bump volume variation FIG FIG D Surface plot of board pad size vs. board warpage variation D Surface plot of board pad size vs. board warpage FIG D Surface plot of board pad size vs. solder paste deposit on board xi

12 LIST OF TABLES TABLE 3.9.1a. A sample of 200 data points on bump volume and component pad size (input) density functions..78 TABLE 3.9.1b. A sample of 40,000 generated bump height and their probabilities...79 TABLE 3.9.1c. A sample of 200 empirical bump heights and probabilities converted from 40,000 generated bump heights TABLE 3.9.2a. A sample of 200 data point on the component warpage density functions in both the X and Y directions..83 TABLE 3.9.2b. A sample of 40,000 values of warpage function...84 TABLE 3.9.2c. 200 values of warpage function (for location 1) and its probabilities based on the combination of warped components and flat boards TABLE generated bump heights and its probabilities and 200 values of distances of separation (L= 1) and its probabilities. 87 TABLE Characteristics of input data used for the sample study...93 TABLE Details on the probability values for individual cases 93 TABLE Expected number of defective joints (out of one million joints)...95 TABLE Number of defective joints from Monte Carlo Method (10 6 iterations) 95 TABLE Comparison of yield values estimated from the new methodology and those predicted from Monte Carlo based approach...96 TABLE Summary of yield predictions for Package 1 Case Study TABLE Summary of yield predictions for Package 1 Case Study TABLE Summary of yield predictions for Package 1 Case Study TABLE Summary of yield predictions for Package 1 Case Study xii

13 TABLE Summary of yield predictions for Package 1 Case Study TABLE 5.4.6a. Summary of yield predictions for Package 1 Case Study TABLE 5.4.6b. Summary of yield predictions for Package 1 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE 5.5.3a. Summary of yield predictions for Package 2 Case Study TABLE 5.5.3b. Summary of yield predictions for Package 2 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE Summary of yield predictions for Package 2 Case Study TABLE Defect in ppm, bump volume variation vs. board pad size TABLE Defect in ppm, component pad size variation vs. board pad size TABLE Defect in ppm, bump volume variation vs. component pad size.172 TABLE Defect in ppm, board warpage variation vs. board pad size 174 TABLE Defect in ppm, board warpage vs. board pad size 175 TABLE Defect in ppm, solder paste deposit on board vs. board pad size..177 xiii

14 CHAPTER ONE: 1.0. INTRODUCTION Recent years have seen tremendous growth in the electronic packaging industry. Due to the volatile nature of this industry, merits of the processes and solutions involved have to be determined in their infancy. Planning and development of new products and processes have to be in accordance with the already established infrastructure in surface mount assembly markets. Some of the general trends that will drive the assembly process in next five years include, 1) smaller, faster and lighter assemblies with an ever increasing levels of functionality, 2) shortened product life cycles, and 3) highly integrated chip with large number of interconnections and finer lead spacing. Worldwide consumption of electronic components continues to increase rapidly. The chip sizes are decreasing, but at the same time assembly and material costs are rising. In order to achieve cost effective and reliable electronic products, the equipment utilization needs to be improved and, the assembly, component and board related parameters ought to be closely monitored and controlled. In order to sustain upward growth in electronic packaging technology, the companies have to develop new and improved designs, manufacture components and boards with minimum variability, use standard materials and optimize the assembly process. Since different elements of the products, such as components and boards have to be developed, tested and used in an application within a short span of time, designers are increasingly relying on new development tools rather than the traditional prototype / manufacturing methods. Several analytical tools such as Finite Element Modeling, 1

15 Mechanical Modeling, Placement Yield Modeling, Cost Modeling etc, are being used in the development, testing and trial runs of new packages and assemblies. This research consists of developing an additional tool, namely "Assembly Yield Model", to predict the assembly yields of devices that have I/O s distributed in an array format (area array packages). The "Area Array Yield Model" can be thought of as a virtual assembly process that uses mathematical expressions to evaluate the interactions of the package, board, and assembly related parameters and predict assembly yields. It can be used to predict the assembly yield for up to one million or more packages and can consider normal, standard or empirical input distributions. This tool can be used by the design / process / quality engineers for projecting short term yields, based on immediate inspection data, or for long term yields using the best available technical judgement on how much can be learned from the individual parameters in the model. If used appropriately, the above mentioned models / tools can help not only in reducing cost and improving design but also in producing advanced and reliable products SURFACE MOUNT TECHNOLOGY By definition, SMT (Surface Mount Technology) is a process to mount electronic components on printed circuit boards [15]. SMT provides a quantum leap over throughhole technology to produce state-of-the-art miniaturized electronic products. Implementation of this technology has enabled the manufacturing of reliable assemblies at a reduced weight, volume and cost. It is essential to have a comprehensive understanding of the surface mount assembly process to be able to evaluate, predict and improve the assembly yields. 2

16 The surface mount technology has witnessed a tremendous growth in scope and technical complexity since the late 1980's. Schematic of a typical surface mount assembly and a through-hole assembly is shown in Figure Compared to the through-hole technology, the most notable benefits resulting from the SMT are significant savings in weight and profile, real estate, and electrical noise reduction [15]. There are three major types of SMT assemblies: Type I: Components used are restricted to SMCs (Surface Mount Components). The components can be active or passive. The assembly can be single-sided or doublesided. Type II: Both the surface mount and through-hole components can be used. The components can be assembled on top or bottom side of the (PCB) printed circuit board. Type III: The topside of the board contains only through-hole components while the bottom side contains only SMCs. It can be considered as a subset of Type II assemblies. Limitations of SMT include requirements of a complicated infrastructure combined with extensive capital investment, increased component density on the PCB and associated thermal effects. An increase in component density requires the use of packages with much finer pitch (lead spacing) and fine routing techniques on the board [15]. 3

17 Figure 1.1.1: Schematic of a Through-Hole and a Surface Mount assembly 4

18 The three main constituents of electronic packaging technology are: 1) package, 2) board, and 3) assembly process. Brief descriptions of each of these constituents are given below TYPES OF SURFACE MOUNT COMPONENTS: A typical surface mount component consists of an electronic circuit etched onto a silicon die and possesses leads for interconnection with the printed circuit boards. However, with the increased demands for miniaturization and functionality, new generations of components are being used in today's electronic packaging industry. The surface mount components can be classified into four different categories. Each of these packages may have different construction features, performance and reliability Flip Chip Packages: Also known as DCA (Direct Chip Attach), the Flip Chip Assembly process consists of attaching bare silicon die on to a printed circuit board (PCB). The attached component is then underfilled with encapsulants for improved interconnection and reliability. The underfill process is inherently slow and increases the assembly time. These packages consist of pitches in the range of 4.00 mil to mil and a low overall profile. The schematic of a typical Flip Chip Package assembled on a PCB is shown in Figure Chip Scale or Chip Size Packages: These packages consist of a silicon die mounted onto a flexible or rigid substrate with the solder bumps on the bottom side. The interconnection between the die and the 5

19 Figure 1.2.1: Generic Flip Chip Device 6

20 solder bumps are achieved using wire bonds. These packages have a relatively larger pitch size compared to the DCA packages. Typically the pitch varies between 0.5 mm (~20 mil) to 1.00 mm (~40 mil). The chip scale packages (CSPs) can be easily reworked and are more robust than the bare die flip chip packages. Schematic of a Chip Scale Package (where the size of a package is approximately 1.2 times the size of die) is shown in Figure , while that of a chip size package (where the size of a package is approximately equal to the size of the die) is shown in Figure Ball Grid Array Packages: Ball grid array packages (BGAs) are area array (interconnection leads are below a package, distributed in an array format) devices that offer an alternative to decreasing electronic package profiles while increasing functionality [17]. A typical BGA device consists of a High Input / Output (I/O) die mounted on a multi layer substrate using wire bonding techniques. Bottom side of substrate contains an array of solder bumps. These packages have pitch sizes varying from 1.00 mm (~40 mil) to 1.50 mm (~60 mil). BGA packages have overall profile larger than those of the CSPs. The schematic of a ball grid array package is shown in Figure Flip Chip CSP & Flip Chip BGA Packages: Flip chip CSP / BGA packages can provide the board real estate saving that is inherent in area array interconnect packages and also give electrical performance advantages of flip chip attach. The major components of a flip chip BGA package, as shown in Figure 1.2.4, are a substrate (laminate) containing die and an epoxy underfill between the die 7

21 Figure : Generic Chip Scale Package Figure : Generic Chip Size Package 8

22 Figure 1.2.3: Generic Ball Grid Array Package 9

23 Figure 1.2.4: Generic Flip Chip - CSP/BGA Device 10

24 and substrate. These packages combine the advantages of BGA and Flip Chip technology PCB (Printed Circuit Board): The PCB (printed circuit board) is a substrate of epoxy glass or other material upon which patterns of conductive traces are formed [15]. The PCB may consist of rigid or flexible substrate and can have single, double or multi-layer configuration. Functions of PCB include conducting current, providing mechanical support, securing the components in a fixed position and providing a common platform for connecting different elements of an electronic circuit such as resistor, transistor, IC chips etc. The choice of a substrate material depends on the application. One of the most commonly used substrate material is FR-4 (Fire Retardant Glass Laminate). This substrate is a composite material consisting of epoxy (resin) and glass fiber (base material). The resin provides ductility while structural strength is given by the base material [15]. The desirable features of PCBs to be used in SMT assembly process includes cleanliness, planarity, solderability of the contact areas (such as pad), proper solder mask finish, minimum thickness variation and resistance to warpage (distortion in shape) ASSEMBLY Assembly of a surface mount device starts with the material preparation of both the board and component followed by flux application or stencil printing, inspection / 11

25 placement of the device by the placement machine followed by solder reflow. Once assembled, they may be inspected by the operator for immediate defects and then subjected to further processes. In order to ensure a "zero defect" or "close to zero defect" assembly, it is essential to ensure that the parameter variations are within acceptable limits. Flowchart of a generic SMT assembly process is shown in Figure This section presents a very brief description of the individual assembly steps Material Preparation: Characteristics of the individual materials play important role in affecting assembly yield. Higher assembly yields can be achieved if proper material preparation is ensured. Some of the common material preparation steps include: bake out for moisture sensitive packages board cleaning to eliminate any debris or oxidized surfaces board support in case of assemblies with thin board inspection of packages for any apparent defect Flux Application / Solder Paste Deposit Based on the application, the surface mount components can be assembled in a flux only environment or with solder paste deposited on the board. One of the prime reasons for using solder paste on board is to mitigate the effect of volume and coplanarity variations. One of the techniques, among dispensing, stencil printing or pin transfer can be used to deposit the paste on to pad. Stencil printing is the most commonly used method. In stencil printing, the solder paste is forced onto the contact pads (on PCB) 12

26 FIGURE 1.4.1: Process flow for the assembly of a Surface Mount Device to a Printed Circuit Board (PCB) 13

27 through stencil apertures, which have similar patterns and an added clearance on all sides (horizontal plane). Some of the factors affecting the paste that transfers to the pad, include the type of solder paste used, alloy, particle size, thickness, size and clearance of the stencil, type and material of squeegee used Component Placement Prior to the reflow process (described below), the components need to be placed accurately on the pad. In general, an automated vision-assisted placement machine is used for the assembly. The pick-and-place machine is one of the most critical and expensive pieces of equipment in the SMT manufacturing line [15]. The components are placed in trays or slots provided in the equipment. An automated head is used to pick the device. The in-built vision system in the placement machine is used to locate the fiduicials on the board (for proper alignment) and match the pattern (board and device). The device is then placed on to the pads Solder Reflow Reflow (in SMT) is a process to heat the eutectic (63/37 Sn/Pb) solder above its melting temperature to form the metallurgical bond between pads on PCB and solder bumps on the component. Once the components are properly placed on to the substrate, the assembly is sent through reflow system. There are numerous options for the reflow system including infrared, convection, forced convection etc [17]. Typically, a reflow profile is prepared prior to the actual assembly so as to control the different temperature zones in the reflow system. Different package types would require separate reflow 14

28 profiles. Some of the key features of reflow profiles include, ramp up rate, time maintained above liquidus temperature, time spent at maximum temperature, max temperature and ramp down rate. A typical profile used in assembly of an area array device having eutectic solder bumps is shown in Figure Inspection: After the assembled packages leave the reflow oven, they are inspected in order to weed out the unacceptable assemblies. This step provides preliminary information on the yield of assembly process. Some of the most common inspection techniques are mentioned below. Visual inspection to determine skewed, mis-registered or rotated components X-ray inspection to determine voids, bridging or other structural defects Electric testing to determine the electrical continuity of the joint Reliability testing: Reliability of an assembly is a basic requirement for the commercial success of packaging technology. Due to complexity in determining the life and performance of individual assemblies at working or field environment, standard tests are used for predicting the lifetime of the products. There are series of standard tests to determine the reliability of the assembled SMT devices. The reliability testing can be done at three levels: 1) package, 2) board and 3) assembly. Some of the package level tests include high temperature aging, moisture sensitivity, 15

29 Figure

30 exposure to high temperature at reflow, vibration, mechanical, shear test of solder balls, drop test, temperature cycling, highly accelerated stress test etc. Board related reliability tests include dielectric strength, surface insulation resistance, reliability of via structure, thermal cycling etc. Some of the common tests for assemblies are thermal cycling, temperature shock, mechanical torsion, drop, vibration test, high temperature storage, power cycling, bending tests etc. Although a majority of these tests are standards and are specified in JEDEC, IPC, EIA standards, the specifications vary from industry to industry and are also based on the application PROBLEM STATEMENT & RESEARCH OBJECTIVE In the recent years, area array packages such as CSP, BGA, DCA etc, have drawn great deal of attention in the electronic industry due to their leadless structure, compatibility with existing SMT assembly processes and improvement in reliability aspects. Although this technology is expected to meet the requirements of a large segment of the electronic market, several challenges inhibit the widespread use of this technology. The economics of the electronic packaging industry is such that the projection of yield has long been a factor of consideration in the advancement of integrated circuits. Due to the close correlation between high yield and high profits, IC manufacturers strive to maximize yield. As the complexity of the design and manufacturing processes continue to increase, the need for computer aids for maximizing yields has become more important. While most of the defects are due to the inherent variability of the assembly process and the variabilities in component dimensions as well as boards and materials related factors, human and environment 17

31 related parameters also contribute to the defects. With the decreasing pitch sizes, minimum tolerances, tight parameter variations and randomly interacting variables, an effective and systematic approach is desired so that these variations can be expressed mathematically and ultimately used to determine the yield of the assembly process. To evaluate the quality of the IC products, most manufacturers use yield models for their prediction. Yield models not only aid in predicting manufacturing costs of these devices, but also facilitate the process of correction when the yields of various products fall below expectations. The problem that we address can succinctly be defined as follows: Given information regarding the package, board and assembly related parameters (e.g. bump volume, pad size on device and board, component and board warpage etc.) of area array packages, determine assembly yield in terms of number of defective joints in joints per million and number of defective components in parts per million. Our approach in tackling this problem, is to use a mathematical model to express the variability of package, board and assembly related parameters and develop an effective methodology to predict the assembly yield of the area array packages. The yield predictions of the model will be based on the characteristics of the input variables as represented by a standard or empirical distribution. A computer implementation of the proposed methodology will also be developed and it s performance will be compared with a Monte Carlo based approach. There are several component, boards, processes and materials related parameters that affect the assembly yield. While some of the 18

32 variables such as bump volume, pad size, paste volume etc, can be represented by distributions, others such as solderability, wettability, personnel related issues etc, are qualitative in nature and are therefore not incorporated in the model. Some of the qualitative issues affecting the assembly yields are discussed in the subsequent chapters THESIS OVERVIEW: An introduction to electronic packaging and the surface mount technology is provided earlier in this chapter. Various elements of the SMT process including component, board, placement process, solder paste printing and solder reflow process are also discussed. Also, a step by step view of surface mount assembly process of an area array package configured on a standard PCB is provided. The chapter concludes by stating the objective of this research. Assembly defects are caused by the variations and issues related to boards, components, materials and processes. Important aspects of parameters causing defects are discussed in Chapter Two. The issues include variables that can be easily quantified and those that are qualitative in nature. Two different models representing different aspects of the electronic manufacturing are also discussed. The mathematical equations and expressions used in the yield model are outlined and discussed. The central logic / concept of the proposed model is explained in Chapter Three. This chapter also contains a list of parameters considered in the model. The yield calculation 19

33 methodology is explained in great detail, including flowcharts and a sample case. In addition, the notations, expressions for calculating the desired probability and the formulas used for yield calculations are described. Finally, the conclusions based on several case studies executed to develop the methodology of yield calculation are presented. The system architecture, installation instruction and the user instructions of the software developed are provided in Chapter Four. Various navigation tools and the input / output screens are outlined. Also included are the details of various distribution types and instruction for input file preparation for an empirical distribution. Results of several case studies on two different packages are presented in Chapter 5. The yields estimated for one million assemblies, by the model are compared with the yields predicted by the Monte Carlo method. Also provided are some recommendations related to the input parameters for both Package 1 and Package 2. The proposed methodology is also used to study the effect of design parameters. A rough estimate of the run time for both the computer programs (the new model and the Monte Carlo) is outlined in the same chapter CONCLUSION: The PCB assembly industry is undergoing a tremendous change today, similar to the innovations and productivity enhancements found in the Integrated Circuit (IC) semiconductor industry. The integration of technologies have lowered component costs 20

34 and board size requirements whereas the automation has improved throughput and yield. Despite an impressive growth, manufacturers and assemblers are in constant pursuit of an improved and robust assembly process. There are several parameters from different sources such as the device manufacturers, material suppliers, board designers / manufacturers and the end user that affect final yields and economics of the products. This research is an effort to identify, discuss and mathematically represent the variations of some of these critical parameters into a yield prediction tool. There is an immense potential for the use of this tool, especially in the present environment that is characterized by rapid change, short product life cycles and quick-time-to-market needs. 21

35 CHAPTER TWO: 2.1. INTRODUCTION As we approach the new millennium, the electronic industry is being forced to do more, for less. The area array package technology has become a promising technology. Key to the success of this technology depends on the ability of the companies to produce reliable and cheap products in mass scale. Although the electrical, thermal and reliability performances of these assemblies have been sufficiently demonstrated, considerable scope of improvement still exists to develop a robust assembly process. The use of area array devices such as Flip Chips, CSPs and BGAs have been steadily increasing with a promise of exceptionally high assembly yields. The introduction of the fine pitch area array devices is an added step toward the miniaturization of the SMT devices. High assembly yields have also been reported for BGAs and CSPs. The assembly yields of these devices are a prerequisite for their commercial success. Due to the use of high-density microelectronics, the performance requirements from the PCBs have also increased. To achieve higher assembly yields all factors pertaining to components, boards, processes and materials need to be considered. This chapter presents relevant component, board and process related issues. While some of the variables affecting the assembly process can be quantified and are incorporated in the model, there are other issues such as solderability, wettability, human factor etc, that are qualitative in nature and beyond the scope of this research. Two different models representing various 22

36 aspects of the electronic manufacturing industry, such as mixed technology assembly (that uses both through hole and surface mount devices) and surface mount assembly have been reviewed. The review gives a brief idea about different models being used in the industry and outlines the various approaches used by the author(s). The discussion also forms a point of reference for the assembly yield model developed in this research COMPONENT RELATED ISSUES: The yield model assumes that devices and boards used in the assembly are functional and do not possess fatal defects. The component related issues affecting assembly yields can be divided into two broad categories. One that is probable to impose fatal or near fatal defects (before assembly) and, two, variables that may cause defects during the assembly process by itself or in interaction with other board, material or process related variables. Component related fatal defects (that occur before assembly) can be traced to corrosion caused by excessive thermal loads, moisture sensitivity, delamination etc. Some of the additional component defects are missing solder bumps, package cracking, wire sweep, shearing and fracture of ball bond, improper wafer dicing etc. Causes of these defects range from manufacturing methods, materials used to handling procedures. Some of the component related variables that cause defects during the assembly process are discussed below. 23

37 Contact Pad Size Variations: Contact pad sizes for packages having vias, mask opening sizes for SMD (solder-mask defined) devices and the pad sizes for NSMD (non solder-mask defined) packages affect the overall solder bump height variations. During the ball attachment process (on the package) and after the reflow process, a pad size larger than the nominal would result in smaller bump height. Similarly, pad sizes lower than the nominal might lead to greater bump heights. Contact pad size variation combined with bump volume variations and warpage can lead to reduced assembly yields Solder Bump Height Variations: The most commonly used material for solder bumps on packages are 63/37 Sn/Pb eutectic composition (liqidus temperature of 183C) and 5/95 Sn/Pb high lead composition (liqidus temperature of 312C). Some of the other compositions used in solder bumps are discussed in section In case of solder bumps having eutectic composition, height variation due to flat bumps, does not constitute a severe problem. At reflow temperature, when all the solder material is in liquidus phase, the flat bumps spring back to make contact with the pad on board. However, the effect of height variations caused by flat bumps may be significant in case of packages with high lead (5/95 Sn/Pb composition) bumps. Since these bumps do not collapse during reflow, the damage cannot be recovered. For these assemblies, combined variations of solder paste volume deposited on board having eutectic composition and the bump height are considered in yield determination. If the height 24

38 distribution is wide, sufficient paste deposit might be required to avoid opens. For both cases, using eutectic or high lead solder bumps, the height variation needs to be viewed with the change in the component and board curvature (warpage). The effect of height variation becomes critical in the presence of board and / or component warpage Solder Volume Variations: Solder volume variation of bumps on package can be determined using the information on the pad size (on package) variation and the ball diameter variations. Automated and programmable equipments such as CMM (coordinate measuring machine), Voyager View and WYKO surface measurement machine can be used for the measurement of the bump diameter. Assuming the bump to be a truncated sphere, relation between diameter and height (shown in Figure 2.2.3) of a bump can be expressed as: h D = D 2 ( R ) 2 1 Eq where h = bump height, R 1 = pad radius, and D = bump diameter. Volume of solder bumps can be obtained from the expression shown below, 2 2 V = π * h(3r ) h, Eq where V = volume of solder, h = bump height, and R 1 = radius of the contact pad. 25

39 Diameter: D Bump height: h SOLDER BUMP SUBSTRATE Pad Radius: R 1 CONTACT PAD h = D D 2 ( R ) 2 1 Figure 2.2.3: Schematic for determining the solder bump height from solder ball diameter and component pad size 26

40 Variations in the X and Y location of the solder bumps: Deviation in location of the solder bumps on package, combined with positional accuracy of the printed circuit board and placement machine, can effect the assembly yields. Unlike boards that have local and global fiduicials, packages do not have fiduicials that can be used as a reference to measure the offset in X & Y location of solder bumps. Relative measurement of X & Y location of bumps can be used to determine the variation within the array, rather than overall variation. If the package edge is used as reference for the measurement of offset in the location of individual bumps on package, the measurement from the edge of package to bump array within the package may vary by as much as 5-6 mil. This is due to the singulation method used in the PCB and component manufacturing as well as from growth / spread in feature location due to the PCB artwork combined with the lithographic process. This type of deviation is more of an assembly issue, if the package edge recognition is used for placement instead of bump find algorithm Warpage Warpage is a thermo-mechanical phenomenon that causes a change in the curvature of the microelectronic component and/or the PCBs. Warpage is a concern in placement, but even more so, it is important for the formation of solder joints during reflow. Of more obvious concern is the substrate warpage during reflow. When combined with the solder bump volume variations across the die, excessive warpage may prevent some bumps from making contact with the substrate pads thereby causing an open. A warped package and/or board at liquidus temperature leads to coplanarity problems during the 27

41 formation of the solder joints. These coplanarity problems could lead to a variation in the shape of the joint and, in severe cases, could lead to defects such as bridging or opens besides causing considerable stress on the solder joints. There are three important aspects of package and board warpage: warpage at room temperature before reflow, warpage at reflow temperature and warpage after reflow temperature. Warpage at room temperature before assembly may be affected by factors such as moisture exposure, handling procedures, stress distribution, physical dimension of die/package, orientation of solder bumps etc. Among the three warpage stages, warpage at reflow temperature has the most profound effect on the solder joint formation and the assembly yields. There could be several reasons that may cause a change in curvature of the package and the board at reflow temperature. These include material properties, CTE (coefficient of thermal expansion), glass transition temperature of respective materials (T g ), presence of moisture and delamination between the layer. The packages also warp at room temperature, after assembly process. Salient factors causing this include negative change in the temperature, relieving of residual stresses and tendency to achieve the most stable state after the assembly. Measuring package and board warpage at reflow temperature can provide a better estimate of its effect on the assembly yields. Techniques such as Shadow Moiré interferometry can be used to measure the out-of-plane displacements of specimens at elevated temperatures. Mathematically, warpage can be defined as a deviation from flatness of the component's substrate. For calculation purpose (in the model), warpage 28

42 is defined as the maximum normal distance between the highest point on the substrate and a straight line joining the two edges of the substrate Planarity In surface mount technology, package coplanarity is defined as the distance between the tallest and the smallest solder bump. To pursue higher soldering yield in surface mount assembly, smaller coplanarity value is desired. Several end users prefer to have the package specification in terms of coplanarity value. Achieving smallest possible coplanarity value without an increase in cost is one of the primary goals for package manufacturers. Non-contact laser scanning or a surface roughness measurement meter can be used to obtain statistics on coplanarity. One of the several effects of bump height variation is the change in planarity. Variations in planarity may contribute to lower yield, joint shape distortion as well as poor reliability of joints BOARD RELATED ISSUES Due to the miniaturization of the area array devices and increase in the package density, additional requirements have been placed on the performance of printed circuit boards. Although boards used in the assembly of area array packages are designed to meet the demands imposed by the complex structure of these devices, variations in pad and solder mask size, substrate thickness and warpage (both local and overall) can influence the assembly yields. Features such as moisture characteristics of the substrate material and registration of solder mask also affect the placement yields and reliability of the assembly. Some of the key features related to PCB in assembly include 29

43 its cleanliness, proper solder mask finish, minimum thickness variation and resistance to warpage at reflow. This section presents a brief discussion on some of the board related parameters that affect the assembly yields of area array devices Shape and Size of Contact Pads: Pad shapes on boards vary from rectangular pads to circular pads with traces. In presence of solder volume variations, different pad shapes may have different sensitivities (with respect to standoff height). For example: diameter of circular contact pad size can be decreased to have an increased standoff height and reduced probability of satellite (presence of excessive solder that might cause bridging of joints) formation, but at the same time, it enhances the chances of an electrical open Deviations in Fiducial & Pad Location: These parameters are part of in-plane variations. Placement machines use fiducial (local or global) on the board as a reference during the component placement procedure. Any deviation in the location of the fiducials may affect the placement accuracy and the subsequent yields. Similarly, the deviations in the locations of pad on the substrate also affect the assembly yields and long term reliability of the assembly. However, these variations are more critical for the fine pitch DCA assembly due to smaller dimensions and reduced tolerances on the pitch, mask opening and the bump sizes. 30

44 Substrate Warpage The warpage effect on the PCB substrate is similar to that of components. The temperature profile during the reflow causes a change in the curvature of the PCBs. Residual thermo-mechanical stresses from the curing process, coupled with the asymmetries of laminate, also cause warpage. PCBs are made of stack of laminates, which in turn is made up of stack of resin impregnated fabric sandwiched between thin layer of copper foils. The thermal mismatch within the laminates and between the laminates causes warpage of the PCBs. The warpage phenomenon is similar to bending of bimetallic strip due to change in temperature. There is a direct relationship between substrate warpage and coplanarity, the coplanarity value decreases with an increase in the substrate thickness [Junicho]. Since solder joints are formed during reflow process, warpage during reflow as opposed to the warpage before and after the reflow process (at room temperature), has a significant effect on the joint formation and consequently on the reliability and assembly yields. Warpage or sagging during the assembly process also depends on the thickness of the board. At reflow temperature, the joint formation depends on the localized warpage (at the package area) rather than the overall warpage. The JEDEC standard specifies overall panel warpage of less than 7.00 mil. In general, the warpage effect is more predominant in the thin boards (<30.00 mil) than the thick boards (>30.00 & < mil). Board supports can be used to prevent warpage in case of assembly on thin boards. 31

45 2.4. ASSEMBLY RELATED ISSUES The yields for surface mount assembly can be affected by defects occurring at three stages. First, prior to assembly based on the integrity of package, board, material, handling etc. Second, during the assembly process based on the process parameters such as placement and interaction of board, package and material related variations. The third stage is after assembly with reliability related defects and issues. This research work is mainly concerned with the interaction of variables and parameters during the stage two, i.e., assembly process Placement Effective placement yields depend on design, substrate tolerances and placement machine accuracy and the vision system. The placement yields also depend on the ability of the machine to recognize features on the board and component, and accurately place the device with close alignment of bumps and pads on the PCB. Two different methods can be used for accurate positioning of the device: 1) using solder ball locations (footprints), and 2) using edge of the package. In case of BGA packages with large pitch (~ 1.00 mm) and solder volume, self-centering phenomenon is quite common and it helps in reducing the placement inaccuracies. Typically, the BGAs have been found to self-center by as much as half the ball diameter Solder Paste Deposit Variations: Variations in the paste volume, combined with other component and board related parameters might, reduce assembly yields. Based on the application, flux-only or solder 32

46 paste deposit can be used in the assembly of surface mount devices. The most common technique used in the industry, for depositing solder paste on board is stencil printing. The solder paste, deposited on the board, helps in mitigating the affect of solder bump height variations, especially in case of eutectic (63/37 Sn/Pb) solder bump by increasing the total solder volume available to form the joint. However, the variation in volume of paste deposit is more critical for packages with high lead bumps (5/95 Sn/Pb) that do not melt during the reflow process, and the joint formation is dependent on the volume of paste deposited on the pads (on board). Solder paste deposit volume variation can be monitored by controlling printing parameters such as print speed, paste material and print pressure ASSEMBLY DEFECTS Although the assembly yield is based on activities during the reflow process, in many cases, the defects from a reflow process are caused by or are initiated in prior process steps. These are the defects related to materials, paste application, PCB design etc. Some of the common defect types included in this research are discussed below Bridging: Bridging is a formation of an undesirable connection between two conductors. Excessive solder volume, package weight and component misplacement are causes for potential bridging. The excessive solder separates from the main solder joint body and becomes a satellite around the solder joint (solder balling). Since these satellites lie on 33

47 non-wetted surface and are not bonded, there is a high chance that they will merge into other joints or create bridges between joints Open: The term refers to a phenomenon when no joint is formed between the component and its corresponding pad on board. In general, the open joint condition can be attributed to causes such as insufficient solder volume, poor lead coplanarity, excessive component and/or board warpage, lack of wetting and solder robbing due to paste slump etc. Solder volume variation and the coplanarity issues can be handled by depositing solder paste on the board pad REVIEW OF YIELD MODELS The statistical design methods for maximizing the electronic packaging yield has been an active area of research for more than two decade. Since high yield means more profit, IC manufactures are willing to use computer aids and models to develop new process parameters and optimize the old ones. Also, many practical yield maximization solutions, specific to the integrated circuits, and the computers powerful enough to use these methods/models have appeared recently. Due to the economics of the electronic industry, maximization of yield rather than mere optimization of performance has become factor of prime importance. In this section, two different models representing different products and aspects of electronic packaging industry, are discussed. These model pertain to mixed technology assembly and surface mount assembly. For the sake 34

48 of brevity, only a brief review is presented here. More details can be found in the referenced literature Yield model for Mixed Technology assembly process [7]. This is a mathematical model developed to predict the assembly yield of mixed technology circuits having both surface mount and through-hole devices, and is based on components and lead counts. The model has been developed using data from three assembly lines of AT&T Denver and claims to predict the results within a margin of RMS error of 5 %. It is based on the concept of calculating the probability of a defect free assembly from the probability of success of each process steps. The main assumptions include knowledge regarding the probability of occurrences of process events and the statistical independence of the processes. Yield has been defined as the percentage of boards built without any assembly defects or bad components. The number and type of components on the board are included in yield calculation. All defects, wherever they occur, are counted, including defects found at the in-circuit or functional test. Results presented in the paper consists of a compilation of data for over a one year period, based on the assemblies done on the surface mount equipment from Fuji and Senju and the through-hole machines from Universal and Electrovert. The assembly lines were used by AT&T for the PBX products. Salient factors considered for yield calculation include component type and count, component layout and circuit board land geometry. Commonly used component types include SOICs, SOTs, Chip Capacitors and reistors, PLCCs, DIPs (Axial and Radial) 35

49 and Non-standard devices. Varieties of lead include SOIC Gull Wings, PLCC J shaped leads, and axial/radial leads. The paper defines two versions of the model, the second version, being an improvement over the first one. The simple model (first version) considers the total number of solder joints, n, as the only design parameter. The Yield expression is shown below: Yield = A+ Bn Eq The second version of the model is more comprehensive and can be summarized by the expression given below: Yield = A + Bg + Cc + Dc + Dd + E p + Fl + Gd t b j t Eq where: A, B, C, D, E, F and G are coefficients (not disclosed due to proprietary reasons) g = # of gull wing leads c t = # of top side chip leads c b = # of bottom side chip leads d j = # of J leaded devices p t = # top side lead density l = # of leads of other types d = # of devices of other types ANOVA method has been used to identify parameters having correlations or parameters having no significant statistical influence on the yield. Parameters with lesser significance are lumped together into one conglomerate value. The coefficients of the model have not been disclosed due to proprietary reasons. Both the simple and 36

50 reduced version of the model claim to predict yields based on the average RMS for the 6 set of test points with an average predictive error of about 4 %. The model seems to be quite comprehensive as it represents the through-hole and surface mount process. The results of the case studies presented in the paper suggest that the predictions have been quite accurate. One of the important features of this model is that, it can represent different assembly lines using similar equipment, although the significant parameter and the value of the coefficient may change with time as the process matures. As per the author s claim, this model is currently being used by AT&T to define the minimum acceptable manufacturability standards for its new designs Yield Estimation for Surface Mount Area Array Devices - Using Monte Carlo Simulation Technique [13]. For surface mount area array devices, assembly yield is dependent on the defects that occur during placement and assembly process. Assembly yield can be defined as ratio of good joints (or component) to the total number of assembled joints (or component). The above mentioned model is a simulation of placement and the assembly process. It uses Monte Carlo technique to calculate the overall assembly yield. Monte Carlo technique is a method that involves statistical simulation of an underlying system, where the system represents a real physical process. The primary components of a Monte Carlo simulation method includes probability distribution functions (pdf's) for 37

51 defining system, random number generator as a source of random numbers uniformly distributed between 0 & 1 and sampling techniques for sampling the specified pdf's. The yield calculation procedure consists of generating "pseudo'' random numbers based on the characteristics of input variables (ex: normally distributed) and using these numbers to simulate random (placement & assembly) processes. Mathematical expression [13] and randomly generated numbers are used to determine the bump heights and the distance of separation between the package substrate and the pad on board. Pre-defined defect criterions are then used to determine the number of defective joints and components. For a random variable with known distributions, its probability can be easily estimated using the probability density function or cumulative probability function. The input variables addressed in this model include board, package and assembly related parameters. Output of model (assembly section) is in terms of the number of joints with satellites, number of opens, number of defective components, and the component and joint defect level estimated at 95% confidence interval. The issues addressed by the model can be divided into two categories, in-plane variations and out-of-plane or Z-axis variations. The in-plane variations are mainly concerning Event A (explained below) and include issues such as the bump to pad alignment, self centering ability, variations in the pad size, mask mis-registration etc. The out-of-plane variations or the Z-axis variations represent the issues related to Event B (explained below) and has parameters such as the solder volume and bump height variations, package and board warpage, solder paste deposit variation etc. Several 38

52 mathematical expressions [13] are used for determining the number of defective joints and components. The Monte Carlo Simulation approach is based on the following assumptions. Random number generator generates numbers that are uniformly distributed between 0 and 1 and generated values can be assumed to be serially independent. Input variables must follow normal distribution. User can determine the number of iterations in the simulation. The confidence interval used in the hypothesis testing is 95 percent. The final yield is calculated in two steps, 1) Event A: Joint with a substantial overlap area between the component pad and the board pad, and 2) Event B: A joint is neither open nor with satellite solder balls around the joint. These two events are defined to ensure that device self-centering occurs during reflow (Event A) and proper interconnections are formed (Event B). Mathematically, the yield can be defined by the expression given below: YIELD = P(B A) = P(B/A). P(A) Eq The model has been transformed into a computer code. Using an input distribution obtained from a large data set accurately represents the characteristics of the population from which it is sampled. The use of large number of iterations provides a better estimate of the characteristics of the population of possible results. As far as simulation modeling is concerned, the assembly of a package with high lead bumps is different from that of packages with eutectic bumps. There are additional assumptions 39

53 and expressions for calculating the yield of assemblies with high lead bumps. The model provides an algorithm for such a scenario, although it is not incorporated in the software program. Also, due to programming constraints, the yield calculation is limited to 30,000 iterations. The run time of the program is dependent to a large extent on the number of solder bumps on a package. Run time in several cases can take hours. The results obtained from the software have been found to be reasonably accurate CONCLUSION: IC packaging technology strives to further industry goals of reducing the amount of space consumed by electrical components while increasing system performance. In general, the assembly process, for area array device, is robust with a tolerable parameter window, although they are application specific. However, many defects can be attributed to the integrity of materials such as packages, boards, solder paste etc. The assembly related parameters such as the reflow atmosphere, placement procedures, vision system etc also contribute to reduce yields. Wide ranges of issues were discussed in this chapter. Some of the issues are qualitative in nature and require further analysis, while numerous other factors can be improved with proper training, education and awareness. Review of the yield models for mixed technology process and the Monte Carlo Area array model gives an idea of the concepts and methods used in modeling. Key features of these models can be used to simulate/model similar processes. 40

54 Parameters representing the variability in the device manufacturing (such as ball coplanarity and volume variations, warpage, contact pad diameter variations), board design and manufacturing (such as pad size, taper, thickness) and solder paste volume related variations have been included in the mathematical model. The concepts, mathematical equations and yield calculation procedure of the proposed approach are discussed in Chapter 3. 41

55 CHAPTER THREE: 3.1. INTRODUCTION In surface mount technology, assembly yield can be defined as a ratio of the number of assemblies that meet specifications to the total number of assemblies produced. However, in the presence of variability, a better definition of yield will be the expected number of acceptable assemblies produced. Hence, this definition of yield is used to determine the accuracy of the underlying assembly process. The yield of direct chip attach/chip scale package (DCA/CSP) assembly is affected by placement related defects such as imperfect wettability/solderability. Assembly related opens, or bridging defects occur due to out-of-plane variations (such as bump volumes, board warpage etc.), effect of variations in pad sizes, solder mask windows and bump damage, among others. Similar to other development tools such as finite element model, cost model, reliability model etc, "Area Array Assembly Yield Model" is a tool that can be used to predict yield of an assembly process based on a set of input variables and pre-defined defect criterions. Two "Yield Models" representing different aspect of electronic manufacturing industry was discussed in the previous chapter. The yield model described in this research consists of three main modules, 1) generating the bump heights, 2) generating the distances of separation between the package substrate and board substrate, and 3) comparison of the bump height with the distances of separation. Since, in real life, most of the input parameters are found to be non-normal or close to normal, one of the important aspects of this model is its ability to consider any distribution type including 42

56 standard, empirical or experimental. This chapter presents the concepts of the mathematical model, methods for the determination of its key components (probability of a joint or component being acceptable or unacceptable), the formulas for predicting the yield in terms of parts or joints per million and a discussion on the methodology used for the yield determination. Implementation of the model on several problem scenarios and brief discussion on the various parameters incorporated in the model is also given. To implement the mathematical model, user-friendly software has been developed [16]. The software predicts the expected number of defective joints and components at the level of one million joints/components. The predictions are based on user-specified information on the input variables MODEL CONCEPT "Area Array Assembly Yield Model" is a tool to determine assembly yields based on the characteristics of input variables. It is a mathematical model designed to express the variability of the package, board and assembly related parameters. The methodology, used for the prediction of yield, assumes discrete points on input distributions along with their probabilities (of occurrence) and evaluates all possible combinations of bump height and distance of separation between the package and board substrate. For a given location, if the bump cannot reach the pad on substrate (bump height being less than distance of separation), the probability of this joint being defective is the product of probability of occurrence of that bump height and the probability of occurrence of that distance of separation. The probability of occurrence of a bump height, in turn, is based on the probability density functions of the pad diameter and solder volume responsible for generating the particular bump height. Similarly, the probability of a particular 43

57 distance of separation can be determined using the probability density function of the component warpage and the board warpage. If a single point input distribution is considered, then the probability of the only occurrence is one. The yield model can be divided into three main parts. Part one consists of generating the bump height density function from the density functions of pad diameter on package and solder volume variations, or using a bump height density function as direct input. Part two consists of generating the distances of separation and their probabilities, based on no warpage (flat substrate) or component and/or board warpage at reflow temperature in the X and Y directions. The warpage shape in the X and Y directions are assumed to be independent and can be convex or concave. Part three compares the individual bump height with individual distance of separation at each bump location. The yield values can be predicted based on a user defined defect level (less than or greater than a specified parts/million criterion) or parts per million level. The yield values can be given in terms of joints per million or parts per million. The model can incorporate normal, empirical, experimental density function or a combination of all density function types. There are certain requirements, advantages and disadvantage for using empirical and experimental density function. Since most of the input parameters are found to be non-normal or close to normal, an assumption of normality incorporates a degree of error in the yield estimates. The use of empirical density functions does capture reality into the model. However, it is very important to determine the sample size of the data to base the empirical density function on. Since 44

58 the calculations are based on the observed maximum and minimum value, extrapolation at the tail of the density function is not possible and the results may be an underestimate. Some of the discrepancy can be reduced in case of empirical density function through extrapolation on the tails of the density function by considering appropriate sigma limits ASSUMPTIONS 1. All the joints are independent of each other, i.e., a particular joint being defective does not affect the nature of a joint next to it. 2. A component is defective if it contains one or more defective joints 3. Warpage is symmetric about the center of component 4. In case of warpage, the assembly can be thought of as consisting of one component on one board, with N number of such components and boards. 5. Bumps on package are assumed to be in perfect alignment with the pad on board 3.4. VARIABLES CONSIDERED IN THE MATHEMATICAL MODEL In the previous chapter, various issues and factors that affect the assembly yields were discussed. These issues can be classified into four broad categories, as mentioned below. 1. Issues related to integrity of devices and boards used in assembly process. These include wire bond failure, missing bumps, flux residue, moisture 45

59 sensitivity, improper dicing/finish of chips, solder-mask finish, and presence of residues/debris around the pad on board among others. 2. Issues related to component, boards and the assembly process that can best be described as qualitative in nature. These include solderability/wettability of joints, reflow atmosphere, reflow profile, delamination, pad metallurgy, flux activity, and vision system in placement machine among others. 3. Issues concerning the training, education, setup & quality control and handling procedures of devices, boards and assemblies within the assembly sequence or storage area 4. Issues related to variability in the package and board parameters, introduced during the individual manufacturing processes that may interact during assembly process thereby forming defects or unreliable joints. Example of such variables include bump coplanarity, solder volume, pad size, component and board warpage, pad size on board, substrate thickness, solder paste deposit volume, placement accuracy, fiducial and pad location, and bump location on device among others. The parameters and issues mentioned in the first three categories are qualitative in nature and are beyond the scope of this mathematical model. However, other factors that are characterized by a statistical density function can be expressed in terms of mathematical expressions. In theory, almost all parameters, that can be defined by a statistical density functions, can be incorporated into a model. However, the extent of detail added in the model should be compromised with the amount of calculations 46

60 involved, computation time, preparation of computer codes and the overall efficiency of the model. Within the scope of this research work, important parameters were identified and incorporated into the model so as to simulate the assembly process and predict the assembly yield. Next we briefly discuss various component, board and process related parameters used in the model Bump Coplanarity The coplanarity value is used as one of the specifications for electronic devices. Planarity is a critical issue for area array devices having high lead (5/95 Sn/Pb) bumps that do not melt during the solder reflow process. To pursue higher soldering yield, a smaller coplanarity value is certainly better. The variation can be characterized by statistical distribution of the bump heights Solder Volume Variations In case of area array devices having eutectic (63/37 Sn/Pb) solder bumps, variations in total solder volume rather than the individual bump volume is an important factor that affects the process yield. In case of assemblies using flux, total solder volume (for a given location) is equal to the volume of solder bump, whereas, in case of assemblies with solder paste deposit on board, the total volume variation is a combination of variations in solder bump volume and the paste deposit volume. Since, at reflow temperature, all the solder material is in a liquidus phase, it is the total volume variation at a given location and the substrate curvature (due to board/component warpage) that affects the joint shape, size and status (defect or no-defect). The volume variation can 47

61 be calculated using a geometrical expression and assuming the solder bump to be truncated sphere. There are two important elements of volume calculation, namely solder bump diameter and contact pad size on package Solder bump diameter variations In a package, solder bump constitutes the majority of solder material in a joint (for flux only assembly) and, therefore, its variability is an important factor for the calculation of volume variations. Typically, the statistics on the ball diameter can be obtained using measurement machines (ex: View Engineering - Voyager Automated Visual Inspection System). However, factors such as flat or damaged bump may give erroneous statistics on bump diameters. For example, diameter measurement of the flat solder bump shown in Figure , may be larger than nominal (due to flatness) but the solder volume may be on the lower side as a result of reduced bump height. The bump diameter variation can be specified in the yield model in terms of a standard (ex: normal), experimental or empirical distribution Contact pad size variations Characterization of the contact pad size variations is an important task for determining the solder bump height variations on the package. Only circular pad sizes have been considered in the model, although other shapes can be incorporated in future. The variations can be indicated using a standard, experimental or empirical distribution. 48

62 Solder mask Substrate on component Solder Bump (truncated sphere shape) Flattened portion of solder bump Figure : Digital image of Damaged / Flat Solder Bumps [4] 49

63 Component Warpage As mentioned in the previous chapter, there are three different aspects of component warpage i.e., warpage before reflow, during reflow and after reflow. Since the joint formation occurs during the reflow process, the package curvature at reflow temperature affects the joint formation. There are several reasons that can cause a change in curvature of the packages at reflow temperature including, material properties, coefficient of thermal expansion (CTE), presence of moisture, delamination between surfaces etc. This change in curvature can be concave, convex, saddle or an irregular shape. Examples of package curvature (at room temperature) are shown in Figure (donut shape - large BGA) and Figure (saddle shape CSP with a flexible substrate). In order to calculate the distance of separation between the package and the board substrate, the warpage shape needs to be defined in the X and Y directions. For determining the assembly yields using the proposed mathematical model, the change in curvature of package substrate has been restricted to regular convex or concave shape about the center of package. Warpage shape in the X and Y directions on device can be the same (i.e., both convex or both concave) or different (one concave the other convex and vice versa). The warpage can be specified as zero (i.e., flat with no warpage), as an average value, or as following, a standard (ex: normal) or an empirical density function. 50

64 Figure :Warped Surface of a Large Ball Grid Array Package Figure : Warped Surface (saddle shape) of a flex device 51

65 Board Pad Size Variations The pad size variation, when combined with other parameters such as board warpage, package warpage and solder volume variations, can cause reduced assembly yields. In general, variations in the pad size within the board can be considered as zero. For calculation in the model, average value of pad size is used. For NSMD (non-solder mask defined) configuration on board, two additional variables such as pad thickness and pad taper are included in the yield determination. Also, the model considers only mean values for pad thickness and pad taper Board Warpage Similar to package warpage, the board warpage during reflow process is used for assembly yield prediction. The board warpage primarily changes the coplanarity effect and is more predominant in the thin boards (thickness < 30 mil). A combination of board and component warpage in opposite directions can be detrimental for the assembly yield and reliability. The model uses localized (package area) warpage effects rather than the overall board warpage. The change in curvature is restricted to regular convex or concave about the center of the package area on board. Warpage shape in the X and Y directions can be the same (both convex or both concave) or different (one concave the other convex & vice versa). As in the case of component warpage, board warpage can be specified as zero (i.e., flat), by an average value or as following: standard (ex: normal) or an empirical density function. 52

66 Solder Paste Deposit Solder paste deposits on board can be used to mitigate the effect of coplanarity variations on assembly yields. In case of area array devices having high lead solder bumps, the interaction of bump height variations, warpage and variation in the volume of the solder paste printed on the board can pretty much define the yield. The paste volume variation is an important parameter even for devices with eutectic solder bump. It has therefore been included in the model. Details on paste deposit parameter can be specified in terms of an average value or as a statistical density function MATHEMATICAL EXPRESSIONS/FORMULAE The yield model can be thought of as a virtual assembly system, where interaction among the critical parameters are represented mathematically and the assembly yield is determined based on the criteria to determine a defective joint. The mathematical expressions/formulae used in the model can be grouped into two sections. One, representing the assembly process, including, the generation of bump height, joint height, distance of separation between the package and board substrate and the warpage function. Section two, consists of concepts and expressions to determine the probability of defective joints and the yield values in terms of the number of defective joint/components. Listed below are some of the most common expressions used in the model for the determination of assembly parameters and yields. 53

67 3.5.1 Solder Joint Height or Distance of Separation The solder joint height (standoff) depends on several factors such as pad size on board, pad taper, pad thickness, solder volume on package, volume of paste deposit on board (for assembly with paste), bump coplanarity (for high lead bumps) etc. In general, based on the average solder volume conditions and the pad conditions on the board, joint height can be calculated by assuming the sphere to have double truncation, at the top and bottom, of size equal to pad size on package and board. In order to determine the standoff height of each solder joint, a reference such as separation between two pad surfaces at one particular location needs to be established. Assuming h 0, to be the separation between the pad surfaces at the center of a package (irrespective of the presence of a joint), the separation, h i, at location i on the package can be determined from the expression given below. h + ( ) i = h 0 f W i Eq where f(w i ) is the warpage function explained in the next section. For calculation purpose, each solder joint under reflow conditions is assumed to be in the form of a linear spring with spring constant k i, and neutral height H i, both of which is dependent on the solder volume and contact pad sizes. Assuming substantial number of joints, the balance of upward and downward forces can be used to determine package-board separation at the individual joint [13] i.e., F total N = Fi = k i= 1 N i= 1 i ( h H ) = 0 i i Eq

68 Based on the statistical distributions, individual solder joint volumes and contact pad dimensions are different. However, to determine the common neutral height H 0, all the individual solder volumes and the pad sizes are replaced by mean of the individual statistical distributions (i.e., all joints are assumed to be identical). Assuming a common spring constant, k, the total displacement of joint height with respect to H 0 is zero and is given by: N i= 1 h i = NH 0 Eq Using the expression from Eq , the distance of separation between the two pad surfaces at the center of a package (h 0 ) can be solved as: N i= 1 h i = N i= 1 h 0 + N i= 1 f ( W ) i Eq Substituting the expression shown in Eq : NH 0 = Nh 0 + N i= 1 f ( ) W i Eq h 0 = H 0 1 N N i= 1 f ( ) W i The common neutral height H 0 (or equilibrium height) corresponding to the volume TV is given by: ( 3R + R H ) 1 TV = πh Eq

69 The final expression [13] for the common neutral joint height (or equilibrium height), H 0, is a solution of polynomial equation (Eq ) and can be given as: 3TV 9TV 3TV 9TV H + π π π π = + + ( R R2 ) + + ( R 2 1 R2 ) Eq where TV: sum of mean solder bump volume and half of the mean of the solder paste volume R 1 : mean component pad radius R 2 : mean board pad radius As discussed in this section, the distance of separation, h i, at each location i, on a package can be determined using Eq The individual bump heights can be compared against these h i values, to determine the yield. In the model, this comparison is done under two scenarios: a) when both component and board is flat (i.e., no warpage), and b) when there is component and/or board warpage. If f(w i ) = 0, Eq , can be written as: h 0 = H 0 hi = H 0 (from Eq ) i.e., the distance of separation at the center of the package (h 0 ) is equal to the common neutral height or equilibrium height (H 0 ). Therefore, individual joint height, h i, irrespective of it location, is equal to the distance of separation h 0 or equilibrium height H 0. A solder joint can be formed, if the individual bump height h h i. A graphical 56

70 representation of these heights (h, h 0, h i and H 0 ) for an assembly with flat board and flat component are shown in Figure In the case of second scenario, i.e., assembly with board and/or component warpage, the distance of separation is different at each location (i.e., h i h 0 H 0 ). In case of warpage with center higher than the corners, the center will move upward while the corners downwards. Assuming a spherical component shape this is not uniform and the effect on the outside bump is larger. Hence a new reference, h 0 (h 0 H 0 ), is determined from the expression shown in Eq In the present case of package center higher than the corners, h 0 will have a value less than the neutral height H 0 (since, f(w i )>0). The distance of separation at individual joint location can then be determined by using the expression shown in Eq A graphical representation of these heights (h, h 0, h i and H 0 ) for an assembly with flat board and positive component warpage (center higher than corner) is shown in Figure Warpage Function: Warpage is a thermo-mechanical phenomenon that causes a change in the curvature of both the package and board substrate. For assembly yield calculation, warpage has been defined as the maximum normal distance between the highest point on the substrate and a straight line joining the two edges of the substrate. In practice, the change in curvature shifts the bump coplanarity by making it better or worse based on other interacting variables. Mathematically, warpage function, f(w i ) can be defined as a 57

71 Height at center of package: h 0 COMPONENT SUBSTRATE f ( W i ) = 0 Joint height: h i = H 0 = h o h 0 H 0 Bump height a location i = h SOLDER JOINT PAD ON BOARD SOLDER BUMP BOARD SUBSTRATE f ( W i ) = 0 Note: Drawing not to scale Figure : Representation of the distance of separation at the center of package (h 0 ), equilibrium height (H 0 ), joint height (h i ) and bump height (h) for an assembly of a flat component on a flat board. 58

72 COMPONENT SUBSTRATE f ( W i ) = + h I h i=1 H 0 h 0 h SOLDER JOINT PAD ON BOARD SOLDER BUMP BOARD SUBSTRATE ( W i ) = 0 Note: Drawing not to scale, the representation may change for different warpage shapes and magnitudes f Figure : Representation of the equilibrium height (H 0 ), joint height or distance of separation (h i ), bump height (h) and separation at the center of package (h 0 ), for an assembly of a component with positive (center higher than corner) warpage on a flat board. 59

73 function of bump location in X & Y directions, package warpage and board warpage (in terms of the radius of curvature), i.e., f ( Wi ) = f ( X i, Yi, RCX, RCY, RBX, RBY ) Eq where R cx = Component warpage in terms of radius of curvature in the X direction R cy =Component warpage in terms of radius of curvature in the Y direction R bx = Board warpage in terms of radius of curvature in the X direction R by = Board warpage in terms of radius of curvature in the Y direction X i = The coordinate of joint i in X direction Y i = The coordinate of joint i in Y direction A schematic of warpage function is shown in Figure The warpage function can be approximated as: f ( Wi ) = f ( X i, Yi, RCX, RCY, RBX, RBY ) = ± R CX 2 2 ( ) 2 2 R X ± R ( R Y ) CX i CY CY i ± R BX 2 2 ( ) 2 2 R X ± R ( R Y ) BX i BY BY i Eq If the center of curve is higher than the corners, warpage is assumed to be convex (positive), whereas, if the center is lower than the corners, warpage is assumed to be concave (negative). 60

74 Board or Package Substrate d X i R CX α R CX d = 2 2 R ( ) CX RCX X i Figure : Graphical representation of warpage calculation 61

75 3.5.3 Solder Bump Height Typically, solder ball attachment process consists of placing a pre-formed spherical ball onto the pad on substrate and is followed by a reflow. During the reflow process, the solder material melts and the interconnection between the pads and solder balls (bumps) are formed. Depending on the attachment process, there might be distortion in the spherical shape. However, in general, it is quite safe to assume the solder bump shape to be a truncated sphere. The individual bump height can be calculated from the solder bump volume and component pad radius using the expression [13] shown in Eq , and by substituting R 2 = 0, TV = V, and H 0 = h, the new expression for bump volume is: 2 2 ( 3R h ) 1 V = πh Eq The expression to determine the bump height is obtained from the solution of a polynomial equation (Eq ) and is given by, 2 3V 9V V 9V h = + + ( R 2 1 ) + + π π π π ( R 2 1 ) Eq where h = solder bump height V = solder bump volume R 1 = component pad radius. 62

76 The solder bump height (on the package) can also be determined by using the statistics on solder ball diameter variations and contact pad size variations. The solder bump is assumed to have truncated sphere shape, (Figure 2.2.3) where h D = D 2 ( R ) 2 1 Eq D = Solder bump diameter R 1 = Component pad radius NOTATION The following notation is used in the development of a methodology for assembly yield determination: C: Random variable corresponding to the component pad diameter V: Random variable corresponding to the solder volume B: Random variable corresponding to the board pad diameter h: Solder bump height h i : P C (C = c): Distance of separation at location i Probability of occurrence of a particular component pad diameter, for a value of C = c P V (V = v): P B (B = b): Probability of occurrence of a particular volume, for a value of V = v Probability of occurrence of a particular Board pad diameter, for a value of B = b P W (W = w): Probability of occurrence of a particular warpage, for a value of W = w 63

77 P W (W = w c ): Probability of occurrence of a particular component warpage, for a value of W = w c P WX (W=w cx ): Probability of occurrence of a particular component warpage in X direction, for a value of W = w cx P WY (W=w cy ): Probability of occurrence of a particular component warpage in Y direction, for a value of W = w cy P W (W=w b ): Probability of occurrence of a particular board warpage, for a value of W = w b P WX (W=w bx ): Probability of occurrence of a particular board warpage in X direction, for a value of W = w bx P WY (W=w by ): Probability of occurrence of a particular board warpage in Y direction, for a value of W = w by P 0 : Probability of an acceptable joint, considering the case of average board pad diameter P s 0: Probability of an acceptable joint, considering satellite in addition to open as a defect Q 0 : Probability of an unacceptable joint, considering average board pad diameter Q s 0: Probability of an unacceptable joint, considering satellite in addition to open as a defect P 1 : P s 1: Probability of an acceptable joint, considering varying board pad diameter Probability of an acceptable joint, considering satellite in addition to open as a defect 64

78 Q 1 : Probability of an unacceptable joint, considering varying board pad diameter Q s 1 Probability of an unacceptable joint, considering satellite in addition to P L 2: Q L 2: PC: open as a defect Probability of an acceptable joint at location L, considering warpage in addition to varying component pad diameter, board pad diameter and solder volume. Probability of an unacceptable joint at location L, considering warpage in addition to varying component pad diameter, board pad diameter and solder volume. Probability of an acceptable Component. N: No of joints/component M: No of components N Total: C: Total no of joints = N. M Increment in the component pad diameter to get discrete data points from a given distribution V: B: Increment in the solder volume to get discrete points from the distribution. Increment in the Board pad diameter obtained from a given distribution 3.7. DETERMINATION OF DESIRED PROBABILITIES One of the important aspects of this approach for yield prediction is the accurate determination of the probability of occurrence of a particular event (ex: component pad diameter = c with respect to its density function. Given below are functions used for the determination of desired probabilities under different scenarios. 65

79 3.7.1 Probability of a defective joint, considering Average Board Pad Diameter (no warpage): Q 0 : = P (unacceptable joint, for a average board pad diameter) = C,V P (unacceptable joint C, V). P(C, V) Eq Where P(Unacceptable joint C,V) = 0 or 1 and is determined experimentally using a pre determined criterion for defects. Note that the outcome (unacceptable joint C, V) follows a degenerate probability density function. Based on the assumption made on the independence of C and V: P(C, V) = P C (C). P V (V) Eq Therefore, P 0 : P(an acceptable joint) = 1- Q 0 Eq Similarly, if Q s 0 is the probability of an unacceptable joint in the presence of satellite or bridging, then P s 0 = 1- Q s 0 Eq Probability of a defective joint considering Variations in the Board Pad Diameter (no warpage): Q 1 : = P(unacceptable joint, varying board pad diameter) = = C, V, B P(unacceptable joint C,V,B). P(C, V, B) Eq where P(Unacceptable joint C, V, B) = 0 or 1 and is determined experimentally using a given criterion as explained above. And, once again, due to the independence of C, V and B, we have: P(C, V, B) = P C ( C ). P V (V). P B (B) Eq

80 Hence, P 1 : P(an acceptable joint) = 1- Q 1 Eq Also, P s 1: P(an acceptable joint, with satellite) = 1- Q s 1 Eq Probability of a defective joint, considering Board Pad Diameter Variations & Warpage: Q L 2: Q Ls 2: P(Unacceptable joint at location L, considering only opens), P(Unacceptable joint at location L, considering satellite in addition to opens) The probability of a joint being acceptable or unacceptable depends on the location of that particular joint. Consequently Q L 2 = C, V, W, B P(Unacceptable Joint at location L C,V,B,W). P(C, V, B, W) Eq where P(Unacceptable Joint at location L C,V,B,W) = 0 or 1, and is determined by the criteria based on the equilibrium height which is affected by the warpage and varies at different locations. Once again, due to the independence of C, V, B and W : P(C, V, B, W) = P C (C). P V (V). P B (B). P W (W) Eq Therefore, P L 2 = P(an acceptable joint) = 1- Q L 2 Also, P Ls 2 = P(an acceptable joint) = 1- Q Ls 2 Eq Eq Determination of Probability of a component being acceptable PC 0 : Probability of an acceptable component, considering average board pad diameter 67

81 N = P 0 or = (P S 0) N in the presence of satellite Eq Similarly, PC 1 = Probability of an acceptable component considering varying board pad diameter N = P 1 or = (P s 1) N in the presence of satellite Eq where N= No of joints /component N P 0 is the probability of an acceptable component considering average board pad N diameter and P 1 is the probability of an acceptable component considering varying board pad diameter 3.8 YIELD DETERMINATION Yield has been defined as the expected number of acceptable joints or components. Once the probability of accepting a joint is calculated, the expressions given below can be used to determine the assembly yield. Expressions for both the expected values and variability around the expected values are listed below Yield in terms of Joints (No warpage) Expected number of acceptable joints = N total. P 0 or N total. P s 0 Eq

82 where P 0, is the probability of an acceptable joint, considering average board pad diameter (P s 0 is its counterpart in the presence of satellite) or = N total. P 1 or N total. P s 1 Eq where P 1 is the probability of an acceptable joint, considering the variability of component pad diameter, board pad diameter and solder volume. (P s 1 is its counterpart in the presence of satellite) Standard deviation: = (N total. P 0. Q 0 ) 1/2 or (N total. P 1. Q 1 ) 1/2 Eq Yield in terms of Components (No warpage) Expected no of acceptable Components = M. PC 0 or M. PC 1 Eq Standard deviation = (M. PC 0. QC 0 ) 1/2 or (M. PC 1. QC 1 ) 1/2 Eq Yield in terms of Joints (With Board and/or Component Warpage) Expected number of acceptable joints = P P P N P N 2 Eq Standard deviation of acceptable joints = (P 1 2. Q P 2 2. Q P N-1 2. Q N P N 2. Q N 2) 1/2 Eq where N= No of joints per component 69

83 P 1 2, P 2 2, P 3 2 etc., are the probability of a joint being acceptable at location 1, 2, 3 etc. Q 1 2, Q 2 2, Q 3 2 etc., are the probability of a defective joint at location 1, 2, 3 etc., in presence of board and/or component warpage Yield in terms of Components (With Board and/or Component Warpage) Probability (of a component being acceptable) = P 1 2. P P N-1 2. P N 2 Eq where N= No of joints per component P 1 2, P 2 2, P 3 2 etc., are the probability of a joint being acceptable at location 1, 2, 3 etc., in presence of board and/or component warpage. Expected no of acceptable component = M. P(of a component being acceptable) Eq PC = P(of a component being acceptable) can be obtained from Eq Standard Deviation of acceptable component = (M. PC. QC) 1/2 Eq where: PC is the probability of an acceptable component QC is the probability of a defective component, and M is the total number of components. 70

84 3.9. METHODOLOGY USED FOR YIELD DETERMINATION As mentioned earlier (in Section 3.2), the computation of yield is accomplished in three modules, namely: 1) generation of bump heights, 2) generation of distances of separations and 3) comparison of bump heights to distances of separation. These modules are described next. For discussion purposes, a total of 200 discrete data points, each are considered for density functions pertaining to: a) solder bump volume, b) component pad size, c) solder paste deposit, d) component warpage in X & Y directions and, e) board warpage in X & Y directions. The justification for using a small number of data points to obtain the desired estimate of yield is given in Section Module One: generating bump heights The solder bump heights are determined (or generated) from the component pad diameter and solder bump volume density functions. Two hundred discrete data points are considered for each of these distributions and their corresponding probability values are determined. These probabilities represent the chance of occurrence of the individual discrete data point based on the distribution function having a specified mean and a standard deviation. All possible combinations of pad diameter and bump volume are considered to generate the bump heights, (40,000 to be specific) and the probability of individual bump height (being the product of the corresponding probabilities of component pad diameter and bump volume). In order to reduce the computation time and improve the efficiency of the yield model program, these bump heights (40,000) are then converted to 200 bump heights with adjusted probabilities such that it represents the effect of 40,000 bump heights. The bump height distribution generated at this point, 71

85 is an empirical distribution. A new bin size is determined for the bump height distribution by dividing the range of the bump height (maximum minimum) into 200 discrete points, all of the previously generated 40,000 bump heights and their probabilities are placed in the respective bins. The value of the bin represents the new bump height and the sum of all the probabilities (corresponding to all the bump height in this bin) represents the probability of occurrence of this height. Therefore, a set of 200 bump heights and their corresponding probabilities are obtained. These bump heights are then compared to the distance of separation (described in Module two) to determine the yield. An extra step is required for assemblies with solder paste deposit on board. The solder paste volume deposited on the board is combined with the board pad diameter to determine an effective bump size on board. The end effect of paste deposit is the presence of large solder volume (ultimately to compensate for bump height variation). Therefore, the effect of paste deposit is combined with the bump height distributions, as increased bump height on package. 200 discrete points are considered on the paste volume distribution to determine the board bump height and its corresponding probabilities. These heights are then combined to the 200 discrete points generated from the bump height distribution to determine the effective bump height on the package. All possible combinations are considered, thereby generating 40,000 effective bump heights. These heights are then converted to 200 heights and probabilities following the procedure described above. The probability of this effective height is the 72

86 product of the probability of the bump height and the probability of the paste height. A schematic of the procedure, used in Module One, is shown in Figure Module Two: distance of separation at each bump location Since warpage is assumed to be symmetric about the center of package, the distance of separation is calculated only for one quarter of the package. In case of flat boards and components (no package or board warpage), the distance of separation is the same at all locations on the board, and is calculated from the average conditions of solder volume and pad sizes. For assemblies with board and/or component warpage in both X and Y directions, the radius of curvature over the package area is calculated. For every bump location on the package, 200 discrete points are considered on each of the component or board warpage density functions in the X & Y directions, thereby generating 40,000 distances of separations and there probabilities. The probability of a particular distance of separation is the product of individual probabilities of warpage in X & Y directions, responsible to generate this distance of separation. These distances of separations and there probabilities are then converted to 200 discrete points similar to the procedure followed for converting 40,000 generated bump heights into 200 bump heights. In the presence of only component or only board warpage, the above mentioned 200 distances of separations can be used for comparisons with the bump heights. This procedure is applicable to both the component and the board, and is repeated to determine the 200 distances of separation at other solder bump locations. 73

87 Density function for Component pad size 200 Discrete values of pad sizes Density function for Solder bump volume 200 Discrete values of bump volume 40,000 Bump Heights & it's Probability pdf of Bump height (as Direct Input) 40,000 Bump heights converted to 200 Bump heights 200 Discrete values of Bump heights 200 Bump heights & it's probabilities pdf of paste deposit on board 200 Discrete values of paste volume 40,000 Bump heights & it's probabilities 40,000 Bump heights converted to 200 Bump heights 200 Bump heights & its probabilities FIGURE 3.9.1: Schematic of bump height generation (Module One) 74

88 If both component and board warpage are considered together, the 200 distances of separation generated from the component warpage (one that has been converted from 40,000 to 200) and the 200 distances of separation generated from the board warpage (also converted from 40,000 to 200) are combined to generate 40,000 distances of separation and their probabilities. The probability of the distance of separation at a particular bump location is the product of the probabilities of component warpage (in X & Y directions) and board warpage (in X & Y directions). These values are then converted to 200 distances of separation along with their adjusted probabilities (as explained before). The procedure is repeated for every single joint on one-quarter (due to symmetry) of the package. Therefore, for every bump location, there exists an empirical distribution of distance of separation that is characterized by 200 discrete values and the corresponding probabilities. The generated bump height can be compared to the distance of separation at the individual bump location to determine the yield. Flowchart, outlining the scheme of Module Two, is shown in Figure Module Three: comparison of bump heights and distances of separation The bump heights and their corresponding probabilities are determined in the first module, while the distance of separation at each bump location and their corresponding probabilities are determined in the second module. The primary function of this module is to compare the bump heights against the distance of separation at each bump location, in order to determine the number of defects and the probabilities of these defects. The probability of a defective joint is defined as a product of the probabilities of the bump height and the distance of separation, an example of which is presented next. 75

89 COMPONENT WARPAGE BOARD WARPAGE X - direction Y - direction X - direction Y - direction pdf's of component warpage pdf's of board warpage For each location Xi & Yi X- Position of bump Y -Position of bump (Input from text file) COMPONENT WARPAGE BOARD WARPAGE 200 Discrete values of warpage in X - dir. 200 Discrete values of warpage in Y - dir. 200 Discrete values of warpage in X - dir. 200 Discrete values of warpage in Y - dir. 40,000 Distance of separation at location i 40,000 Distance of separation at location i 200 Distance of separation at location i 40,000 Distance of separation at location i 200 Distance of separation at location i 40,000 Distance of separation converted to 200 distance of separation 200 Distance of separation at location i LOOP UNTIL END OF JOINT Figure A schematic of the generation of distance of separation (Module Two) 76

90 Example: The yield calculation procedures mentioned in the three modules are enumerated for a sample case. Assuming the solder bump volume density function with a mean of 900 mils 3 and standard deviation of 45 mils 3, the 200 discrete data points considered on this distribution range (based on a choice of ± 6 sigma limit) from 630 mils 3 to 1170 mils 3 with an increment of mils 3. A sample of the 200 discrete data points on the bump volume density function and their probabilities are shown in the 2 nd and 3 rd columns of Table 3.9.1a. A discrete data point of 630 mils 3 (at negative 6 standard deviation) will have a probability P V (V = 630) = 3.72 x Similarly, the component pad size variation defined by a mean of 12 mils and standard deviation of 0.6 mils, will have 200 data points (shown in Table 3.9.1a, 4 th column) considered in the range of 15.6 mils to 8.4 mils with an increment of 3.61 x A discrete data point of 8.4 mils (also at negative 6 standard deviation) will have a probability P C (C = 8.4) of occurrence = 3.72 x By considering all possible combinations of 200 bump volume data points and equal number of component pad sizes, (as shown in the 2 nd and 4 th column of Table 3.9.1b), a total of 40,000 bump heights with corresponding probabilities are generated. A sample of the 40,000 generated bump heights corresponding to the data points on the bump volume (given in the 2 nd column) and component pad size (shown in the 4 th column) density functions are shown in Table 3.9.1b. The probability of the generated bump height, h is given by: = P V (V = v). P C (C = c) Eq e.g.: for a bump height of (from Table 3.9.1b), its probability is = 3.72 x X 3.72 x = 1.38 x

91 Data points # Bump volume: V = v Probability P v (V = v) Component pad size: C = c Probability P c (C = c) E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-10 Table 3.9.1a: A sample of 200 data points on the bump volume and the component pad size (input) density function 78

92 Combination # V = v P v (V = v) C = c P c (C = c) Bump height h Probability P(h) E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-19 Table 3.9.1b: A sample of 40,000 generated bump height and the corresponding probabilities from bump volume and component pad size density function 79

93 The next step in yield estimation is to convert the 40,000 generated bump heights as shown in 6 th column of Table 3.9.1b, into 200 new bump heights and change its probabilities such that it represents the effect of 40,000 bump heights. In order to accomplish this task, a new increment for bump height is calculated by considering the maximum (11.73 mils) and minimum bump heights (5.62 mils), the increment for this example being 3.07 x Starting with the minimum bump height (of 5.62 mils), the increment value is used to determine the additional 199 bump heights, a sample of which are shown in the 2 nd column of Table 3.9.1c. The recently generated 200 bump heights are used as a bin and all of the previously generated 40,000 bump heights and their probabilities are placed in the respective bins. The value of the bin represents the new bump height and the sum of all the probabilities (corresponding to all the bump height in this bin) represents the probability of occurrence of this height. The adjusted probability value (compared to previously generated 40,000 probabilities for 40,000 bump heights) for the respective bump heights are shown in the 3 rd column of Table 3.9.1c. At this stage, the bump heights are ready for comparison with the distances of separation and hence, estimation of yields. Similar to the case of generating the bump heights from the bump volume and the component pad size density functions, parameters characterizing the component and board warpage are used to generate the distances of separations at each solder bump location on the package (or pad location on the PCB). For the discussion purpose, we assume both the component and the board warpage to be convex with mean of 1.0 mils and a standard deviation of 0.1 mils in both the X and Y directions on a package with 48 80

94 Bump height # Bump height Probability of bump height E E E E E E E E E E E E E E E E E E E E E E E E-18 Table 3.9.1c: A sample of 200 empirical bump heights and the corresponding probabilities, converted from 40,000 generated bump heights and probabilities 81

95 I/O s (see Figure 5.4). The 200 discrete data values considered on each of the four variables (component warpage in X & Y directions and board warpage in X & Y directions) lie in the range of 0.4 mils to 1.6 mils (based on a choice of ± 6 standard deviation) with an increment of 6.03 x Given below is an example to determine the distance of separation based on component warpage, assuming the board to be flat. The example given below is for a single bump location only. However, the procedure is true for other bump locations as well. For a given bump location (say, first location), a sample of the data points (out of 200) and their probabilities, considered on the density function of component warpage in X (2 nd & 4 th column) and Y (5 th & 7 th column) directions are shown in the Table 3.9.2a. Also indicated are the values of warpage function f(w i ) (See Section 3.5.1) for the first solder bump location, in both the X (3 rd column) and Y (6 th column) directions. Considering the 200 discrete values of the warpage function in both the X and Y directions and evaluating all possible combinations leads to 40,000 new values of warpage function for the component. Again a sample of these values are shown in the 6 th column of Table 3.9.2b, along with their probabilities of occurrence. The probability P w (W = W c ) of the component warpage function f(w i ) is given by: = P wx (W = W cx ). P wy (W = W cy ) Eq where: P WX (W = w cx ) is the probability of component warpage in the X direction, and P WY (W = w cy ) is the probability of component warpage in the Y direction eg: probability of a warpage function value (from Table 3.9.2c) is = 3.7 x X 3.7 x = 1.37 x

96 Data points # Device warpage in X direction W = W cx Warpage function In X- dir. f(w i ) Probability P wx (W = W cx ) Device warpage in Y dir. W = W cy Warpage function In Y- dir. f(w i ) Probability P wy (W = W cy ) E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-10 Table 3.9.2a: A sample of 200 data point on the component warpage density function in both the X and Y directions. 83

97 Combination # X-dir. f(w i ) P wx (W = W cx ) Y-dir. f(w i ) P wy (W = W cy ) Overall f(w i ) P w (W = W c ) E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-19 Table 3.9.2b: A sample of 40,000 data point on the component warpage density function. 84

98 Once the 40,000 values of warpage function is generated, the next step is to convert these large amount of warpage function data into 200 new values and adjust its probabilities such that it represents the effect of the original 40,000 values. The methodology used in converting the 40,000 bump heights into 200 new bump heights and adjusted probabilities (as explained before) is used here. A sample of the 200 new values of warpage function and its probabilities are shown in Table 3.9.2c. This value of the warpage function is used to determine the distances of separation, h i, (See Section 3.5.1) at the individual solder bump location. The procedure is repeated for other solder bump locations (based on the X and Y locations of the bump). Therefore, every bump location has an empirical distribution of distances of separation characterized by 200 discrete data points and its probabilities. The same methodology can be used to determine the distances of separation based on board warpage (with flat component). In the case of assemblies with both component and board warpages, the 200 values of warpage function based on component warpage is combined with an equal number of warpage function values determined from the board warpage conditions. All possible combination are evaluated, and the resulting 40,000 values are converted into 200 new combined warpage function with adjusted probabilities. These 200 combined warpage function values and their probabilities are then used to generate the distances of separations at the individual solder bump location on the package. At this stage, the bump heights generated in the First Module (shown in 2 nd column of Table 3.9.3) can be compared to the distance of separations generated in the Second Module (shown in the 4 th column of Table 3.9.3), to determine the assembly yields. 85

99 Combination # Warpage function: f(w i ) P w (W = W c ) E E E E E E E E E E E E E E E E E E E E-19 Table 3.9.2c: A sample of 200 values of warpage function (for location 1) and its probabilities for component warpage 86

100 Combination # Bump height h Probability of bump height Distance of separation (h i ) for L = 1 Probability of distance of separation E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-19 Table 3.9.3: 200 generated bump heights and its probabilities and 200 values of distances of separation (for bump location 1) and its probabilities based on the assembly of warped components to flat boards. 87

101 If the bump height h, is less than the distance of separation h i, the probability of defective joint is given by: = P V (V = v). P C (C = c). P W (W = w c ). P W (W = w b ). P B (B = b). Eq where: P V (V = v) : P C (C = c) : Probability of the solder bump volume Probability of component pad size P W (W = w c ): Probability of component warpage P W (W = w b ) : Probability of board warpage P B (B = b) : Probability of board pad size eg: since bump height (h) = mils is less than the distance of separation (h i ) = mils (from Table 3.9.3), the probability of defective joint is given by: = 1.4 x X 1.39 x = 1.95 x Similarly all the 200 bump heights are compared to the 200 distances of separations at individual bump locations. The sum of all such probabilities (See Section 3.8) is used to determine the final yield value. 88

102 3.10. NUMBER OF DISCRETE POINTS TO BE CONSIDERED ON THE DENSITY FUNCTIONS From the discussion in previous section, it is apparent that the accurate determinations of P 0, P 1 and P L 2 for L=1, 2,.N are crucial for good estimates of the assembly yields. Also, the underlying probability density functions of the random variable C (component pad diameter), V (solder bump volume), B (board pad diameter) and W (component and/or board warpage) are continuos in nature. Since discrete data points are considered on the density function to evaluate all possible combinations among the interacting parameters, the total number of discrete points on individual distribution is crucial for the time required to compute the yield and the accuracy of prediction. In theory, a finitely large number of discrete points should be considered on the individual density functions. However, in practice, the same effect can be achieved by using n discrete points, where n is a reasonable number (much smaller than finitely large value). An experimental study was done to demonstrate that it is sufficient to consider discrete values on the above mentioned density functions (representing the input parameters). The study included evaluation of several cases considering input parameters such as component pad diameter, solder bump volume and board pad diameter, represented by both normal and empirical distributions, and resulted in two main findings: a) as the domains of input variables are discretized into finer intervals, the above mentioned probabilities (such as P 0, P 1 and P L 2) of acceptance (or non-acceptance) of a joint/component converge monotonically to a desired value, and b) it is sufficient to consider a small number of discrete points on the input distributions and evaluate their combinations (as per the interaction) in order to estimate the desired probabilities. It is 89

103 important to note that the convergence of probability values is a relative term. However, since the objective of the model is to predict the assembly yields for million assemblies, the convergence factor has been defined at the level of six decimal places. Sample calculations were done to determine the number of discrete point that needs to be considered on an input density function such that the variations are represented accurately, including those at tails, for the yield determination. For individual sample calculation, 5 to 8 different combinations of discrete points (ranging from 10 to 400) were considered on the density functions, such as component pad diameter and solder volume. In several cases, considering 100 discrete point on individual distribution was found to be relatively sufficient (converged) for yield prediction at the parts /million level. The yield obtained from the converged probability values was compared to yield determined by Monte Carlo Method for one million assemblies (ppm). The yield predicted by both the methods was found to be in a very close range. Based on the observation from several case studies and comparison of results, 200 discrete points on individual distribution has been used in the model software. Key features of a sample case study are discussed below. Three input parameters namely, component pad diameter, solder bump volume and board pad diameter were considered in the determination of probability of an acceptable joint/component. Both component pad diameter and the bump volume were assumed to have normal distribution (Table ), whereas an average value of board pad diameter was considered. Four different cases were evaluated for each set of input 90

104 distributions, with 25, 50, 100 & 200 number of discrete points on the individual density functions. In addition, for individual cases, equal number of discrete points were considered on each of the input parameters. Bump heights and the corresponding probabilities of their occurrence were generated by considering all possible combination of the discrete data point on the component pad diameter and solder volume distribution (e.g., if number of data points = 25, on the individual pad diameter and solder volume density functions, total number of generated bump height = 625). Since average diameter was used for the board pad, the probability of its occurrence is one. The probability of an acceptable (non-acceptable) joint was determined using the expressions discussed in Section 3.7. Details on probability values are shown in Table The first column indicates the number of discrete points considered on the input distribution, whereas the values given in second and third columns represent the probability of acceptable and un-acceptable joints. It is evident from the values in Table and the graph shown in Figure , that the probability of acceptance of a joint converged almost monotonically, to a limit value as the number of discrete points considered on the input distribution was increased. Assembly yield predictions for this set of input parameters are presented in Table The yield represents number of defective joints out of one million joints. For comparison purpose, the same input parameters were used in Monte Carlo based program. Ten different runs were done with each run having one million iterations. The number of simulation runs, average number of defects and standard deviation is shown in Table A comparison of the number of defective joints and the difference in 91

105 percentage yield value between the proposed method and the Monte Carlo method are shown in Table The difference in total number of defective joints determined using 100 discrete points (on the distribution) and those using 200 discrete points are approximately 12 out of 1,000,000 joints. In addition, the percentage difference in the predicted yield values compared to Monte Carlo Method is of the order of % %. The above result was verified on numerous other situations, and consequently was incorporated in the proposed methodology. The saving in computational effort obtained, as a result of this observation is significant and will be demonstrated in later chapters. 92

106 Input Parameter Mean Standard deviation Distribution Component pad diameter (mil) 0.75 Normal Bump volume (mil 3 ) 766 Normal Board pad diameter (mil) 0 Average Table : Characteristics of Input Data for sample calculation Number of Discrete Points (on each distribution) Probability of a Joint being Acceptable (P 0 ) Probability of a Joint being Unacceptable (Q 0 ) Table : Details on the probability values for individual cases 93

107 P(acceptable joint) Number of data point on a distribution Figure : Monotonically increasing probability values vs. number of discrete points on input distributions 94

108 Number of Discrete Points (on each distribution) Probability of a Joint being Unacceptable (Q 0 ) # of defective joints Table : Expected number of defective joints (out of one million joints) determined for individual cases # of Runs # of iterations Average # of defective joints Standard deviation 10 1,000, Table : Number of defective joints for one million iterations using the Monte Carlo approach. 95

109 Number of Discrete Points (on each distribution) # of defective joints Yield (%) # of defective joints (Monte Carlo Method) Yield (%) (Monte Carlo) Difference in # of defective joints (New Model vs. Monte Carlo) in ppm (~126) (~126) (~126) (~126) Table : Comparison of # of defective joints and the % Yield values estimated from the new methodology and those predicted by the Monte Carlo based approach 96

110 3.11. CONCLUSION The variations in the component, board and process related parameters are critical factors for reducing the assembly yields. Good prediction of assembly yield requires an accurate representation of the individual input parameters, an effective methodology to represent the interaction among these parameters and realistic defect determination criteria. In this chapter, we described a new concept for the calculation of yield for an assembly of area array devices on to printed circuit boards. Various aspects of the model including the generation of bump heights, distances of separation, determination of probability, calculation of yield, and requirement of the number of discrete data points on individual parameters were discussed. Furthermore, expressions and equations used in the model were presented. 97

111 CHAPTER FOUR: 4.1. INTRODUCTION TO SOFTWARE DEVELOPMENT/USER S MANUAL Area Array Assembly Yield Model is a tool to estimate the total number of defective joints and components for one million assemblies, as per the distribution of the input variables. Most critical parameters were identified and incorporated in the development of a mathematical model for representing the assembly process. The Yield Model Software is an extension of the mathematical model. It provides a user-friendly front end for the determination of the yield value. The program presents a series of input screen and context sensitive help on individual screens. Yield calculations are performed in different modules based on the option selected by the user. The software has a combination of option button and check box as selection mode. The model (program) can incorporate normal, empirical, experimental distributions or combinations of all distribution types. The model software can be divided into three main parts. Module one generates the bump heights and their probabilities from the pad diameter and solder volume variations or uses the bump height distribution as a direct input. Module two consists of generating the distances of separation and their probabilities, based on, the average solder joint volume and component and board warpages at reflow in the X and Y directions. Module three consists of comparing each bump height with the corresponding distance of separation at each bump location. The yield values are predicted as number of defective joints per million and number of defective components (assemblies) per million or defects within a user-specified number of components. The software requires the 98

112 user to supply information and details on the variables, and it provides a choice of various options to predict the yield. The use of this software does require an understanding of the underlying technology and issues. The program can account for the individual variations of up to eight different assembly parameters and their effect on each of the 4000 solder joints. As such, run times may become substantial (in excess of 24 hours). However, Monte Carlo based predictions for the same at the ppm (parts per million) level would require the simulation of at least 10 7 components (10 10 joints), that is clearly be prohibitive. This chapter presents a discussion on the software development issues, system architecture, the scope of program, yield calculation modules, input screens and system output. It also provides sample yield calculation for two different cases assuming normally distributed input variables and empirical distribution INSTALLATION/UN-INSTALLATION INSTRUCTIONS For installation of the software on the computer hard drive, a set up wizard has been created. Folder named YIELD MODEL contains all the required files (28) including sample file of bump location for a 64 I/O flex CSP (Locat.txt), pad diameter variations (Cpd.txt), bump volume variation (Vol.txt), board warpage in X & Y direction (WBoardX.txt & WBoardY.txt) and component warpage in the X & Y direction (WCompX.txt & WCompY.txt). File named Readme.txt has the details for install/uninstall procedures. First step is to copy the entire folder on to the hard drive. The user should go to windows explorer and double click on the file named setup.exe in the YIELD MODEL folder. The setup.exe file will install the complete software on to the C:\Program 99

113 Files\YM_Form folder. The setup wizard will also create an icon in the windows START MENU. The setup program and the prompts for the installation (during the setup) is very similar to installing any other windows based software. Once the icon is created all the sample text and help file (MODEL HELP.hlp) should be copied to this directory (C:\Program Files\YM_Form). For the calculation purpose, especially in the case of empirical distribution, all the new input text files (Ex: bump location, warpage etc) should be included in this (C:\Program Files\YM_Form) folder only. For successful running of the program, all the.dll (dynamic link library),.ocx (custom control),.exe (executable) files should be preserved. The program can be uninstalled by using the SETTING/CONTROL PANEL/ADD- REMOVE PROGRAM options in the START MENU. The uninstallation procedure removes the files from the C:\Program Files\YM_Form folder. However, some of the files, such as the input text file, may have to be deleted manually. The procedure is very similar to uninstalling any other windows based software Overview of yield model computer program This section describes the application of programming language in the design of the yield model software, systems inputs and output and the architecture of yield calculation module. Also, various navigation tools and terminologies used in the software are discussed. 100

114 Programming Language The yield model has been programmed using Microsoft Visual Basic 5.0. The language is simple yet a powerful tool for developing windows based stand-alone applications. The language was primarily chosen due to its flexibility in developing graphical user interfaces Structure of the Software The software is developed as a user friendly, menu driven interface with simple navigation tools, that prompts the user to input values and/or select options. The software consists of three scenarios, selection of the distribution types and sigma limits, details on input variables and selection of package types. The results are provided at a user-defined defect level or at part per million levels Navigation Tools In order to provide flexibility to the user, a series of command button and navigation tools have been used in the software. A brief description on the tools and terminology used in the software are given below. START BUTTON This button is used to start the yield program and provides a series of windows/forms for details on input variables 101

115 CANCEL BUTTON This Button provides an option to cancel the yield calculation and/or start a new case. It does not quit the program. HELP BUTTON Help has been provided on the individual form/window for the related topics. The help file contains instruction and examples to demonstrate the salient points of the model. The user can also find help on topics using the windows search option. OPTION BUTTON It provides a choice to the user to select only one item among several possibilities. The option button is in the form of a toggle switch. QUIT BUTTON A Single Click on the QUIT button will cause the program to quit. INPUT TEXT BOX This is mainly used to enter, copy or edit information or data, the values entered in the text box are used by the program to execute various modules. CHECK BOX This provides an option for the user to choose between two or more alternatives. It is toggle switch, selecting a particular check box triggers a set of events. FORM/ WINDOW/SCREEN The space provided to the user to input information or present results. VIEW FOOTPRINT BUTTON This button can be used to view the footprints or the bump location as entered by the user in the input text file Locat.txt 102

116 4.4. ERROR/INFORMATION MESSAGES The program has an in-built ability to detect for errors in the input values (as provided by the user), given below are the most probable cause of errors/messages and the corrections required. Wrong Input Values This message prompt is displayed, if strange characters such # etc., (instead of finite numerical values) are entered in the mean or standard deviation input box. Wrong Input Data Values This message indicates that a negative or zero value has been entered for a variable that can only have positive non-zero values SYSTEM INPUT Yield Calculation using the model software is based on a series of inputs and options selected by the user. The user should provide all information corresponding to a particular screen. The software has an in-built ability to check for input data and suggest changes using error or information messages. This section gives a description on input screens and various options available to the user. Double Click on the Program Icon gives the introductory screen as shown in Figure There are two main source of information on the menu bar, Details and About. The topics discussed in Details Sub Menu include the choices available for selection of distribution types, and assumptions in the mathematical model. The About Menu provides the contact address for any reference or questions. 103

117 Figure 4.5.1: Introductory Screen of Yield Model Software 104

118 Program Start A click on the START BUTTON in the introductory screen (Figure 4.5.1) provides the user with subsequent windows to input information on different variables, while the QUIT BUTTON can be used to quit the program Distribution Type and Sigma Limits Once the program has been started, the user can choose one of the two (normal or empirical) distribution type and sigma limits. Empirical distribution type, as mentioned in the model software, includes the experimental or any other distribution type. Also, the choice of sigma limits is applicable only in the case of normal distribution type. Assembly yield model has the capability of using any distribution type. Although, the main module has been written to calculate yields based on normally distributed input variables, there is a separate module to predict yield for variables with empirical distributions Normal (Input) Distribution If a user checks the Normal Distribution Type CHECK BOX, the program assumes that all input variables to be used in the yield determination follow normal distribution and are represented by individual means and standard deviations. For example: variables such as bump volume, solder paste deposit on board, component & board warpage etc are all represented by normal distribution with a mean and standard deviation. 105

119 Experimental (Input) Distribution A click on the Empirical Distribution Type CHECK BOX ensures that the input variables are represented by an empirical or experimental distribution. This option provides a choice of considering different distribution types for the individual input variables. For example: component pad diameter may follow normal distribution, whereas, solder paste volume may follow an experimental distribution. The input data to be used by the model program (for experimental distribution) must follow a specified format as explained later Empirical (Input) Distribution The methodology used for determining the yield based on an empirical distribution is similar to that of using an experimental distribution. The input file needs to be prepared in a similar format (as the experimental distribution). Unlike experimental distribution, in this case, extrapolations at the tail ends are possible by selecting the appropriate sigma limits Combination of Normal, Experimental and Empirical Distributions The model provides an option of using a combination of all the above mentioned distribution types. The key is to generate the input file for respective distribution types and use the option of empirical distribution in the choice of distribution type. For example: the input text file for a normally distributed input variable can be prepared by calculating the probability value for the discrete points based on the mean and standard 106

120 deviation of the distribution. Features are available in software such as Mathematica, Statistica and Microsoft Excel to determine the probability for standard distributions Sigma Limit The selection of sigma limit in the program determines the range of values to be considered (on an input distribution) by the model, for the determination of assembly yield. Since discrete points are considered on input distributions, the value of sigma determines the maximum and minimum data point to be considered on the distribution in addition to the probability of occurrence of these limiting values. The choice of sigma limits has an effect on the assembly yields. A large sigma limit provides an opportunity for evaluating the data points at the far end of (the tail) of the distributions, which otherwise may be neglected. Since a majority of defects occur at the tail portion of the distribution, for greater accuracy, higher sigma limits should be considered. Since the criterion for the determination of the Assembly Yield is at the level of one million parts, choosing ±4.7 sigma seems to be reasonable limit. There are five different choices of sigma limits starting from ±6, ±4.7, ±4.5, ±3 to a user specified sigma limit. The user also has a choice of selecting one sigma value for all the input distributions or individual sigma limit for every variable. Choice of any of the first four options will fix the sigma limit, for all the subsequent input variables, to that particular choice. For Example: If first option (6 Sigma limit) is chosen, variables such as bump volume, paste deposit, component warpage, board warpage etc., will be evaluated to 107

121 the extent of ±6 sigma limits. The selection of INDIVIDUAL SIGMA LIMIT provides an option of evaluating data points on the individual distribution, to the suggested limits BUMP HEIGHT VARIATIONS Based on the choice of the distribution type, the model branches into two separate modules. Assuming that the distribution type has been selected as normal for all the input variables, there are two choices to select the bump height variations. The options are specifying the bump height as direct input or generating the bump heights using the data from the pad size and volume variations. The bump height variation can be represented by measured heights (determined experimentally using a measuring equipment) or calculated heights (from ball volume and package pad diameter). For the case of measured bump height variation, the screen as shown in Figure consists of four input boxes for 1) mean of bump height distribution, 2) standard deviation, 3) sigma limit, and 4) mean component pad diameter. Default units for all the input values are mils. The user can have a single bump of mean height (standard deviation = 0) or a distribution with a specified mean and standard deviation. Data on component pad diameter is used to determine the collapse height of the solder bump. In order to generate the bump heights from the bump volume and component pad variations, six different input boxes require information on the mean, standard deviation and sigma limit on each of the variables. The input screen is shown in Figure

122 FIGURE : Input screen for bump height (as direct input) FIGURE : Input screen for determining bump heights (from solder volume & pad size variations) 109

123 An average pad diameter or volume can be specified by making the standard deviation zero. Statistics on the pad diameter and solder volume variation is used to generate the bump heights. For the case of generated bump heights, the bumps are assumed to have a truncated sphere shape and a simple geometrical expression (explained in Chapter 3) is used to determine the bump heights. This method clearly does not account for damaged or distorted bumps or strange pads on the package SOLDER PASTE DEPOSIT The program provides a choice to determine the assembly yields with or without solder paste deposit. There are three INPUT BOXES for the paste deposit variable (Figure 4.5.4) to be specified in terms of the solder paste volume. The user can specify no deposit, average volume deposit or a distribution for the paste volume deposited on the pad. The program assumes the paste deposit at reflow to be 50 % of the original volume. The user must consider issues related to transfer ratio and efficiency BOARD PAD DETAILS There are five input text boxes (Figure 4.5.4) for the details of pads on board. They are mean and standard deviation of pad diameter, sigma limits pad thickness and pad taper. The pad is assumed to be circular in shape. Representation of the taper as assumed in the software is given in the on-screen help menu, which can be accessed by using the help button. 110

124 FIGURE 4.5.4: Input screen for solder paste deposit on board and board pad details 111

125 4.5.6 PACKAGE TYPE Yield calculation for CSP (chip scale package)/bga (ball grid array) and the Direct chip attach packages are programmed in different modules. All the input information so far, is common to both package types. The main difference between CSP & DCA package is warpage factor. Once the information on bump height, paste deposit and the board pad diameter is entered in the program, the next logical step is to choose the package type between CSP/BGA and DCA CHOICE OF WARPAGE/NO WARPAGE Ideally, both the package and the board should be flat (no warpage) during assembly. However, for large BGA packages, the warpage can be substantial based on the substrate material and the resulting stresses, whereas, in DCA devices, the package warpage is zero. Based on the selection of package type, the user can select warpage or no warpage conditions from the options given in the screen shown in Figure For example, if no warpage is selected, implying that both package and board is flat, the user is presented with an option to start the yield calculation, whereas incase of warpage, the user is presented with screens for input of data on the board and component warpage. Some of the other input parameters required at this stage include package dimension in X & Y direction (length over which the warpage effect needs to be evaluated by the model), number of bump location on one quadrant of the package (i.e., total number of I/O's divided by four, due to assumption of symmetry about the center of package). 112

126 FIGURE 4.5.7: Input screen for selecting zero or finite warpage 113

127 BUMP LOCATION INPUT FILE The program reads X and Y location of the solder bumps from the input text files (locat.txt) provided by the user. The screen used for selection of warpage condition (Figure 4.5.7) also has an option to view the bump location on the package being evaluated. The bumps are represented by the circular dots. A click on the VIEW FOOTPRINTS button provides a visual image of the bump locations as read by the program. This option can be used to correct error(s) in the input text file. The input file representing the bump locations must follow a specified format. A sample input file for the footprint shown in Figure is presented in Figure This file represents a 64 I/O's area array CSP (chip scale package), and contains X & Y coordinates of 16 joints at the lower left corner of the package. It is important to note that the zero reference point, for representing the coordinates of solder bumps, is at the center of package. The yield model software can be used for yield determination of a package having the total number of I/O s anywhere in the range of 4 to Also, since the program reads data from an input file, it requires a unique file name. Therefore, any input file, representing the coordinates of bump locations, must be named locat.txt WARPAGE AT REFLOW (package and board) In the yield model software, warpage is defined as the maximum normal distance between the highest point on the substrate and a straight line joining the two edges of the substrate. The program considers warpage independently in both the X and Y directions. Both component and board warpage can have flat, convex or concave 114

128 FIGURE 4.5.8: A sample input file representing the bump locations (48 I/O) on the package 115

129 shape, also the curvature shape in the X and Y directions can be convex or concave, independent of each other. Warpage is considered to be negative (concave) if the center is lower than the corners and positive (Convex) if the center is higher than the corners. The notations used for the concave or convex warpage are also represented on the input screens. Both component and board warpage is assumed to be symmetric about the center of package. The program assumes same sigma limit for warpage in both X & Y directions. If DCA package type is selected, the user needs to provide information on board warpage only. Various input parameters to be entered for board warpage are shown in Figure However, if a CSP or BGA package is selected, input details are required on both the component (Figure ) and board warpage (Figure ). Input screens in both the cases require input on mean and standard deviation of warpage in X & Y directions and sigma limits. If the warpage shape is concave, negative numbers should be entered whereas, if the warpage shape is convex, positive numbers should be selected. A note provided on the screen represents the convention of concave and convex warpage shapes for both components and boards. If a CSP or BGA package having warped surface is assembled on flat boards, the parameters specifying the board warpage should have zero values CALCULATE With the assumption that input variables follow normal distribution, the input data specified so far (by the user) is sufficient to predict the assembly yield. The yield 116

130 FIGURE : Input Screen for Board Warpage in both X & Y direction FIGURE : Input Screen for Component Warpage in both X & Y direction 117

131 calculation can be started by specifying the number of components in the input screen shown in Figure and by pressing the CALCULATE button. The user can enter any number (non-negative) of components (less than, equal to or greater than one million components). The assembly yields are based on the number of components entered by the user. In addition, there is an option to convert the prediction for any number of components into ppm (parts per million level) by simple click of buttons provided on the output screen. 4.6 EMPIRICAL / EXPERIMENTAL / NON-NORMAL DISTRIBUTION TYPE The choice of distribution type in the software program has been provided to incorporate all distributions representing the input parameters for the determination of assembly yields. An assumption of normally distributed variable may incorporate a degree of approximation into the yield calculation. If the given data is not normally distributed, the user has the option to select an approximate normal fit to the data or use the input distribution as it is. This would enable representation of the input distribution much closer to the actual variation. In order to use this option, empirical distribution type should be selected at the beginning of the model. It is important to note that the empirical distributions may be truncated based on the observed limiting value, for a certain sample size of package or board. Therefore, it restricts the option of extrapolation at the tails of the distribution. Also, the limits to which data may be considered for yield calculation depend to a great extent on the sample size chosen to determine the experimental distribution. For example: yield predicted (at 118

132 FIGURE : Input screen for entering the total number of components to be evaluated (less than, equal to or greater than one million devices) 119

133 parts per million level) by using an experimental distribution of bump height for a sample size of 100 or 50,000 will usually be very different. Therefore, using an experimental distribution to predict assembly yields may underestimate the defect level. In the case of empirical distribution, choosing appropriate sigma limits may help in extrapolating the tail of a distribution, but in case of truncated experimental distribution, the predicted yield will be an underestimate. As mentioned in Chapter 3 (Section 3.9), it was concluded that considering 200 discrete data points on an input distribution is sufficient to accurately represent the characteristics of the input variable for the purpose of yield determination. Since the input variables are represented by an empirical distribution, an input text file containing 200 discrete data points and its corresponding probabilities needs to be prepared. Format of a typical input text file is shown in Figure In order to predict the assembly yields, the software program reads data from the input file. Also, the input files must have unique name as mentioned below. 1) BUMPM.txt (for measured bump height distribution) 2) CPD.txt (for component pad diameter) 3) VOL.txt (for solder ball volume) 4) Locat.txt (for bump location details) 5) WCompX.txt (for component warpage in X direction) 6) WCompY.txt (for component warpage in Y direction) 7) WBoardX.txt (for board warpage in X direction) 8) WBoardY.txt (for board warpage in Y direction) 9) Paste.txt (for paste Height variation) 120

134 FIGURE 4.6.1: Sample input file (bump height variation) representing an experimental distribution 121

135 Format of Data in Input Text File: It is required that the number in the input files be restricted to three decimal places (example.002 instead of ) else the numbers should be written in the form of scientific expression such as 2.0E-6. The files are opened and the data read by the software based on the user s choice of variables. For example, if the board and components have no warpage, the program does not search for the related input files. In addition, input files should be stored in the same directory as the yield model software File preparation for Empirical/ Experimental Distribution The yield model software has the capability to determine assembly yields for input variables having normal or empirical distribution. Preparing computer codes for several different standard distribution types and performing curve fitting procedures for experimental distribution is an uphill task and beyond the scope of this research. The same objective can be achieved by following the file preparation procedure explained below. This approach is true for any distribution type including normal distribution. The input file (for a variable having empirical distribution) contains two main attributes, namely data points of the variable and its probability of occurrence. Given below is a sample for preparing an input text file for a variable (measured bump height) in a format that can be read by the model software and used for predicting the assembly yields. The measurement unit of bump height used in this example is mil. A total of 1320 solder bumps were measured to obtain statistics on its height variation. All the individual data points are available in a Microsoft Excel Sheet as shown in column A of Figure

136 The mean bump height is mils and standard deviation is First step is to determine the maximum and minimum bump height and divide the range by 199 (for 200 data points), this gives the ( h) increment value for the bump height. The maximum, minimum and increment values in this case are 23.03, and mils, respectively. Next step is to generate the new bump heights and their probabilities. New bump height starts from the minimum observed value (i.e., mil) and the subsequent bump height with an increment of In this example, the 200 new bump heights start at and end at The generated bump heights are shown in column E of Figure In order to use the new bump heights in the yield determination, its probability of occurrence needs to be determined. These probabilities will be based on the distribution defined by 1320 measured bump heights. A histogram needs to be calculated using the distribution of 1320 points (column A) as the input value and discrete new bump height (column E) of 200 as the bin size. Microsoft Excel can be used to determine the frequency table, via OPTIONS, DATA ANALYSIS and HISTOGRAM items in the menu bar. Each of the bin (i.e. the 200 new bump heights) will have a certain frequency value as shown in Column F of Figure The probability of this bin is the ratio of this frequency divided by total frequency (1320 in this case). This method is an approximation to calculate the area of the individual bin size based on the curve represented by the 1320 measured bump heights. The frequency values are shown in Column G of Figure

137 FIGURE 4.6.2: An example representing file preparation for empirical / experimental distribution 124

138 Columns representing the new bump heights (column E) and probability of bump heights (column G) can be copied to the text file and saved as BUMPM.txt. The resulting text file should not have any empty space or text between the rows or columns, or at the beginning of the rows. The first column should be bump height and the second column its corresponding probability value. Outlook of the final input text file to be used in the yield calculation should be similar to the one shown in Figure The above mentioned procedure can be used to prepare input text files for any distribution type, as long as the probability values of discrete data points can be determined. The idea is to represent variations of 1320 bump heights with a new set of 200 bump heights that lie within the same range (of 1320 heights). Although the individual new heights are different, the effect (of actual variation) is accomplished by considering these 200 new heights along with their probability of occurrence PROCESSING OF DATA Information provided by the user is processed through the use of multiple Visual Basic forms. The user interface is designed as a series of input screens composed on forms. The data input in each screen is processed behind the same screen or in the central module, depending on the options selected by the user. During processing, the program checks for validity of the entered data and assigns the processed results to corresponding variables. These variables are available to all parts of the program. Change to an input variable, at any stage of the program, will automatically update the variables in the subsequent modules. The program has in-built features to check for the 125

139 validity of data entered in the forms. It also ensures that the user inputs all required information before proceeding to the next input screen. Errors regarding the nature of the input values is reported through error or information messages Run Time In general, the total time required to complete calculation will depend on the configuration of computer. For the sake of illustration, yield prediction for a DCA device with only 4 I/O's, assuming variable board warpage in X & Y directions may require a minute. The user may wish to time such a case for his/her computer for reference. For the purpose of estimate, the total time can be assumed to be proportional to number of I/O (if warpage varies). Inclusion of component warpage variations roughly doubles the time Yield Calculation Modules Based on the options selected and the data provided by the user, the yield calculation in the software can be divided into three sections or modules. First module is used to generate the solder bump height and consider the effect of solder paste deposit on board (see Section 3.9.1). The second module determines the distance of separation between the board and package substrate for every solder bump location on the package (see Section 3.9.2). Maximum amount of calculation is done in both, the first and second modules. The third module is used for comparing the generated bump heights (Module one) and the distance of separations (Module two), to determine the probability values, which is ultimately used to determine the assembly yields. 126

140 4.8. SYSTEM OUTPUT The system output of the assembly yield model software is presented in two different screens. The screens display the expected number of defective joints and the expected number of defective components. This screen (shown in Figure 4.8.1) displays the prediction for a desired number of components and joints. The first TEXT BOX indicates the expected number of defective joint, while the second box indicates the expected number of defective components. If the user decides to determine the defect at the parts per million or joints per million level, a click on the YIELD FOR A MILLION JOINTS or COMPONENTS button shown in Figure 4.8.1, performs the desired conversion. The resulting ppm yield values is displayed in the screen shown in Figure This is the last screen presented in the yield software and it provides the user with two choices, quit the program (QUIT button) or go back to the previous screen (BACK button) CONCLUSION One of the important aspects of a software program representing a mathematical model is its robustness and its ability to check for the validity of data entered by the user. The assembly yield model software, addresses both of these issues. The user has been provided with a flexibility to choose variables and provide information by use of simple buttons, checks and text boxes. A brief description has been provided regarding the system output and the option available to the user to predict yields for any number of devices or joints (i.e., less than, equal to or greater than one million assemblies). An overview of the software program and its capabilities were provided in this chapter. 127

141 FIGURE 4.8.1: Predicted yield value for a user specified number of components FIGURE 4.8.2: Predicted yield value for one million components 128