ARM Interrupts. EE383: Introduction to Embedded Systems University of Kentucky. James E. Lumpp

Transcription

1 ARM Interrupts EE383: Introduction to Embedded Systems University of Kentucky James E. Lumpp Includes material from: - Jonathan Valvano, Introduction to ARM Cortex-M Microcontrollers, Volume 1 Ebook, EE 319K, EE319L Lecture Notes 1

2 Interrupts An interrupt is the automatic transfer of software execution in response to an event (trigger) that is asynchronous with current software execution. external I/O device (like a keyboard or printer) or an internal event (like an op code fault, or a periodic timer.) Occurs when the hardware needs or can service Function called by hardware 2

3 Interrupt Processing Hardware Busy Done Busy Main Thread Interrupt Thread Hardware needs service Saves execution state ISR provides service Restores execution state time 3

4 Interrupt Events Respond to infrequent but important events Alarm conditions like low battery power Error conditions I/O synchronization Trigger interrupt when signal on a port changes Periodic interrupts Generated by the timer at a regular rate Systick timer can generate interrupt when it hits zero Reload value + frequency determine interrupt rate 4

5 ARM Cortex-M Interrupts Cortex-M 240 possible interrupt sources 77 interrupt sources on TM4C123 Each potential interrupt source has a separate arm bit Set for those devices from which it wishes to accept interrupts, Deactivate in those devices from which interrupts are not allowed Each potential interrupt source has a separate flag bit hardware sets the flag when it wishes to request an interrupt software clears the flag in ISR to signify it is processing the request Interrupt enable conditions in processor Global interrupt enable bit, I, in PRIMASK register Priority level, BASEPRI, of allowed interrupts (0 = all) 5

6 Interrupt Conditions Four conditions must be true simultaneously for an interrupt to occur: 1. Arm: control bit for each possible source is set 2. Enable: interrupts globally enabled (I=0 in PRIMASK) 3. Level: interrupt level must be less than BASEPRI 4. Trigger: hardware action sets source-specific flag Interrupt remains pending if trigger is set but any other condition is not true Interrupt serviced once all conditions become true Need to acknowledge interrupt Clear trigger flag or will get endless interrupts! 6

7 Interrupt Processing 1. The execution of the main program is suspended 1. the current instruction is finished, 2. suspend execution and push 8 registers (R0-R3, R12, LR, PC, PSR) on the stack 3. LR set to 0xFFFFFFF9 (indicates interrupt return) 4. IPSR set to interrupt number 5. sets PC to ISR address 2. The interrupt service routine (ISR) is executed clears the flag that requested the interrupt performs necessary operations communicates using global variables 3. The main program is resumed when ISR executes BX LR pulls the 8 registers from the stack 7

8 Saving Registers R0-R3 parameters R4-R11 must be saved R14, R15 are important SP (R13) refers to PSP or MSP We will use just the MSP PRIMASK has intr. enable (I) bit BASEPRI has allowed intr. priority 8

9 Interrupt Context Switch I 0 IPSR 0 BASEPRI 0 MSP Before interrupt I 0 RAM Context Switch Finish instruction IPSR 18 a) Push registers b) PC = {0x } BASEPRI 0 c) Set IPSR = 18 d) Set LR = 0xFFFFFFF9 Use MSP as stack pointer MSP Stack After interrupt old R0 old R1 old R2 old R3 old R12 old LR old PC old PSR Stack Vector address for GPIO Port C Interrupt Number 18 corresponds to GPIO Port C EE383/Spring 2015/L9 J. E. Lumpp, Jr. 9

10 Selected TM4C Interrupt Vectors Vector address Num IRQ ISR NVIC Priority bits 0x C 15-1 SysTick Handler 0x GPIO Port A NVIC_PRI0_R 7 5 0x GPIO Port B NVIC_PRI0_R x GPIO Port C NVIC_PRI0_R x C 19 3 GPIO Port D NVIC_PRI0_R x GPIO Port E NVIC_PRI1_R 7 5 0x UART0 Rx/Tx NVIC_PRI1_R x UART1 Rx/Tx NVIC_PRI1_R x ADC Sequence 0 NVIC_PRI3_R x C Timer 0A NVIC_PRI4_R x Timer 0B NVIC_PRI5_R 7 5 0x Timer 1A NVIC_PRI5_R x Timer 1B NVIC_PRI5_R x C Timer 2A NVIC_PRI5_R x000000A Timer 2B NVIC_PRI6_R 7 5 0x000000B GPIO Port F NVIC_PRI7_R x000000CC Timer 3A NVIC_PRI8_R x000000D Timer 3B NVIC_PRI9_R interrupt sources on TM4C123 with 8 priority levels 10

11 Interrupt Rituals Things you must do in every ritual Initialize data structures (counters, pointers) Arm (specify a flag may interrupt) Configure NVIC Enable interrupt (NVIC_EN0_R) Set priority (e.g., NVIC_PRI1_R) Enable Interrupts Assembly code C code CPSIE I EnableInterrupts(); 11

12 Arm Bits Each potential interrupt source has a separate arm bit. Set arm bits for those devices from which it wishes to accept interrupts, Deactivate arm bits in those devices from which interrupts are not allowed 12

13 Nested Vectored Interrupt Controller (NVIC) Hardware unit that coordinates among interrupts from multiple sources Define priority level of each interrupt source (NVIC_PRIx_R registers) Separate enable flag for each interrupt source (NVIC_EN0_R and NVIC_EN1_R) Interrupt does not set I bit Higher priority interrupts can interrupt lower priority ones 13

14 NVIC Priority Registers 12 NVIC_PRI Registers 8 priority levels (0-high, 7-low) High order three bits of each byte define priority Address Name 0xE000E400 GPIO Port D GPIO Port C GPIO Port B GPIO Port A NVIC_PRI0_R 0xE000E404 SSI0, Rx Tx UART1, Rx Tx UART0, Rx Tx GPIO Port E NVIC_PRI1_R 0xE000E408 PWM Gen 1 PWM Gen 0 PWM Fault I2C0 NVIC_PRI2_R 0xE000E40C ADC Seq 1 ADC Seq 0 Quad Encoder PWM Gen 2 NVIC_PRI3_R 0xE000E410 Timer 0A Watchdog ADC Seq 3 ADC Seq 2 NVIC_PRI4_R 0xE000E414 Timer 2A Timer 1B Timer 1A Timer 0B NVIC_PRI5_R 0xE000E418 Comp 2 Comp 1 Comp 0 Timer 2B NVIC_PRI6_R 0xE000E41C GPIO Port G GPIO Port F Flash Control System Control NVIC_PRI7_R 0xE000E420 Timer 3A SSI1, Rx Tx UART2, Rx Tx GPIO Port H NVIC_PRI8_R 0xE000E424 CAN0 Quad Encoder 1 I2C1 Timer 3B NVIC_PRI9_R 0xE000E428 Hibernate Ethernet CAN2 CAN1 NVIC_PRI10_R 0xE000E42C udma Error udma Soft Tfr PWM Gen 3 USB0 NVIC_PRI11_R 0xE000ED20 SysTick PendSV -- Debug NVIC_SYS_PRI3_R 14

15 NVIC Interrupt Enable Registers Two enable registers NVIC_EN0_R and NVIC_EN1_R Each 32-bit register has a single enable bit for a particular device NVIC_EN0_R control the IRQ numbers 0 to 31 (interrupt numbers 16 47) NVIC_EN1_R control the IRQ numbers 32 to 47 (interrupt numbers 48 63) 15

16 Device Enable Nested Vectored Interrupt Controller (NVIC) Device must be enabled in the NVIC and its priority set BASEPRI register sets priority of interrupts that are permitted to occur if BASEPRI = 3, interrupts with priority 0 2 can occur, suspending this interrupt 3-7 will be postponed until this interrupt is finished 16

17 Priority Mask Register Disable interrupts (I=1) CPSID I Enable interrupts (I=0) CPSIE I MRS R0,PRIMASK CPSID I MRS PRIMASK,R0 Interface latency 17

18 Interrupt Service Routine (ISR) Things you must do in every interrupt service routine Acknowledge clear flag that requested the interrupt SysTick is exception; automatic acknowledge Maintain contents of R4-R11 (AAPCS) Communicate via shared global variables 18

19 Flag Bits Each potential interrupt source has a separate flag bit. hardware sets the flag when it wishes to request an interrupt software clears the flag in ISR to signify it is processing the request 19

20 Program Status Register Accessed separately or all at once Q = Saturation, T = Thumb bit 20

21 Interrupt Program Status Register (ISPR) Run debugger: - stop in ISR and - look at IPSR 21

22 Interrupt Enable/Disable ;*********** DisableInterrupts *************** ; disable interrupts ; inputs: none ; outputs: none DisableInterrupts CPSID I BX LR ;*********** EnableInterrupts *************** ; disable interrupts ; inputs: none ; outputs: none EnableInterrupts CPSIE I BX LR 22

23 Critical Sections Shared access to permanently allocated data or I/O port Multistep non-atomic sequence, in which one step is a write: Read modify write Write write Write read 23

24 Critical Sections Implementation ;*********** StartCritical ************************ ; make a copy of previous I bit, disable interrupts ; inputs: none ; outputs: previous I bit StartCritical MRS R0, PRIMASK ; save old status CPSID I ; mask all (except faults) BX LR ;*********** EndCritical ************************ ; using the copy of previous I bit, ; restore I bit to previous value ; inputs: previous I bit ; outputs: none EndCritical MSR PRIMASK, R0 BX LR 24

25 Critical Sections Example Force critical write to be atomic eliminate critical section unsigned long volatile num; void Count(void){ long sr; sr = StartCritical(); num = num + 1; EndCritical(sr); } 25