EE251: Tuesday October 23

Size: px
Start display at page:

Download "EE251: Tuesday October 23"

Transcription

1 EE251: Tuesday October 23 Higher Frequency Clock via Phase Locked Loop TIMER MODULE: SysTick-Basis of next week s lab Section 12.4 and 18 in text describes our SysTick Section 2.5 of Valvano s Real Time Interfacing text Several SysTick slides are from Dr. Jonathan Valvano, University of Texas SysTick Use of Interrupts Lab 5 Due This Week Lab 6 (AtoD Conversion) This Week. Homework #5 Due Thursday Lab 7 (SysTick Timer) Next Week Lecture #19 1

2 PLL: Phase-Locked Loop External crystal Main Osc 16 MHz Internal Osc /4 30 khz Internal Osc Ref Clk OSCSRC 00 Mux 01 10* 11* Phase/ Freq Detector Phase-Lock-Loop Up Down * can't drive the PLL /m Charge Pump/ LPF VCO 400 MHz /2 DIV400 1 Mux MHz BYPASS USESYSDIV 1 Mux 0 0 Mux /n SYSDIV 1 XTAL Internal oscillator requires minimal power but is imprecise External crystal provides stable bus clock TM4C is equipped with 16 MHz crystal and bus clock can be set to a maximum of 80 MHz See Wikipedia s entry on Phase-Locked Loop for explanation Lecture #19 2

3 Phase-Locked Loop Software to enable the phase-lock loop is not worth the effort to explain in this course. Example source code to enable changing the system clock frequency is available in Code Files on our lab web page. We have tested this code. PLL.s subroutine to enable PLL PLL_main.s program to demonstrate its use Used with Precision Clock Lecture #19 3

4 SysTick Timer Timer/Counter operation 24-bit counter decrements at system clock frequency (or precision clock frequency 4) 16 MHz system clock 62.5 ns decrements 16 MHz precision clock ns decrements Counting is from n 0 Setting n appropriately will make the counter a modulo n+1 counter. That is: next_value = (current_value-1) mod (n+1) Sequence: n,n-1,n-2,n-3 2,1,0,n,n-1 E.g. Find n for a 1 ms. count to 0 at 16 MHz? For system clock: 1ms/62.5ns = 16,000 = n+1 or n = 15,999 Will this fit in 24 bits? How big can n be? How much time is this? Lecture #19 4

5 SysTick Registers Initialization (4 steps) SysTick Timer Address Name $E000E COUNT 0 CLK_SRC INTEN ENABLE NVIC_ST_CTRL_R $E000E bit RELOAD value NVIC_ST_RELOAD_R $E000E bit CURRENT value of SysTick counter NVIC_ST_CURRENT_R Step1: Clear ENABLE bit to stop counter Step2: Specify the RELOAD value n (from previous slide) Step3: Clear the counter by writing to register NVIC_ST_CURRENT_R Step4: Set CLK_SRC=1 (system) or 0 (precision) and specify whether interrupt action via INTEN in NVIC_ST_CTRL_R For details, see the Tiva TM4C123GH6PM Microcontroller Data Sheet, Sect , p. 123 and Section 3.3, pp Lecture #19 5

6 SysTick Status Lecture #19 6

7 SysTick Control Lecture #19 7

8 Lecture #19 8

9 Lecture #19 9

10 SysTick Timer Setup Subroutine SysTick_Init ; disable SysTick during setup LDR R1, =NVIC_ST_CTRL_R MOV R0, #0 ; Clear Enable STR R0, [R1] ; set reload to maximum reload value LDR R1, =NVIC_ST_RELOAD_R LDR R0, =0x00FFFFFF; ; Specify RELOAD value STR R0, [R1] ; reload at maximum ; writing any value to CURRENT clears it LDR R1, =NVIC_ST_CURRENT_R STR R0, [R1] ; clear counter ; enable SysTick with core clock LDR R1, =NVIC_ST_CTRL_R MOV R0, #0x0005 ; Enable but no interrupts (later) STR R0, [R1] ; ENABLE with System Clock BX LR ; Return from subroutine Lecture #19 10

11 Time Delay Subroutine (Polling) ; SysTick_Wait ; Time delay using busy wait. ; Input: R0 delay parameter in ticks of the core clock ; At 16 MHz, tick is 62.5 nsec ; Output: none ; Modifies: R1 SysTick_Wait SUB R0, R0, #1 ; delay-1 LDR R1, =NVIC_ST_RELOAD_R STR R0, [R1] ; time to wait LDR R1, =NVIC_ST_CURRENT_R STR R0, [R1] ; any value written to CURRENT clears LDR R1, =NVIC_ST_CTRL_R SysTick_Wait_loop LDR R0, [R1] ; read status ANDS R0, R0, #0x ; bit 16 is COUNT flag BEQ SysTick_Wait_loop ; repeat until flag set BX LR ; flag set, so return from sub Lecture #19 11

12 Delay Using SysTick_Wait ; SysTick_Wait10ms ; Call this routine to wait for R0*10 ms ; Time delay using busy wait. This assumes 16 MHz clock ; Input: R0 number of times to wait 10 ms before returning ; Output: none ; Modifies: R0 DELAY10MS EQU ; clock cycles for 10 ms delay SysTick_Wait10ms PUSH {R4, LR} ; save R4 and LR MOVS R4, R0 ; R4 = R0 = remainingwaits BEQ SysTick_Wait10ms_done ; R4 == 0, done ; SysTick_Wait10ms_loop LDR R0, =DELAY10MS ; R0 = DELAY10MS BL SysTick_Wait ; wait 10 ms SUBS R4, R4, #1 ; remainingwaits-- BHI SysTick_Wait10ms_loop ; if(r4>0), wait another 10 ms ; SysTick_Wait10ms_done POP {R4, PC} ; pop R4 and Return Lecture #19 12

13 SysTick Timer Methods Method just shown uses polling. When would using polling be appropriate? Will show how to initiate and use interrupts Frees up processor for other tasks Basis for Real-Time systems SysTick Interrupts will be used in Lab 7 Also Precision Clock, but no PLL Lecture #19 13

14 Lab 7 Fig Data Structures NVIC_ST_CTRL NVIC_ST_RELOAD NVIC_ST_CURRENT SHP_SYSPRI3 RELOAD_VALUE Stack EQU 0xE000E010 EQU 0xE000E014 EQU 0xE000E018 EQU 0xE000ED20 EQU 0x EQU 0x EXTERN OutStr ; Stack area AREA STACK, NOINIT, READWRITE, ALIGN=3 StackMem SPACE Stack ; Reset area AREA RESET, CODE, READONLY THUMB EXPORT Vectors Vectors DCD StackMem + Stack ; Top of Stack DCD Reset_Handler ; Reset Handler... DCD SysTick_Handler ; SysTick Handler Lecture #19 14

15 Lab 7 Fig Setup/Main ; Program area AREA.text, CODE, READONLY, ALIGN=2 THUMB EXPORT Reset_Handler Reset_Handler LDR R1, =NVIC_ST_CTRL ; Systick Setup MOV R0, #0 STR R0, [R1] LDR R1, =NVIC_ST_RELOAD LDR R0, =RELOAD_VALUE STR R0, [R1] LDR R1, =NVIC_ST_CURRENT MOV R0, #0 STR R0, [R1] LDR R1, =SHP_SYSPRI3 MOV R0, #0x STR R0, [R1] LDR R1, =NVIC_ST_CTRL MOV R0, #0x03 STR R0, [R1] ; End of Systick Setup. Main follows CPSIE I ; Systick Main Program wait WFI B wait Lecture #19 15

16 Lab 7 Fig. 7.5 SysTick ISR ; SysTick ISR EXPORT SysTick_Handler SysTick_Handler ; Systick Interrupt Service Routine (ISR) PUSH {LR} ; Save whatever was in LR since BL Outstr will change this! LDR R0,=hello ; Address of message to Termite in R0 BL OutStr POP {LR} BX LR ; Data area hello DCB "Hello from SysTick",13,4 ALIGN END Lecture #19 16

17 Enable SysTick Interrupts SysTickInts.s enables interrupts in SysTick (from TI/Texas U) ; **************SysTick_Init********************* ; Initialize SysTick periodic interrupts, priority 2 ; Input: R0 interrupt period Units of period are 1/clockfreq ; Maximum is 2^24-1 Minimum is determined by length of ISR ; Output: none Modifies: R0, R1, R2, R3 SysTick_Init ; start critical section MRS R3, PRIMASK ; save old status CPSID I ; mask all interrupts(except faults) ; disable SysTick during setup LDR R1, =NVIC_ST_CTRL_R MOV R2, #0 STR R2, [R1] ; maximum reload value LDR R1, =NVIC_ST_RELOAD_R ; R1 is pointer to NVIC_ST_CTRL_R ; disable SysTick ; R1 is pointer to NVIC_ST_RELOAD_R SUB R0, R0, #1 ; counts down from RELOAD to 0 STR R0, [R1] ; establish interrupt period ; any write to CURRENT_R clears it LDR R1, =NVIC_ST_CURRENT_R ; R1 is pointer to NVIC_ST_CURRENT_R STR R2, [R1] ; writing to counter clears it Lecture #19 17

18 Enable SysTick Interrupts SysTickInts.s continued ; set NVIC system interrupt 15 to priority 2 LDR R1, =NVIC_SYS_PRI3_R LDR R2, [R1] ; R1 = &NVIC_SYS_PRI3_R (pointer) ; friendly access AND R2, R2, #0x00FFFFFF ; R2 = R2&0x00FFFFFF (clear interrupt 15 ORR R2, R2, #0x ; priority) ; R2 = R2 0x (interrupt 15 priority ; is in bits 31-29) STR R2, [R1] ; set SysTick to priority 2 ; enable SysTick with core clock LDR R1, =NVIC_ST_CTRL_R ; R1 = &NVIC_ST_CTRL_R ; ENABLE SysTick (bit 0), INTEN enable interrupts (bit 1), and ; CLK_SRC (bit 2) is internal MOV R2, #(NVIC_ST_CTRL_ENABLE+NVIC_ST_CTRL_INTEN+NVIC_ST_CTRL_CLK_SRC) STR R2, [R1] ; end critical section ; store a 7 to NVIC_ST_CTRL_R MSR PRIMASK, R3 ; restore old status BX LR ; return Lecture #19 18

19 SysTick Interrupt Handler PeriodicSysTickInts.s SysTick Interrupt Handler from TI/Texas U EXPORT SysTick_Handler SysTick_Handler ; increment Counts LDR R2, =Counts LDR R3, [R2] ; SysTick Interrupt Service Routine ; R2 = &Counts (pointer) ADD R3, R3, #1 ; R3 = R3 + 1 (Counts = Counts + 1) STR R3, [R2] ; Change LED LDR R2, =GPIO_PORTF_DATA_R AND R3, #0x E ; (overflows after 49 days) ; R2 = &GPIO_PORTF_DATA_R (pointer) ; Keep LED bits only BX LR STR R3, [R2] ; Store back into Port F Data Register ; return from interrupt ; Is this just a regular subroutine return??? Lecture #19 19

20 SysTick Main Program PeriodicSysTickInts.s Skeleton of main program from TI/ Texas U Start BL PLL_Init ; activate clock for Port F ; set direction register ; regular port function ; enable digital port ; configure as GPIO ; disable analog functionality ; initialize Counts loop WFI LDR R1, =Counts ; 50 MHz clock MOV R0, #0 ; R0 = 0 ; R1 = &Counts (pointer) STR R0, [R1] ; [R1] = R0 (Counts = 0) ; enable SysTick MOV R0, #0x00FFFFFF BL SysTick_Init CPSIE I ; initialize SysTick timer for slow interrupts ; enable SysTick ; enable interrupts and configurable fault ; handlers (clear PRIMASK) ; wait for interrupt B loop ; unconditional branch to 'loop' Lecture #19 20

21 SysTick Summary SysTick can be used as a time delay It is most powerful as method for creating interrupts on a fixed interval Programming SysTick is straightforward Creating a real-time system based on it is a bit more complex, but fixed-time interrupts is required in many real system environments See both Lecture and Lab Examples Next topic: Timer Module, a Major Topic and basis for Lab #8. Lecture #19 21

ECE251: Thursday September 27

ECE251: Thursday September 27 ECE251: Thursday September 27 Exceptions: Interrupts and Resets Chapter in text and Lab #6. READ ALL this material! This will NOT be on the mid-term exam. Lab Practical Exam #1 Homework # due today at

More information

Modes and Levels. Registers. Registers. Cortex-M3 programming

Modes and Levels. Registers. Registers. Cortex-M3 programming Modes and Levels Cortex-M3 programming Texas Instruments, www.ti.com CortexM3InstructionSet.pdf STMicroelectronics, www.st.com CortexM3Programmer.pdf PM0056 Registers Registers R0-R3 parameters R4-R11

More information

Timers and Pulse Accumulator

Timers and Pulse Accumulator 7 7.1 Objectives: Tiva is equipped with six General Purpose Timer Modules named TIMERn. Additionally, each TIMERn consists of two 16 bit timers (A and B). Most GPIO pins can be assigned a TIMERn as an

More information

ARM Interrupts. EE383: Introduction to Embedded Systems University of Kentucky. James E. Lumpp

ARM Interrupts. EE383: Introduction to Embedded Systems University of Kentucky. James E. Lumpp ARM Interrupts EE383: Introduction to Embedded Systems University of Kentucky James E. Lumpp Includes material from: - Jonathan Valvano, Introduction to ARM Cortex-M Microcontrollers, Volume 1 Ebook, EE

More information

EE4144: ARM Cortex-M Processor

EE4144: ARM Cortex-M Processor EE4144: ARM Cortex-M Processor EE4144 Fall 2014 EE4144 EE4144: ARM Cortex-M Processor Fall 2014 1 / 10 ARM Cortex-M 32-bit RISC processor Cortex-M4F Cortex-M3 + DSP instructions + floating point unit (FPU)

More information

Subroutines and the Stack

Subroutines and the Stack 3 31 Objectives: A subroutine is a reusable program module A main program can call or jump to the subroutine one or more times The stack is used in several ways when subroutines are called In this lab

More information

Embedded Systems. October 2, 2017

Embedded Systems. October 2, 2017 15-348 Embedded Systems October 2, 2017 Announcements Read pages 267 275 The Plan! Timers and Counter Interrupts A little review of timers How do we keep track of seconds using a timer? We have several

More information

Design and Implementation Interrupt Mechanism

Design and Implementation Interrupt Mechanism Design and Implementation Interrupt Mechanism 1 Module Overview Study processor interruption; Design and implement of an interrupt mechanism which responds to interrupts from timer and UART; Program interrupt

More information

Interrupt-Driven Input/Output

Interrupt-Driven Input/Output Interrupt-Driven Input/Output Textbook: Chapter 11 (Interrupts) ARM Cortex-M4 User Guide (Interrupts, exceptions, NVIC) Sections 2.1.4, 2.3 Exceptions and interrupts Section 4.2 Nested Vectored Interrupt

More information

References & Terminology

References & Terminology , 2/22/2018 Embedded and Real-Time Systems/ Real-Time Operating Systems : RTOS, OS Kernel, Operating Modes, Context Switch 1 References & Terminology μc/os-iii, The Real-Time Kernel, or a High Performance,

More information

ECE251: Thursday September 13

ECE251: Thursday September 13 ECE251: Thursday September 13 Lab 9: Some Details Stack and Subroutines, continued--chapter 8 Stack Example SUBROUTINES More Details Initializing the Stack/Pointer Passing Parameters to Subroutines via

More information

(5) Question 2. Give the two most important factors for effective debugging. Jonathan W. Valvano

(5) Question 2. Give the two most important factors for effective debugging. Jonathan W. Valvano EE445M/EE380L Quiz 1 Spring 2013 Page 1 of 5 First Name: Last Name: March 1, 2013, 10:00 to 10:50am Quiz 1 is a closed book exam. You may have one 8.5 by 11 inch sheet of hand-written crib notes, but no

More information

ECE251: Tuesday September 18

ECE251: Tuesday September 18 ECE251: Tuesday September 18 Subroutine Parameter Passing (Important) Allocating Memory in Subroutines (Important) Recursive Subroutines (Good to know) Debugging Hints Programming Hints Preview of I/O

More information

// middle priority ISR Status.flag = 1; Status.y = 6;

// middle priority ISR Status.flag = 1; Status.y = 6; EE445L Spring 2018 Quiz 1A Page 1 of 6 Jonathan W. Valvano First: Last: March 1, 2018, 3:30pm-4:45pm. This is a closed book exam, with one 8.5 by 11-inch crib sheet. You have 75 minutes, so please allocate

More information

EE251: Thursday September 20

EE251: Thursday September 20 EE251: Thursday September 20 Parallel I/O aka General Purpose I/O aka GPIO Common Devices: Switches, LEDs, Keypads Read Lab 4 carefully, and Chapter 14 in text Think about what you would like to review

More information

ARM PROGRAMMING. When use assembly

ARM PROGRAMMING. When use assembly ARM PROGRAMMING Bùi Quốc Bảo When use assembly Functions that cannot be implemented in C, such as special register accesses and exclusive accesses Timing-critical routines Tight memory requirements, causing

More information

EE251: Tuesday September 5

EE251: Tuesday September 5 EE251: Tuesday September 5 Shift/Rotate Instructions Bitwise logic and Saturating Instructions A Few Math Programming Examples ARM Assembly Language and Assembler Assembly Process Assembly Structure Assembler

More information

COEN-4720 Embedded Systems Design Lecture 4 Interrupts (Part 1) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University

COEN-4720 Embedded Systems Design Lecture 4 Interrupts (Part 1) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University COEN-4720 Embedded Systems Design Lecture 4 Interrupts (Part 1) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University Outline Introduction NVIC and Interrupt Control Interrupt

More information

University of Texas at Austin Electrical and Computer Engineering Department. EE319K, Embedded Systems, Spring 2013 Final Exam

University of Texas at Austin Electrical and Computer Engineering Department. EE319K, Embedded Systems, Spring 2013 Final Exam University of Texas at Austin Electrical and Computer Engineering Department EE319K, Embedded Systems, Spring 2013 Final Exam Directions There are 6 problems worth a total of 100 points. The number of

More information

Parallel I/O and Keyboard Scanning

Parallel I/O and Keyboard Scanning 4 4.1 Objectives: Microprocessors can monitor the outside world using input ports. They can also control it using output ports. The TM4C123G (Tiva) performs I/O using 6 ports. Computer keyboards are typically

More information

ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview

ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview M J Brockway January 25, 2016 UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All

More information

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: Interrupt Handling Module No: CS/ES/13 Quadrant 1 e-text 1. Interrupt An interrupt is the occurrence of a condition--an event --

More information

Exam 1 Fun Times. EE319K Fall 2012 Exam 1A Modified Page 1. Date: October 5, Printed Name:

Exam 1 Fun Times. EE319K Fall 2012 Exam 1A Modified Page 1. Date: October 5, Printed Name: EE319K Fall 2012 Exam 1A Modified Page 1 Exam 1 Fun Times Date: October 5, 2012 Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will

More information

Assembly Language Programming

Assembly Language Programming Experiment 3 Assembly Language Programming Every computer, no matter how simple or complex, has a microprocessor that manages the computer s arithmetical, logical and control activities. A computer program

More information

The ARM Cortex-M0 Processor Architecture Part-1

The ARM Cortex-M0 Processor Architecture Part-1 The ARM Cortex-M0 Processor Architecture Part-1 1 Module Syllabus ARM Architectures and Processors What is ARM Architecture ARM Processors Families ARM Cortex-M Series Family Cortex-M0 Processor ARM Processor

More information

The ARM Cortex-M0 Processor Architecture Part-2

The ARM Cortex-M0 Processor Architecture Part-2 The ARM Cortex-M0 Processor Architecture Part-2 1 Module Syllabus ARM Cortex-M0 Processor Instruction Set ARM and Thumb Instruction Set Cortex-M0 Instruction Set Data Accessing Instructions Arithmetic

More information

ELC4438: Embedded System Design ARM Cortex-M Architecture II

ELC4438: Embedded System Design ARM Cortex-M Architecture II ELC4438: Embedded System Design ARM Cortex-M Architecture II Liang Dong Electrical and Computer Engineering Baylor University Memory system The memory systems in microcontrollers often contain two or more

More information

LDR R0,=0x L: LDREX R1, [R0] ORR R1, #4 STR R1, [R0] (5) Part a) Why does the 9S12 code not have a critical section?

LDR R0,=0x L: LDREX R1, [R0] ORR R1, #4 STR R1, [R0] (5) Part a) Why does the 9S12 code not have a critical section? EE445M/EE380L Quiz 1 Spring 2017 Solution Page 1 of 5 First Name: Last Name: March 3, 2017, 10:00 to 10:50am Open book and open notes. No calculators or any electronic devices (turn cell phones off). Please

More information

Exam 1. Date: February 23, 2016

Exam 1. Date: February 23, 2016 Exam 1 Date: February 23, 2016 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:

More information

Advanced Assembly, Branching, and Monitor Utilities

Advanced Assembly, Branching, and Monitor Utilities 2 Advanced Assembly, Branching, and Monitor Utilities 2.1 Objectives: There are several different ways for an instruction to form effective addresses to acquire data, called addressing modes. One of these

More information

Multitasking on Cortex-M(0) class MCU A deepdive into the Chromium-EC scheduler

Multitasking on Cortex-M(0) class MCU A deepdive into the Chromium-EC scheduler Multitasking on Cortex-M(0) class MCU A deepdive into the Chromium-EC scheduler $whoami Embedded Software Engineer at National Instruments We just finished our first product using Chromium-EC and future

More information

EE445L Fall 2014 Final Version A Page 1 of 7

EE445L Fall 2014 Final Version A Page 1 of 7 EE445L Fall 2014 Final Version A Page 1 of 7 Jonathan W. Valvano First: Last: This is the closed book section. You must put your answers in the boxes. When you are done, you turn in the closed-book part

More information

ECE 362 Experiment 4: Interrupts

ECE 362 Experiment 4: Interrupts ECE 362 Experiment 4: Interrupts 1.0 Introduction Microprocessors consistently follow a straight sequence of instructions, and you have likely only worked with this kind of programming until now. In this

More information

Exam 1. Date: Oct 4, 2018

Exam 1. Date: Oct 4, 2018 Exam 1 Date: Oct 4, 2018 UT EID: Professor: Valvano Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat

More information

Real Time Operating Systems

Real Time Operating Systems Real Time Operating Systems Terminology uc/os-iii, The Real-Time Kernel, or a High Performance, Scalable, ROMable, Preemptive, Multitasking Kernel for Microprocessors, Microcontrollers & DSPs, Book & Board

More information

EE251: Thursday November 30

EE251: Thursday November 30 EE251: Thursday November 30 Course Evaluation Forms-fill out Memory Subsystem continued Timing requirements Adding memory beyond 4 Gbyte Time Allowing: Begin Review for Final Exam Homework due next Tuesday,

More information

Forth and C on the Cortex-M3. Saturday, April 28, 12

Forth and C on the Cortex-M3. Saturday, April 28, 12 Forth and C on the Cortex-M3 Arm Cortex-M3! 32-Bit Architecture Low-latency Prioritized Interrupt controller - NVIC Single-Cycle Multiply Sophisticated Debug C and Assembly friendly Common across all major

More information

ECE251: Intro to Microprocessors Name: Solutions Mid Term Exam October 4, 2018

ECE251: Intro to Microprocessors Name: Solutions Mid Term Exam October 4, 2018 ECE251: Intro to Microprocessors Name: Solutions Mid Term Exam October 4, 2018 (PRINT) Instructions: No calculators, books, or cell phones; do not communicate with any other student. One side of a single

More information

(2) Part a) Registers (e.g., R0, R1, themselves). other Registers do not exists at any address in the memory map

(2) Part a) Registers (e.g., R0, R1, themselves). other Registers do not exists at any address in the memory map (14) Question 1. For each of the following components, decide where to place it within the memory map of the microcontroller. Multiple choice select: RAM, ROM, or other. Select other if the component is

More information

EE251: Tuesday December 4

EE251: Tuesday December 4 EE251: Tuesday December 4 Memory Subsystem continued Timing requirements Adding memory beyond 4 Gbyte Time Allowing: Begin Review for Final Exam Homework #9 due Thursday at beginning of class Friday is

More information

Lab 4 Interrupt-driven operations

Lab 4 Interrupt-driven operations Lab 4 Interrupt-driven operations Interrupt handling in Cortex-M CPUs Nested Vectored Interrupt Controller (NVIC) Externally-triggered interrupts via GPIO pins Software setup for interrupt-driven applications

More information

Interrupts and Low Power Features

Interrupts and Low Power Features ARM University Program 1 Copyright ARM Ltd 2013 Interrupts and Low Power Features Module Syllabus Interrupts What are interrupts? Why use interrupts? Interrupts Entering an Exception Handler Exiting an

More information

Bonus Lecture: Fibonacci

Bonus Lecture: Fibonacci Bonus Lecture: Fibonacci ECE 362 https://engineering.purdue.edu/ee362/ Rick Reading You could try looking up recurisve function in your textbook. Recursive Fibonacci if (x < 2) return fibonacci(x 1) +

More information

Cortex-M4 Processor Overview. with ARM Processors and Architectures

Cortex-M4 Processor Overview. with ARM Processors and Architectures Cortex-M4 Processor Overview with ARM Processors and Architectures 1 Introduction 2 ARM ARM was developed at Acorn Computer Limited of Cambridge, UK (between 1983 & 1985) RISC concept introduced in 1980

More information

EE445L Fall 2014 Final Version A solution Page 1 of 7

EE445L Fall 2014 Final Version A solution Page 1 of 7 EE445L Fall 2014 Final Version A solution Page 1 of 7 Jonathan W. Valvano Solution This is the closed book section. You must put your answers in the boxes. When you are done, you turn in the closed-book

More information

E85 Lab 8: Assembly Language

E85 Lab 8: Assembly Language E85 Lab 8: Assembly Language E85 Spring 2016 Due: 4/6/16 Overview: This lab is focused on assembly programming. Assembly language serves as a bridge between the machine code we will need to understand

More information

ARM Cortex-M4 Architecture and Instruction Set 3: Branching; Data definition and memory access instructions

ARM Cortex-M4 Architecture and Instruction Set 3: Branching; Data definition and memory access instructions ARM Cortex-M4 Architecture and Instruction Set 3: Branching; Data definition and memory access instructions M J Brockway February 17, 2016 Branching To do anything other than run a fixed sequence of instructions,

More information

Module 3. Embedded Systems I/O. Version 2 EE IIT, Kharagpur 1

Module 3. Embedded Systems I/O. Version 2 EE IIT, Kharagpur 1 Module 3 Embedded Systems I/O Version 2 EE IIT, Kharagpur 1 Lesson 15 Interrupts Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would learn Interrupts

More information

EE445M/EE380L.6, Lecture 1 1/28/2015. EE445M/EE360L.6 Embedded and Real-Time Systems/ Real-Time Operating Systems. Lecture 1

EE445M/EE380L.6, Lecture 1 1/28/2015. EE445M/EE360L.6 Embedded and Real-Time Systems/ Real-Time Operating Systems. Lecture 1 , 1/28/2015 EE445M/EE360L.6 Embedded and Real-Time Systems/ Real-Time Operating Systems : Introduction, TM4C123 Microcontroller, ARM Cortex-M 1 Class Setup Class web page http://www.ece.utexas.edu/~gerstl/ee445m_s15

More information

EE319K Fall 2013 Exam 1B Modified Page 1. Exam 1. Date: October 3, 2013

EE319K Fall 2013 Exam 1B Modified Page 1. Exam 1. Date: October 3, 2013 EE319K Fall 2013 Exam 1B Modified Page 1 Exam 1 Date: October 3, 2013 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will

More information

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss

Grundlagen Microcontroller Interrupts. Günther Gridling Bettina Weiss Grundlagen Microcontroller Interrupts Günther Gridling Bettina Weiss 1 Interrupts Lecture Overview Definition Sources ISR Priorities & Nesting 2 Definition Interrupt: reaction to (asynchronous) external

More information

Chapter 2. Overview of Architecture and Microcontroller-Resources

Chapter 2. Overview of Architecture and Microcontroller-Resources Chapter 2 Overview of Architecture and Microcontroller-Resources Lesson 4 Timers, Real Time Clock Interrupts and Watchdog Timer 2 Microcontroller-resources Port P1 Port P0 Port P2 PWM Timers Internal Program

More information

EE319K Spring 2016 Exam 1 Solution Page 1. Exam 1. Date: Feb 25, UT EID: Solution Professor (circle): Janapa Reddi, Tiwari, Valvano, Yerraballi

EE319K Spring 2016 Exam 1 Solution Page 1. Exam 1. Date: Feb 25, UT EID: Solution Professor (circle): Janapa Reddi, Tiwari, Valvano, Yerraballi EE319K Spring 2016 Exam 1 Solution Page 1 Exam 1 Date: Feb 25, 2016 UT EID: Solution Professor (circle): Janapa Reddi, Tiwari, Valvano, Yerraballi Printed Name: Last, First Your signature is your promise

More information

Embedded assembly is more useful. Embedded assembly places an assembly function inside a C program and can be used with the ARM Cortex M0 processor.

Embedded assembly is more useful. Embedded assembly places an assembly function inside a C program and can be used with the ARM Cortex M0 processor. EE 354 Fall 2015 ARM Lecture 4 Assembly Language, Floating Point, PWM The ARM Cortex M0 processor supports only the thumb2 assembly language instruction set. This instruction set consists of fifty 16-bit

More information

ARM Architecture and Assembly Programming Intro

ARM Architecture and Assembly Programming Intro ARM Architecture and Assembly Programming Intro Instructors: Dr. Phillip Jones http://class.ece.iastate.edu/cpre288 1 Announcements HW9: Due Sunday 11/5 (midnight) Lab 9: object detection lab Give TAs

More information

Program SoC using C Language

Program SoC using C Language Program SoC using C Language 1 Module Overview General understanding of C, program compilation, program image, data storage, data type, and how to access peripherals using C language; Program SoC using

More information

Lab 2 Part 3 Assembly Language Programming and 9S12 Ports

Lab 2 Part 3 Assembly Language Programming and 9S12 Ports Lab 2 Part 3 Assembly Language Programming and 9S12 Ports Introduction and Objectives In this week s lab you will write an assembly language program to display various patterns on the eight individual

More information

ARM Cortex-M4 Architecture and Instruction Set 4: The Stack and subroutines

ARM Cortex-M4 Architecture and Instruction Set 4: The Stack and subroutines ARM Cortex-M4 Architecture and Instruction Set 4: The Stack and subroutines M J Brockway February 13, 2016 The Cortex-M4 Stack SP The subroutine stack is full, descending It grows downwards from higher

More information

ARM Cortex-M4 Programming Model

ARM Cortex-M4 Programming Model ARM Cortex-M4 Programming Model ARM = Advanced RISC Machines, Ltd. ARM licenses IP to other companies (ARM does not fabricate chips) 2005: ARM had 75% of embedded RISC market, with 2.5 billion processors

More information

introduction to interrupts

introduction to interrupts introduction to interrupts Geoffrey Brown Chris Haynes Bryce Himebaugh C335 Fall 2013 Overview Why interrupts? Basic interrupt processing Sources of interrupts Handling interrupts Issues with interrupt

More information

8051 Microcontroller

8051 Microcontroller 8051 Microcontroller 1 Salient Features (1). 8 bit microcontroller originally developed by Intel in 1980. (2). High-performance CMOS Technology. (3). Contains Total 40 pins. (4). Address bus is of 16 bit

More information

How to use imxrt Low Power feature

How to use imxrt Low Power feature NXP Semiconductors Document Number: AN12085 Application Note Rev. 0, 11/2017 How to use imxrt Low Power feature 1. Introduction This document discusses about low power application design and power consumption

More information

8051 Microcontrollers

8051 Microcontrollers 8051 Microcontrollers Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu March 8, 2016 Controller vs Processor Controller vs Processor Introduction to 8051 Micro-controller In 1981,Intel corporation

More information

ECE 598 Advanced Operating Systems Lecture 8

ECE 598 Advanced Operating Systems Lecture 8 ECE 598 Advanced Operating Systems Lecture 8 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 15 February 2018 Homework #3 Due. Announcements Homework #4 Posted Soon 1 (Review)

More information

EE 354 Fall 2015 Lecture 1 Architecture and Introduction

EE 354 Fall 2015 Lecture 1 Architecture and Introduction EE 354 Fall 2015 Lecture 1 Architecture and Introduction Note: Much of these notes are taken from the book: The definitive Guide to ARM Cortex M3 and Cortex M4 Processors by Joseph Yiu, third edition,

More information

These three counters can be programmed for either binary or BCD count.

These three counters can be programmed for either binary or BCD count. S5 KTU 1 PROGRAMMABLE TIMER 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to perform timing and counting functions using three 16-bit registers.

More information

AN10254 Philips ARM LPC microcontroller family

AN10254 Philips ARM LPC microcontroller family Rev. 02 25 October 2004 Application note Document information Info Content Keywords ARM LPC, Timer 1 Abstract Simple interrupt handling using Timer 1 peripheral on the ARM LPC device is shown in this application

More information

Exam 1. Date: February 23, 2018

Exam 1. Date: February 23, 2018 Exam 1 Date: February 23, 2018 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:

More information

Exam 1. Date: March 1, 2019

Exam 1. Date: March 1, 2019 Exam 1 Date: March 1, 2019 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam: Signature:

More information

Introduction to C. Write a main() function that swaps the contents of two integer variables x and y.

Introduction to C. Write a main() function that swaps the contents of two integer variables x and y. Introduction to C Write a main() function that swaps the contents of two integer variables x and y. void main(void){ int a = 10; int b = 20; a = b; b = a; } 1 Introduction to C Write a main() function

More information

ECE251: Tuesday September 11

ECE251: Tuesday September 11 ECE251: Tuesday September 11 Finish Branch related instructions Stack Subroutines Note: Lab 3 is a 2 week lab, starting this week and covers the Stack and Subroutines. Labs: Lab #2 is due this week. Lab

More information

EE319K Spring 2015 Exam 1 Page 1. Exam 1. Date: Feb 26, 2015

EE319K Spring 2015 Exam 1 Page 1. Exam 1. Date: Feb 26, 2015 EE319K Spring 2015 Exam 1 Page 1 Exam 1 Date: Feb 26, 2015 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help

More information

Interrupt/Timer/DMA 1

Interrupt/Timer/DMA 1 Interrupt/Timer/DMA 1 Exception An exception is any condition that needs to halt normal execution of the instructions Examples - Reset - HWI - SWI 2 Interrupt Hardware interrupt Software interrupt Trap

More information

Microprocessors B (17.384) Spring Lecture Outline

Microprocessors B (17.384) Spring Lecture Outline Microprocessors B (17.384) Spring 2013 Lecture Outline Class # 04 February 12, 2013 Dohn Bowden 1 Today s Lecture Administrative Microcontroller Hardware and/or Interface Programming/Software Lab Homework

More information

Microprocessors & Interfacing

Microprocessors & Interfacing Lecture Overview Microprocessors & Interfacing Interrupts (I) Lecturer : Dr. Annie Guo Introduction to Interrupts Interrupt system specifications Multiple sources of interrupts Interrupt priorities Interrupts

More information

8051 Microcontroller Interrupts

8051 Microcontroller Interrupts 8051 Microcontroller Interrupts There are five interrupt sources for the 8051, which means that they can recognize 5 different events that can interrupt regular program execution. Each interrupt can be

More information

Exam 1. Date: February 23, 2018

Exam 1. Date: February 23, 2018 Exam 1 Date: February 23, 2018 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:

More information

Embedded System Design

Embedded System Design ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH TRƯỜNG ĐẠI HỌC BÁCH KHOA KHOA ĐIỆN-ĐIỆN TỬ BỘ MÔN KỸ THUẬT ĐIỆN TỬ Embedded System Design Chapter 2: Microcontroller Series (Part 1) 1. Introduction to ARM processors 2.

More information

C Language Programming, Interrupts and Timer Hardware

C Language Programming, Interrupts and Timer Hardware C Language Programming, Interrupts and Timer Hardware In this sequence of three labs, you will learn how to write simple C language programs for the MC9S12 microcontroller, and how to use interrupts and

More information

ECE251: Tuesday September 12

ECE251: Tuesday September 12 ECE251: Tuesday September 12 Finish Branch related instructions Stack Subroutines Note: Lab 3 is a 2 week lab, starting this week and covers the Stack and Subroutines. Labs: Lab #2 is due this week. Lab

More information

AVR XMEGA Product Line Introduction AVR XMEGA TM. Product Introduction.

AVR XMEGA Product Line Introduction AVR XMEGA TM. Product Introduction. AVR XMEGA TM Product Introduction 32-bit AVR UC3 AVR Flash Microcontrollers The highest performance AVR in the world 8/16-bit AVR XMEGA Peripheral Performance 8-bit megaavr The world s most successful

More information

EE319K Exam 1 Summer 2014 Page 1. Exam 1. Date: July 9, Printed Name:

EE319K Exam 1 Summer 2014 Page 1. Exam 1. Date: July 9, Printed Name: EE319K Exam 1 Summer 2014 Page 1 Exam 1 Date: July 9, 2014 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help

More information

OUTLINE. STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and Pipelining Cortex-M0 Programming Model Toolchain and Project Structure

OUTLINE. STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and Pipelining Cortex-M0 Programming Model Toolchain and Project Structure ARCHITECTURE AND PROGRAMMING George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners OUTLINE STM32F0 Architecture Overview STM32F0 Core Motivation for RISC and

More information

ARM Cortex core microcontrollers

ARM Cortex core microcontrollers ARM Cortex core microcontrollers 2 nd Cortex-M3 core Balázs Scherer Budapest University of Technology and Economics Department of Measurement and Information Systems BME-MIT 2016 The Cortex-M3 core BME-MIT

More information

A block of memory (FlashROM) starts at address 0x and it is 256 KB long. What is the last address in the block?

A block of memory (FlashROM) starts at address 0x and it is 256 KB long. What is the last address in the block? A block of memory (FlashROM) starts at address 0x00000000 and it is 256 KB long. What is the last address in the block? 1 A block of memory (FlashROM) starts at address 0x00000000 and it is 256 KB long.

More information

The University of Texas at Arlington Lecture 21_Review

The University of Texas at Arlington Lecture 21_Review The University of Texas at Arlington Lecture 21_Review CSE 5442/3442 Agenda Tuesday December 1st Hand back Homework 7,8 and 9. Go over questions and answers Exam 3 Review Note: There will be a take home

More information

Interrupts (Exceptions) Gary J. Minden September 11, 2014

Interrupts (Exceptions) Gary J. Minden September 11, 2014 Interrupts (Exceptions) Gary J. Minden September 11, 2014 1 Interrupts Motivation Implementation Material from Stellaris LM3S1968 Micro-controller Datasheet Sections 2.5 and 2.6 2 Motivation Our current

More information

Chapters 5. Load & Store. Embedded Systems with ARM Cortex-M. Updated: Thursday, March 1, 2018

Chapters 5. Load & Store. Embedded Systems with ARM Cortex-M. Updated: Thursday, March 1, 2018 Chapters 5 Load & Store Embedded Systems with ARM Cortex-M Updated: Thursday, March 1, 2018 Overview: Part I Machine Codes Branches and Offsets Subroutine Time Delay 2 32-Bit ARM Vs. 16/32-Bit THUMB2 Assembly

More information

ERRATA SHEET INTEGRATED CIRCUITS. Date: July 9, 2007 Document Release: Version 1.6 Device Affected: LPC2148

ERRATA SHEET INTEGRATED CIRCUITS. Date: July 9, 2007 Document Release: Version 1.6 Device Affected: LPC2148 INTEGRATED CIRCUITS ERRATA SHEET Date: July 9, 2007 Document Release: Version 1.6 Device Affected: LPC2148 This errata sheet describes both the functional deviations and any deviations from the electrical

More information

Chapter 3 BRANCH, CALL, AND TIME DELAY LOOP

Chapter 3 BRANCH, CALL, AND TIME DELAY LOOP Islamic University Gaza Engineering Faculty Department of Computer Engineering ECOM 3022: Embedded Systems Discussion Chapter 3 BRANCH, CALL, AND TIME DELAY LOOP Eng. Eman R. Habib February, 2014 2 Embedded

More information

Interrupts and Exceptions

Interrupts and Exceptions Interrupts and Exceptions ECE 362 https://engineering.purdue.edu/ee362/ Rick Reading assignment: Reading Assignment STM32F0x1 Family Reference, Chapter 12, pages 217 228, "Interrupts and events" Your textbook,

More information

Exam 1. Date: March 1, 2019

Exam 1. Date: March 1, 2019 Exam 1 Date: March 1, 2019 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam: Signature:

More information

EECS 373 Fall 2018 Homework #3

EECS 373 Fall 2018 Homework #3 EECS 373 Fall 2018 Homework #3 Answers 1) Loaders, Linkers and Executables a) In straightforward English, explain the role of a linker. [7 points] A linker receives object files as input and must emit

More information

Interrupts (Exceptions) (From LM3S1968) Gary J. Minden August 29, 2016

Interrupts (Exceptions) (From LM3S1968) Gary J. Minden August 29, 2016 Interrupts (Exceptions) (From LM3S1968) Gary J. Minden August 29, 2016 1 Interrupts Motivation Implementation Material from Stellaris LM3S1968 Micro-controller Datasheet Sections 2.5 and 2.6 2 Motivation

More information

Timers and Counters. LISHA/UFSC Prof. Dr. Antônio Augusto Fröhlich Fauze Valério Polpeta Lucas Francisco Wanner.

Timers and Counters. LISHA/UFSC Prof. Dr. Antônio Augusto Fröhlich Fauze Valério Polpeta Lucas Francisco Wanner. Timers and Counters LISHA/UFSC Prof. Dr. Antônio Augusto Fröhlich Fauze Valério Polpeta Lucas Francisco Wanner http://www.lisha.ufsc.br/~guto March 2009 March 2009 http://www.lisha.ufsc.br/ 103 Timers

More information

Final Exam. Date: May 14, Printed Name:

Final Exam. Date: May 14, Printed Name: EE319K Spring 2015 Final Exam Page 1 Final Exam Date: May 14, 2015 UT EID: Circle one: MT, NT, JV, RY, VJR Printed Name: Last, First Your signature is your promise that you have not cheated and will not

More information

Final Exam. Date: May 12, 2017

Final Exam. Date: May 12, 2017 Final Exam Date: May 12, 2017 UT EID: Printed Name: Last, First Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam:

More information

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1

Interrupts (I) Lecturer: Sri Notes by Annie Guo. Week8 1 Interrupts (I) Lecturer: Sri Notes by Annie Guo Week8 1 Lecture overview Introduction to Interrupts Interrupt system specifications Multiple Sources of Interrupts Interrupt Priorities Interrupts in AVR

More information

Systems Architecture The ARM Processor

Systems Architecture The ARM Processor Systems Architecture The ARM Processor The ARM Processor p. 1/14 The ARM Processor ARM: Advanced RISC Machine First developed in 1983 by Acorn Computers ARM Ltd was formed in 1988 to continue development

More information

ARM Cortex-M0 DesignStart Processor and v6-m Architecture. Joe Bungo ARM University Program Manager Americas/Europe R&D Division

ARM Cortex-M0 DesignStart Processor and v6-m Architecture. Joe Bungo ARM University Program Manager Americas/Europe R&D Division ARM Cortex-M0 DesignStart Processor and v6-m Architecture Joe Bungo ARM University Program Manager Americas/Europe R&D Division 1 2 Agenda Introduction to ARM Ltd Cortex-M0 DesignStart Processor ARM v6-m

More information