ME 4447/6405. Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics. Instructor: Professor Charles Ume LECTURE 6

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1 ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume LECTURE 6

3 MC9S12C Microcontroller Covered in Lecture 5: Quick Introduction to Microcontroller Subsystems Microcontroller Registers Microcontroller Modes (Single chip, Extended, etc..) EVBU Memory Maps Covered in this section: HCS12 CPU (Note: the Central Processing Unit (CPU) is the core of the microcontroller where instructions are executed)

4 The HCS12 CPU contains: Circuits to process instructions CPU Registers (Note: HCS12 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations)

5 Accumulators A, B, and D A & B are: 8-bit registers Can be used for 8-bit math operations ( Note: This is why A & B are called Accumulators ) Can also be used for 8-bit binary logic, comparisons, memory transfers, etc Can be used for accumulator offsets in indexed addressing D is: 16-bit register Cannot be used when A or B is in use Can be used for 16-bit math in conjunction with Index X & Y Can be used for 16-bit memory transfers, comparisons, etc.. Can be used for accumulator offsets in indexed addressing Index Registers X & Y Can be used for 16-bit math with Accumulator D Mainly used for addressing memory in Indexed mode (Note: Indexed addressing mode will be covered in a later section) Program Counter (PC) Contains the address of the next instruction to be executed Can be used as index register in indexed addressing Stack Pointer (SP) Contains the address of the last stack location used (1 greater than the George currently W. available Woodruff location) School of Mechanical Engineering, Georgia Tech Can be used as index register in indexed addressing

6 HCS12 CPU STACK POINTER An interrupt can be recognized at any time after it is enabled by its local mask, if any, and by the global mask bit in the CCR. Once an interrupt source is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the current instruction. When the CPU begins to service an interrupt, the contents of the CPU registers are pushed onto the stack in the order shown above (see also p. 2 of the CPU12 reference guide). After the CCR value is stacked, the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The interrupt vector for the highest priority pending source is fetched and execution continues at the address specified by the vector. At the end of the interrupt service routine, the return-frominterrupt instruction is executed and the saved registers are pulled from the stack in reverse order George so W. that Woodruff normal School program of Mechanical execution Engineering, can resume. Georgia Tech

7 RTI: At the end of an interrupt service routine, the user writes a Return from Interrupt (RTI) instruction. This causes the CPU registers and the return address to be pulled from the stack, permitting main program execution to continue where it left off with the same values in the CPU registers as before the interrupt occured. LEGEND: RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN ROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTN HI = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTN LO = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS X,Y HI = MOST SIGNIFICANT BYTE OF X OR Y INDEX REGISTER X,Y LO = LEAST SIGNIFICANT BYTE OF X OR Y INDEX REGISTER

JSR or BSR: RTS: Execution of Jump To Subroutine (JSR) and Branch To Subroutine (BSR) instructions causes the contents of the program counter to be pushed onto the stack.

8 JSR or BSR: RTS: Execution of Jump To Subroutine (JSR) and Branch To Subroutine (BSR) instructions causes the contents of the program counter to be pushed onto the stack. At the end of the subroutine, the user writes a Return from Subroutine (RTS) instruction. This causes the return address to be pulled from the stack, permitting execution to continue after the JSR or BSR instruction LEGEND: RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN ROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTN HI = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTN LO = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS

9 MC9S12C CONDITION CODE REGISTER S X H I N Z V C MASKING BITS S Disables STOP instruction when set. X Masks XIRQ Request when set. set by hardware reset, cleared by software set by unmasked XIRQ See page 116 of Technical Data ARITHMETIC BITS Reflect results of instruction execution C Carry/Borrow from MSB unsigned arithmetic V 2 s complement overflow indication signed arithmetic I Masks interrupt request from all IRQ level sources (both external and internal) when set. set by unmasked I level request or unmasked XIRQ See page 116 of Technical Data Z Zero result N Negative (follows MSBit of result) H Half Carry from bit 3 to bit 4 ADD operations only George W. Woodruff School of Mechanical Engineering, Georgia Tech H will be set to 1

10 Example 3 from Lecture 4: = = = = 1 s comp. of = 2 s comp. of V bit will be set. C bit will be set = 5A 16 = = 1 s comp. of 5A = 2 s comp. of 5A = (2 s comp. of ) = (2 s comp. of 5A 16 ) = =

11 QUESTIONS???

Chapter 7 Central Processor Unit (S08CPUV2)

Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more