HMS30C7110. uclinux Developer Guide. Multipurpose Network Processor. Interrupt Controller Guide. MagnaChip Semiconductor Ltd. Version 0.

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1 Multipurpose Network Processor uclinux Developer Guide Interrupt Controller Guide Version 0.1 MagnaChip Semiconductor Ltd.

2 Copyright MagnaChip Semiconductor Ltd. - ii -

3 ALL RIGHTS RESERVED. No part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without the prior written permission of MagnaChip Semiconductor Ltd. MagnaChip Semiconductor Ltd. #1, Hyangjeong-dong, Heungduk-gu, Cheongju-si, Chungcheongbuk-do, Republic of Korea Homepage: Technical Support Homepage: H.Q. of MagnaChip Semiconductor Inc. Marketing Site Sales in Korea Telephone: 82-(0) Telephone: 82-(0) Telephone: 82-(0) Facsimile: 82-(0) Facsimile: 82-(0) Facsimile: 82-(0) World Wide Sales Network U.S.A. Taiwan U.K. Telephone: Telephone: 886-(0) Telephone: 44-(0) Facsimile: Facsimile: 886-(0) Facsimile: 44-(0) HMS30C7110 uclinux development Docu for IRQ, ver1.0 - iii -

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5 TABLE OF CONTENTS 1 OVERVIEW INTERRUPT PROCESSING UCLINUX INTERRUPT PROCESSING INTERRUPT SUPPORTS IN ARM ARCHITECTURE HMS30C7110 INTERRUPT CONTROLLER INTERRUPT HANDLING INSTALL ARM EXCEPTION VECTORS FIRST IRQ HANDLER MODE DEPENDENT IRQ HANDLER DETERMINE WHAT INTERRUPT SHOULD BE PROCESSED HIGH-LEVEL INTERRUPT HANDLER INTERRUPT INITIALIZING MISCELLANEOUS diable_fiq Macro Interrupt definitions

6 1 Overview This document describes how the interrupt controller in HMS30C7110 working with uclinux. Interrupt mechanism has strong relationship with processor architecture as well as interrupt controller. uclinux has general interrupt handling mechanism for many processor and with our platform ARM architecture version will be used. We briefly introduce interrupt processing and then explain how HMS30C7110 works. This document will cover, uclinux interrupt processing mechanism Interrupt supports in ARM architecture HMS30C7110 Interrupt Controller features HMS30C7110 Interrupt Controller driver 2-2 -

7 2 Interrupt Processing In this section, we briefly describes how uclinux process interrupts and how interrupt is supported in ARM architecture. For more detail, see ARM architecture reference and ucinux/linux documents. 2.1 uclinux Interrupt Processing uclinux has abstracted high-level interrupt handler function which process general device interrupts. Even though interrupt processing defers from architecture to architecture, common interrupt processing function do_irq() exists in arch/{architecture}/irq.c. i.e. for ARM without MMU, in uclinux-dist/linux- 2.4.x/arch/armnommu/irq.c. In this function, registered device specific interrupt handlers are called. uclinux interrupt processing supports chained interrupt (several device shares the same interrupt) so that every chained interrupt handlers called in order and a handler should determine that the interrupt is really happens on the device which the handler have interest in. Also, do_irq does call soft irq handler and supports bottom halves. For more about linux interrupts see other linux references. 2.2 Interrupt supports in ARM architecture As mentioned, interrupt processing has strongly related with processor architecture. In ARM core, very simple model of interrupt is supported. ARM has two level of interrupts IRQ and FIQ. IRQ supports normal interrupt handling and FIQ is designed for fast interrupt handling. But, uclinux does utilize only one kind of interrupt IRQ. It provide unified path of interrupt handling to reduce complexity. Just about you concerning is IRQ. 2.3 HMS30C7110 Interrupt Controller <This section will be filled later. Refer HMS30C7110 user guide until then > 3-3 -

8 3 Interrupt Handling In this captor, we describe the real interrupt handling how interrupt is handled by what code and what to do with HMS30C7110. Most of code are exists in uclinux. What we wrote for HMS30C7110 will be marked as RED. The points you should see carefully marked as BLUE. 3.1 Install ARM Exception Vectors ARM treats interrupt as a kind of exception and use vectors to handle exceptional case. uclinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.s Install exception vectors from trap_init subroutine call from high-level trap_init() function. What just we concern about is IRQ. Above code shows that when IRQ occurs, jump to vector_irq routine. ( real_stubs_start and strubs_start is a magic working for code relocation) 4-4 -

9 3.2 First IRQ Handler uclinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.s Different routines for processor modes is needed because there are some difference in register because ARM architecture has windowed register by mode. Interrupt only from USER mode and SVC mode are valid. Interrupt from other mode should not be occurred

10 3.3 Mode Dependent IRQ Handler uclinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.s As explained there are some difference in register due to register windows, two difference interrupt handler used to save context. You can see several difference in saving registers and returning from interrupt. Despite of difference, two routine commonly use get_irqnr_and_base macro and call do_irq(). 3.4 Determine what interrupt should be processed The macro get_irqnr_and_base determines what interrupt should be processed at this time and set flag if there is interrupt to be processed. Because every interrupt controller has different scheme to determine those thing, you should write it for HMS30C7110. HMS30C7110 interrupt controller have register indicating interrupt number to be processed (0 if there are no more interrupt to be processed), so that just read it and compare it 6-6 -

11 to 0 is OK. uclinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.s 7-7 -

12 3.5 High-level Interrupt Handler Rest of interrupt processing will be done at high-level (the functions written in C). The main handling function is do_irq(). Every interrupt to be processed is described by an interrupt descriptor which says how to process the device interrupt. The function do_irq() find interrupt descriptor from the irq number passed from low-level handler and do proper action. As you see in following code (not a full source code of do_irq() but extracted code to show what it does), one interrupt can have many actions and this enables chained interrupt feature. Before and after action, the proper masking and unmasking of interrupt, and locking mechanism for multiple processor architecture is added. HMS30C7110 needs to clear source pending bit in Interrupt Controller and let the controller knows interrupt is processed. (ACK to Interrupt). uclinux-dist/linux-2.4.x/arch/armnommu/kernel/irq.c 8-8 -

13 3.6 Interrupt Initializing Interrupt descriptor have major information how to handle interrupt. It should have proper value before any interrupt called. Handler and other functions are initialize when registering irq handler but several fields should be initialize by hand such as mask/unmask function. Interrupt controller should be initialized during initialization process also. uclinux-dist/linux-2.4.x/include/asm-armnommu/arch-hynix/irq.h 9-9 -

14 uclinux-dist/linux-2.4.x/arch/armnommu/mach-hynix/irq.c 3.7 Miscellaneous diable_fiq Macro For some platform utilizing FIQ, it s needed. But we don t need to implement it. Just adding empty macro to prevent compiler/link errors. uclinux-dist/linux-2.4.x/arch/armnommu/kernel/entry-armv.s

15 3.7.2 Interrupt definitions The number of interrupt in system and what interrupts is defined in header file. uclinux-dist/linux-2.4.x/include/asm-armnommu/arch-hynix/irqs.h