Dialog Power Tree solutions for Xilinx Zynq Ultrascale+ MPSoC
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1 Dialog Power Tree solutions for Xilinx Zynq Ultrascale+ MPSoC Jan 2017 personal portable connected
2 Dialog Power Solutions Dialog specializes in a range of flexible, OTP programmable PMIC products. At the heart of the Dialog PMIC family is the System PMIC Copyright 2016 Dialog Semiconductor. All Rights Reserved 2
3 Key blocks and features 6x 3 MHz buck converters with programmable current limits. 11x LDO linear regulators. 2x slew rate programmable rail switch controllers (with charge pump for drive voltage generation). Programmable power sequencer. Low quiescent current 32 khz crystal oscillator and RTC clock with alarm. Backup battery or super-cap charger with programmable voltage and current limit. 16x GPIO, some with dedicated alternative functionality. Can be controlled via 2-wire I 2 C or 4-wire SPI. 10bit multi-channel ADC. Voltage supervisory function able to monitor input and output voltages. Provides for a controlled shutdown in the event of brown-outs on input or output. Watchdog supervisor for automatic recovery from a system software crash. AEC-Q100 Grade3 Copyright 2016 Dialog Semiconductor. All Rights Reserved 3
4 Buck power supplies 6x high current bucks BuckCore1 and 2 are identical and can optionally be combined to provide a dual phase double current output (5 A total). BuckMem and BuckIO can optionally be combined to provide single phase double current ouput (3 A total). BuckPeri is designed to power higher voltage peripherals. BuckPro is similar but has the option to sink and source current in memory termination (VTT) mode. Each bucks has a pull-down resistor that can be configured to automatically turn on when the buck is disabled. All bucks can perform DVC ramping during output voltage changes. All bucks can be operated in: PWM mode for fixed frequency operation PFM mode for best efficiency at low load currents Auto mode for best efficiency across all load currents Copyright 2016 Dialog Semiconductor. All Rights Reserved 4
5 LDO power supplies & GPIO 11x LDOs LDO1 4 can perform DVC ramping during output voltage changes. LDO1 can optionally be set as always on. LDO3, 4, 7, 8 & 11 can be operated in an unregulated bypass mode. Allowing them to be used as sequenced rail switches. LDO6, 9 & 10 are designed to be very low noise output. 2x LDOs have 100mA load current capability 7x LDOs have 200mA load current capability 2x LDOs have 300mA load current capability GPIO 16 flexible GPIO 5 controllable via the sequencer for the control of sub PMICs Copyright 2016 Dialog Semiconductor. All Rights Reserved 5
6 DA921x Sub PMICs Powering the high current rails of SOC The DA921x family of sub PMIC s are designed to work alongside a System PMIC such as the The Sub-PMIC family consists of 6 members:. Device Current Phase DA A 4 DA A 4 DA9212 6A+6A 2,2 DA A 4 DA A +5A 3,1 DA A+10A 2,2 Combining these building blocks it is possible to address the power tree requirements for a wide range of systems such as the Xilinx Zynq Ultrascale+ MPSoc range. Copyright 2016 Dialog Semiconductor. All Rights Reserved 6
7 Automotive Solutions Many of the Dialog PMIC products are already automotive qualified to AECQ-100 grade 3 with further qualification to grade 2 in progress during DA2017. DA9062-A AECQ 100 grade 3 -A AECQ 100 grade 3, grade 2 qualification ongoing. DA9210-A AECQ 100 grade 3 DA9213-A AECQ 100 grade 2, 1H 2017 DA9214-A AECQ 100 grade 2, 1H 2017 This means that a common design can be ported between Automotive and Consumer/industrial applications with a fairly simple exchange of the passive components And by specifying the A PMIC part. Copyright 2016 Dialog Semiconductor. All Rights Reserved 7
8 Dialog Solutions for Xilinx ZUXX Family Power Scheme ZU19EG ZU9EG ZU9CG ZU7EG ZU5EG ZU3EG(1) ZU3EG(2) Always On: Cost optimized 2xDA9210, 2xDA9210, DA9213, DA9210, DA9210, DA9210, DA9062 Always On: Power/Efficiency optimized DA9213, * DA9213, * DA9214, DA9214, Always On: PL performance optimized 2xDA9210, 2xDA9210, DA9213, DA9210, DA9210, DA9210, DA9062 Full power management flexibility DA9215, * DA9213, * DA9213, DA9214, DA9214, * Additional single external regulator required Copyright 2016 Dialog Semiconductor. All Rights Reserved 8
9 ZU3CG Example Always On: Power/Efficiency optimized Based on the ZU3CG Requirements we can map all of the required rails for the Always On: Power/Efficiency optimized solution on to a single. This mapping still leaves 6 LDO s available for additional system requirements. The -EVAL8 evaluation kit is available to evaluate this configuration. Always On: Power/Efficiency optimized Dialog Mapping Power Possible Power Rail Regulator Consolidation Voltage Current Resource Current 1 VCCINT,VCCINT_IO, 0.85 VCCBRAM 4.6 Core1&2 5 2 VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR,, and 0.85 VCCINT_VCU 2.55 Pro VCC_PSAUX, VCC_PSADC(1), Required VCC_PSDDR_PLL(2),VCC 1.8 AUX, VCCAUX_IO, and VCCADC(1) 1.04 Peri VCCO_PSDDR USER 0.5 Mem VCC_PSPLL, VMGTAVTT (GTH), and VMGTYAVTT 1.2 (GTY) 0.1 LDO VCCO_PSIO[0:3] assuming all PS I/Os run from same USER voltage 0.3 LDO VPS_MGTRAVCC 0.3 LDO1& VPS_MGTRAVTT, User- VMGTVCCAUX (GTH), and 1.8 Defined VMGTYVCCAUX (GTY) 0.1 LDO VMGTAVCC (GTH) and 0.9 VMGTYAVCC (GTY) 0 10 Optional PL and PS I/O USER voltages 1 IO 1.5 Copyright 2016 Dialog Semiconductor. All Rights Reserved 9
10 ZU3CG Example Always On: Power/Efficiency optimized Copyright 2016 Dialog Semiconductor. All Rights Reserved 10
11 25mm ZU3CG: PCB area Note: in this layout the has input decoupling in the reverse side of the board. 26.7mm Copyright 2016 Dialog Semiconductor. All Rights Reserved 11
12 ZU3CG Example The -EVAL8 evaluation kit is available to evaluate this configuration. See the Dialog Website for further details of the and the evaluation boards. Ht Copyright 2016 Dialog Semiconductor. All Rights Reserved 12
13 ZU9EG Full power management flexibility To Support the Fully Flexible solution for the ZU9EG requires the use of a DA9213 to supply the high current VCCINT rail, along with the. In addition a single external regulator will be required for Reg 13. This can be scaled dependant on the end system requirements and utilisation of the Gigabit interfaces Full power management flexibility Dialog Mapping Power Possible Power Rail Regulator Consolidation Voltage Current Resource Current 1 VCC_PSINTLP Pro VCC_PSAUX, VCC_PSADC(1) LDO VCC_PSPLL, LDO VCCO_PSIO[0:3] assuming all PS I/Os run from same voltage USER 0.3 LDO VCC_PSINTFP, Required VCC_PSINTFP_DDR, Core VCC_PSDDR_PLL(2) LDO User- Defined Spare VCCO_PSDDR USER 0.5 Mem VCCINT, VCCINT_IO, VCCBRAM DA VCCAUX, VCCAUX_IO, and VCCADC(1) Peri VPS_MGTRAVCC LDO1& VPS_MGTRAVTT LDO VMGTAVTT (GTH), VMGTYAVTT (GTY), and VCC_VCU_PLL Core VMGTAVCC (GTH) and VMGTYAVCC (GTY) External 14 VMGTVCCAUX (GTH), and VMGTYVCCAUX (GTY) LDO Optional PL and PS I/O voltages USER 1.5 IO 1.5 LDO8,9,11 Copyright 2016 Dialog Semiconductor. All Rights Reserved 13
14 ZU9EG Full power management flexibility The provides control of both the DA9213 and the external regulator via its sequence-able GPIO. Currently in development is a Power Board for this solution. Schematics and BOM will be available during early Feb Layout will be available by the end of Feb and actual boards will be available during March. Copyright 2016 Dialog Semiconductor. All Rights Reserved 14
15 25mm 29mm ZU9EG ZU9EG solution : Automotive components DA9213 This layout example provides an indication of the area required for the ZU9 solution including the and the DA9213. This example uses Automotive qualified components, the overall area could be further optimised if consumer grade parts were used. Note: in this layout the has input decoupling in the reverse side of the board. 26.7mm 7mm Copyright 2016 Dialog Semiconductor. All Rights Reserved 15
16 ZU19EG Full power management flexibility The final example demonstrates how we can extend this flexible solution with the addition of a single external High current regulator to address the requirements of the ZU19. This solution uses a DA9215 to provide two 10A rails for regulators 12 & 13 along with a as the main system PMIC and the previously mentioned high current single regulator. Full power management flexibility Dialog Mapping Power Regulato r Possible Power Rail Consolidation Voltage Current Resource Current 1 VCC_PSINTLP Pro VCC_PSAUX, VCC_PSADC(1) LDO VCC_PSPLL, LDO VCCO_PSIO[0:3] assuming all PS I/Os run from same voltage USER 0.3 LDO Required 5 VCC_PSINTFP, VCC_PSINTFP_DDR, Core VCC_PSDDR_PLL(2) LDO User- Defined Spare VCCO_PSDDR USER 0.5 Mem VCCINT, VCCINT_IO, VCCBRAM External 9 VCCAUX, VCCAUX_IO, and VCCADC(1) Peri VPS_MGTRAVCC LDO1& VPS_MGTRAVTT LDO VMGTAVTT (GTH), VMGTYAVTT (GTY), and VCC_VCU_PLL DA VMGTAVCC (GTH) and VMGTYAVCC (GTY) DA VMGTVCCAUX (GTH), and VMGTYVCCAUX (GTY) LDO Optional PL and PS I/O voltages USER 1.5 IO 1.5 LDO8,9,11 Copyright 2016 Dialog Semiconductor. All Rights Reserved 16
17 ZU19EG Full power management flexibility Copyright 2016 Dialog Semiconductor. All Rights Reserved 17
18 More Information For More information about the range of Dialog Semiconductor PMICs and Sub-PMICs See the Dialog Website : Or Contact your local Dialog Field Applications team for direct support. Copyright 2016 Dialog Semiconductor. All Rights Reserved 18
19 Powering the Smart Connected Future personal portable connected Copyright 2016 Dialog Semiconductor. All Rights Reserved 19
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