XMC-SDR-A. XMC Zynq MPSoC + Dual ADRV9009 module. Preliminary Information Subject To Change. Overview. Key Features. Typical Applications
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1 Preliminary Information Subject To Change XMC-SDR-A XMC Zynq MPSoC + Dual ADRV9009 module Overview PanaTeQ s XMC-SDR-A is a XMC module based on the Zynq UltraScale+ MultiProcessor SoC device from Xilinx and two ADRV9009 RF Wideband Transceivers from Analog Devices for a broad range of applications such as Software Defined Radio, MILCOM, massive MIMO, Phase Array Radar and Electronic Warfare. It is HW/SW compatible with ADRV9009-ZU11EG RF SoM from Analog Devices. The baseband processor is a Zynq UltraScale+ MPSoC that integrates a Quad-core ARM Cortex-A53 based Application Processing Unit (APU), a Dual-core ARM Cortex-R5 based Real- Time Processing Unit (RPU), a ARM MALI-400 based Graphic Processing Unit (GPU), a Video CODEC H.264/H.265 (EV devices only) and an UltraScale+ Programmable Logic (PL) in a single device. It also includes on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The board can be ordered with different versions of the Zynq UltraScale+ MPSoC family of devices, coupled with up to 8GB 64- bit DDR Processing Memory with 8-bit ECC. Up to 4GB 32-bit of DDR is also available as the Programmable Logic Memory, allowing data streaming applications such as video CODEC and signal processing. 64GB of soldered managed NAND Flash is available for local data storage. The XMC-SDR-A provides a frond-end RF interface using 10 SSMC connectors. The board can act as a PrPMC in the system. When the XMC- SDR-A is System Controller.There is no need to add any SBC in the System, improving Size, Weight, Power and Cost (SWaP-C). A large number of the Zynq Ultrascale+ PS peripherals are available on the XMC connectors: 1x ETH 1000Base-T, 2x USB 3.0/2.0, 2x USB 2.0, 1x SATA 3.1, 2x CAN-2.0B, 2x RS-232/422/485, 4x MGT, 24x GPIO, Video Out Display Port 1.2. PanaTeQ offers a System Development Kit XMC-SDR-A-PSDK for the developers and that includes the XMC-SDR-A-D1N-AS and IO-XMC-SDR-A boards, a PetaLinux BSP, the PanaTeQ FPGA Design Kit (PAN-FDK) and cables. Key Features Vita 42.3 XMC Compliant Compatibility with ADI ADRV9009-ZU11EG RF SoM Dual ADRV9009 RF Wideband Transceivers Four TX and Four RX coherent channels synchronized in frequency and phase Wide tuning range 75MHz to 6GHz Max receiver BW 200MHz. Up to 800MHz using 4 receivers Max transmitter synthesis BW 450MHz Integrated LO and Phase sync between all channels On-board Xilinx Zynq UltraScale+ MPSoC as Baseband processor ZU7CG/ZU7EG/ZU7EV/ZU11EG FFVC-1156 Package Up to 8GB DDR bit PS memory with 8-bit ECC Up to 4GB DDR bit PL memory 64GB (V4.51), MRAM 512KB PCIe x8 Gen 1/2/3 on XMC-P5 4x User Defined MGT on XMC-P6 1x Display Port 1.2 Video Out on XMC-P6 1x ETH 1000Base-T on XMC-P4 2x USB 3.0/2.0, 2x USB 2.0, 1x SATA 3.1 on XMC-P6 24x LVCMOS or 12x LVDS GPIO on XMC-P6 2x RS.232/422/485, 2x CAN 2.0B on XMC-P4 Board Management Controller ARM Cortex-M3 based Air Cooled and Conduction Cooled Typical Applications Software Defined Radio, MILCOM, DataLink Massive MIMO Electronic Warfare, Signal Intelligence Phase Array RADAR Systems Version 1.2 August 2018
2 Block Diagram Baseband Processor Zynq Utrascale+ MPSOC ISP Board Management Controller FPGA ARM Cortex-M3 PMBus IPMB JTAG Power Supplies DC/DC LDO VPWR 3V3_AUX XMC-P5 Wideband RF 4x4 Dual ADRV9009 PCIe-GTH[7:4] PCIe-GTH[3:0] PCIe-GTR[3:0] MUX MUX GTH[11:8] 4x JESD204B GTH[15:12] LVCMOS_1V8 LVDS_1V8 4x JESD204B GTH[19:16] LVCMOS_1V8 LVDS_1V8 PS Memory DDR Up to 8GB with ECC PL Memory DDR Up to 4GB 64bit Data 8bit ECC 32bit Data Quad-Core Cortex-A53 GPU MALI 400 MP2 Memory Control DDR3 DDR4 SD PCIe Hard Block IP X8 Gen1/2/3 RC/EP FPU NEON Dual-Core Cortex-R5 VCU H.264/H265 4x GEM 2x UART 2x CAN 2x USB 3.0 2x SPI 2x I2C 2x SATA 3.1 Zynq Utrascale+ MPSoC ZU7/ZU11 CG/EG/EV FFVC-1156 Programming Logic USB 3.0 1x RGMII 2x Serial COM USB HUB Ports GETH PHY Magnetic 2x CANBus 2.0 2x USB 2.0 2x USB 3.0/2.0 1x 1000Base-T Display Port 1.2 Video Out 1x SATA x GPIO XMC-P6 + XMC-P4 SPI RS-232 R-422 RS-485 2x RS-232/422/485 MRAM 512KB NAND FLASH 64GB NOR FLASH 2x 64MB XMC VITA 42.3
![processors up to 600MHz: Low-latency, highly deterministic performance APU offloading New integrated hardened multimedia blocks up to 667MHz: Graphics processing unit (GPU) [ARM Mali -400MP2] 4Kx2K](/docs-images/85/91726588/images/3-1.jpg "60fps video encoder/decoder (VCU) [in select devices] 4Kx2K 30fps DisplayPort interface New integrated high-speed peripherals: PCIe Gen1 or Gen2 root complex and integrated Endpoint block in x1, x2,")
3 Xilinx Zynq Ultrascale+ MPSoC Processing System Highlights Applications processing unit (APU) with quad-core ARM Cortex -A53 processors up to 1.5GHz: Next-generation ARMv8 architecture supporting 32- or 64-bit data widths Ideal for Linux and bare-metal SMP/AMP application systems Real-time processing unit (RPU) with dual-core ARM Cortex-R5 processors up to 600MHz: Low-latency, highly deterministic performance APU offloading New integrated hardened multimedia blocks up to 667MHz: Graphics processing unit (GPU) [ARM Mali -400MP2] 4Kx2K 60fps video encoder/decoder (VCU) [in select devices] 4Kx2K 30fps DisplayPort interface New integrated high-speed peripherals: PCIe Gen1 or Gen2 root complex and integrated Endpoint block in x1, x2, and x4 lanes USB 3.0/2.0 with host, device, and OTG modes Gigabit Ethernet with jumbo frames and precision time protocol SATA 3.1 host Dedicated quad transceivers up to 6Gb/s General and boot peripherals: CAN, I2C,, SD,, and NAND flash interfaces GPIO, UART, and trace ports 6-port DDR controller with ECC, supporting x32 and x64 DDR3, DDR3L, LPDDR3, LPDDR4, DDR4 Integrated platform management unit (PMU) supporting multiple power domains Integrated configuration security unit (CSU) TrustZone support Peripheral and memory protection
4 Board Specifications XMC Interfaces VITA 42.3 Specifications compliant XMC P5: 8 lanes PCIe Gen1/2/3 XMC P6: 4x MGT up to 16.3 Gb/s connected to/from Zynq Ultrascale+ Programming Logic XMC P4; 1x ETH 1000BASE-T, 2x RS-232/422/485 XMC P6: 1x SATA 3.1, 1x Display Port 1.2 VIDEO OUT, 2x USB 3.0/2.0, 2x USB 2.0, 12x LVDS XMC P5: IPMI EEPROM, Temperatures, Voltages, Currents, Board Management Controller (BMC), JTAG Xilinx Zynq Ultrascale+ MPSoC Supported Devices:ZU7CG/ZU7EG/ZU7EV/ZU11EG FFVC1156 (Speed Grade 1/2/3) Processing System : Quad-Core ARM A53, Dual-Core ARM R5, GPU Mali-400, 2x SATA, 2x USB, 4x GETH MACs Programmable Logic: 504K Logic Cells (ZU7CG/EG) / 504K Logic Cells (ZU7EV) / 653K Logic Cells (ZU11EG) On-Chip Memories: 38Mb (ZU7CG/EG) / 38Mb (ZU7EV) / 43.6Mb (ZU11EG) DSP Slices: 1728 (ZU7CG/EG) / 1728 (ZU7EV) / 2928 (ZU11EG) High Speed Serial Links: 16 full duplex, high performance, GTH Multi-Gigabit Tranceivers up to 16.3 Gb/s 2x 10-bit, 1MSPS ADCs for System Monitoring Supported by PanaTeQ s FPGA Development Kit (PAN-FDK) External Memories Up to 8GB of DDR Processor System (PS) memory, 64-bit data, 8-bit ECC Up to 4GB of DDR Programmable Logic (PL) memory, 32-bit data, no ECC 64GB v4.51 of managed NAND Flash memory. HS200 up to 100MB/s 512KB of SPI MRAM (NVRAM) 2x 512Mb of NOR Flash memory for booting Zynq MPSoC Programmable Logic and Firmware Processing System Board Main ADI Components HW/SW compatible with ADI s ADRV9009-ZU11EG RF SOM ADRV9009: Integrated, Dual RF Transceiver with Observation Path HMC7044: JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD7291 : 8-Channel, I2C, 12-bit SAR ADC with Temperature Sensor RF Performances RF coverage 75MHz to 6.0GHz Tx synthesis bandwidth to 450MHz Rx bandwidth to 200MHz On-board VCXO Options (see ordering information) MHz MHz MHz MHz MHz Front I/O: 10x SSMC Connectors TX Transmitter Channel 1 Output (From ADRV9009) TX Transmitter Channel 2 Output (From ADRV9009) TX Transmitter Channel 3 Output (From ADRV9009) TX Transmitter Channel 4 Output (From ADRV9009) RX Receiver Channel 1 Input (To ADRV9009) RX Receiver Channel 2 Input (To ADRV9009) RX Receiver Channel 3 Input (To ADRV9009) RX Receiver Channel 4 Input (To ADRV9009) Optional Input/Output External Reference Clock Input (To AD9578) Environnemental Specifications Commercial Ruggudized 0-50C Conduction Cooled 40C to 70C at Thermal Interface
5 Product Codification The XMC-SDR-A can be assembled with different versions of the Zynq Ultrascale+ devices and various amounts of memory storage. The cooling technique et ruggedization level are also available options. The following table shows the product coding for all these options. XMC-SDR-A B 1 N AS Device ARM A53 System DSP GPU VCU Cores Logic Cells Slices Memory A XCZU7CG 2 No No 504K Mb B XCZU7EG 4 Yes No 504K Mb C XCZU7EV 4 Yes Yes 504K Mb D XCZU11EG 4 Yes No 653K Mb Device Speed Grade 1 Slowest 2 Mid 3 Fastest N M PS / PL Memory Size 4GB/1GB 8GB/2GB Ruggedization Level VITA 47 AS Air Standard EAC4 AR Air Rugged EAC6 CC Conduction Cooled ECC3 CR Conduction Rugged ECC4 Ordering Information The following product references are offered by PanaTeQ as standard products. Other combinations of devices, speed grade, memory and cooling can be specially ordered. Please contact us for details Reference Device Speed Memory Ruggedization Level XMC-SDR-A-A1N-AS ZU7CG -1 4GB/1GB Standard Air Cooled XMC-SDR-A-A1N-CC ZU7CG -1 4GB/1GB Conduction Cooled XMC-SDR-A-B1N-AS ZU7EG -1 4GB/1GB Standard, Air Cooled XMC-SDR-A-B1N-CC ZU7EG -1 4GB/1GB Conduction Cooled XMC-SDR-A-C1N-AS ZU7EV -1 4GB/1GB Standard, Air Cooled XMC-SDR-A-C1N-CC ZU7EV -1 4GB/1GB Conduction Cooled XMC-SDR-A-D1N-AS ZU11EG -1 4GB/1GB Standard, Air Cooled XMC-SDR-A-D1N-CC ZU11EG -1 4GB/1GB Conduction Cooled Reference XMC-SDR-A-PDSK IO-XMC-SDR-A VPX3-XMC-SDR-A PCIe-XMC-SDR-A Description XMC-SDR-A Development System Kit IO Carrier board for XMC-SDR-A 3U VPX Carrier board for XMC-SDR-A PCIe Carrier board for XMC-SDR-A PanaTeQ 7812 E. Acoma Dr # Scottsdale, AZ, USA Available from: 10C Ch. Sous-Bois 1212 Geneva, Switzerland info@panateq.com
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