Application Note: APP0002 Rev D. DLIS 2K/4K- Mode Programming Guide

Transcription

1 Application Note: APP0002 Rev D DLIS 2K/4K- Mode Programming Guide The DLIS 2K/4K is a multi-mode sensor featuring a user programmable timing engine. The sensor contains 4 rows of pixels. Each row contains 16 dark pixels and 2080/4096 optical pixels. Several topics for DLIS operation are discussed in this note as well as useful programming data for use with the DLIS demonstration kit. The main purpose of this document is to describe how the imager is put into and operated in different modes of operation. The different modes of operation are as follows: 1. Normal/ Correlated Double-Sampling (CDS) 2. Ambient light subtraction 3. High Dynamic Range (HDR) 4. Correlated Multi-Sampling (CMS) 5. Non-Destructive Read 6. Binning of different rows 7. High resolution readout 8. Auto Dynamic Threshold (ADT) In addition to sections on each of the different modes, a section is also included on advanced options. Many of these options can be utilized in some or all of the operating modes, but separated out for clarity. A section on how to write a setup file for the Unified Demo board, is also included at the end of this document. The DLIS demonstration kit provides all the listed setup timing files to accomplish different readout modes listed above. Please refer to the Unified GUI User Manual (latest rev.) to setup the demonstration kit. The modes listed above are not the only modes of operation, combinations and permutations are possible by experienced operator. Contact the company for engineering assistance if needed. Digital Linear Image Sensor (DLIS) Timing Overview The CMOS imager is an array of individual pixels that are accessed in a sequential order for display. The readout occurs after the selected row and associated timing for the desired readout mode has occurred. The APP0002 Rev D.doc Page 1 7/10/2009

2 different readout modes are listed above. No matter what mode is selected, the information is none the less read out in a predetermined sequential order. It is this predetermined sequence that this application note will explain and explore the options available to the camera designer. The order of timing will be referenced to the DLIS sensors. The DLIS sensors are based on a Distributed Analog to Digital per pixel (D/AD TM ) architecture patented by Panavision Imaging. The predetermined sequence, follows three top level functions. The three top level functions are: row selection, sampling, digitizing the pixel data from the selected row, and reading the stored data out to the camera. In short we will refer to these operations as: row selection, sampling, digitizing and readout. Before a detailed timing sequence discussion can ensue for the different modes of operation, a good conceptual explanation of row selection, sampling and readout must be understood first. Also, the necessary jargon is defined to aid the subsequent detailed discussions that follow. Row Selection Row Sampling/Digitization reference and video data Row Readout Fig. # 1 Top level imager timing sequence. Row sampling/digitizing consists of two operations, background (reference level) capture and video capture. Row selection for background capture occurs by programming one of four Row_Reset registers to reset the sense node. When the sense node is reset this becomes the reference level (a.k.a. background level) that is digitized. The sense node is the node that is digitized by the Distributed Analog to Digital (D/AD TM ) per pixel. The sense node is common for the four photodiodes. Row selection for video capture occurs by programming one of four Shutter registers to transfer the pixel charge to the sense node for reading. After the pixel charge has been transferred and digitized by the D/AD TM the sense node needs to be reset to accept the next transfer. The difference between the reference level and the video, is the Correlated Double Sampled (CDS) information that is output to the user. Since the video is digitized and has the reference level subtracted from the video there are a couple of items that need to be understood by the user. Subtraction of the reference level from the video level is done to remove all or most of the Fixed Pattern Noise (FPN) that exists at black. Black is used here as the signal generated by the imager without any light exposure. If at black the video and reference level are identical the output is zero counts. Add in some noise then it is possible that one can generate a negative value for video. Since the DLIS sensor doesn t have the ability to show a negative value it will output the rollover of data. Unfortunately, the data will appear as if it is bright white on the output instead of black. To eliminate this problem, and keep the digital block as simple as possible to keep costs down, we added in a programmable offset to the video data and the default value is 128 counts to account for the extreme cases of wide temperature ranges and noisy environments the imager may be used in. The user can reprogram if needed to maximize the dynamic range of the system. When the imager is approaching saturation the video information becomes non-linear in its response and the offset information is lost and stronger FPN is noticed on the output. To minimize FPN, the exposure can be reduced or utilize one of the modes like, Ambient APP0002 Rev D.doc Page 2 7/10/2009

3 light subtraction, High dynamic range (HDR), or Correlated Multi-Sampling (CMS). Another aspect of reading digital data, is the10 bit external data bus and 11 bit internal latches in that the user with some of the modes, like HDR and CMS, could have data in the eleventh bit and not be reading out the data. If there is data in the eleventh bit that is not readout the data effectively has 1023 counts subtracted from those pixels and the data that should appear bright will now be dark. Proper set up of the D/AD for resolution and the number of reads will eliminate any potential issues. Also, the user should they decide that data in the eleventh bit is proper the user has the option to read out the upper ten bits. The reason for the 11 bit latches is to have good 10 bits of information after CDS the signal internally should be 11 bits. The DLIS sensors are very flexible and allow the user to program the bit depth of the DAC from 8 to 12 bits per sample. PROGRAMMABLE SIGNAL DEFINITIONS In the following section, the individual programmable timing edges required to implement each mode are grouped into functional blocks, and then further described of their function and impacts on the operation of the sensor. Correlated Double Sampling (CDS) is the default mode, and will be the basis for all other modes in describing individual timing edges. Subsequent modes will be described in differences from the default mode. Pixel SHUTTER [0:3]- When active high, connects pixel to sense node which transfers charge accumulated in pixel to the column amplifier or resets the pixel in conjunction with the additional following signal combinations: ROW_RESET [0:3]- When active high, resets column amplifier sense node. Also resets pixel when SHUTTER is invoked. Row Reset in conjunction with the following signal combinations sets the sense node and or pixel to the following conditions: ROW_RESET- Resets sense node to column amplifier bias. ROW_RESET + ZERO_RESET + AMP_ACTIVATE - Resets sense node to zero. ROW_RESET + FORCE_RESET + AMP_ACTIVATE- Resets sense node to BLKRESET0 Bias. SHUTTER + ROW_RESET- Reset pixel & sense node to column amplifier bias. SHUTTER + ROW_RESET + ZERO_RESET + AMP_ACTIVATE - Reset pixel & sense node to zero. SHUTTER + ROW_RESET + FORCE_RESET + AMP_ACTIVATE- Reset pixel & sense node to BLKRESET0 Bias. Note: FORCE_RESET and ZERO_RESET not to be active at same time, and only in conjunction with AMP_ACTIVATE. APP0002 Rev D.doc Page 3 7/10/2009

4 Column Amplifier/Comparator AMP_ACTIVATE- When low, disconnects column amplifier from pixel by shutting off current loop between pixel and column amplifier. See Row Reset combinations shown above. FORCE_RESET- When high, resets pixel and/or sense node to BLKRESET0 Bias. See Row Reset combinations shown above. ZERO_RESET- When high, resets pixel and/or sense node to zero. See Row Reset combinations shown above. Distributed A/D (D/AD ) COUNTER_CLK- Drives counter to per column distributed A/D binary converter latches. DATA_VALID- Active high during readout of pixel values. EXTRA_CLK- Used in conjunction with TOGGLE to toggle between MINUS_CNT and PLUS_CNT. MINUS_CNT- When initiated (high pulse), latches negative count value. PLUS_CNT- When initiated (high pulse), latches positive count value. PRELOAD- When high, sets a predetermined digital black threshold value. READOUT- When high, reads out values stored in column latches. RESET_LATCH- When active low, resets column latches to zero. TOGGLE- When active high, and overlapping EXTRA CLK (high) allows toggling between MINUS_CNT or PLUS_CNT. WRITE- When active high, enables count values to column latches. Ramp DAC BIN_CNT_CLK- Drives DAC binary counter that creates Video/Background Ramp. BIN_CNT_RST- Resets DAC binary counter. PULL_UP_DAC- Auxiliary signal to insure hard pull up on DAC output. APP0002 Rev D.doc Page 4 7/10/2009

5 1.) Normal/ Correlated Double-Sampling (CDS)-Default Mode CONCEPT The default programming upon power up is normal CDS destructive readout. This mode is the standard or only mode of operation for most imagers. Correlated Double Sampling is performed by reading the background and then the video and taking the difference. The background information is read by resetting and sampling the sense node. The video is sampled after transferring the pixel value onto the sense node. The difference between the two is output to the 10 bit port. In DLIS Distributed Analog to Digital (D/AD TM ) the bit depth of the DAC is adjustable from 8 to 12 bits and by default is set to 10-bits digital format by setting the appropriate registers as shown in figure #2. Address Name Description/Bits 0x003 DAC_CON Bits [14:12] = DAC Counter Clock Shift Control 000: 12 bit ramp 001: 11 bit ramp 010: 10 bit ramp (default) 011: 9 bit ramp 100: 8 bit ramp Default at Reset=0x2 Figure #2- DAC bit depth registers The user should become familiar with all the registers by referring to the imager specification. The CDS function is also realized in the digital domain, meaning that the background and video are digitized separately and digitally differenced for the output. CONCEPTUAL WAVEFORMS (Readout not shown for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) RAMP ROW RESET SHUTTER Sample Background Sample Video Photo-Diode Reset Standard CDS Sample Timing Exposure time Start for next frame APP0002 Rev D.doc Page 5 7/10/2009

6 DETAILED OPERATION The CDS mode begins by resetting the sense node to the background level and digitizing it by the distributed A/D (D/AD ) per column Resetting the pixel sense node to the background level is accomplished by programming a logic high to ROW_RESET signal for the desired row [0:3]. The described ROW_RESET or SHUTTER functions may also be invoked via the external Reset[0:1] pins and/or Shutter[0:1] pins, except for Row 3, which is programmed internally. Both Reset & Shutter External pins are combined with internally programmed ROW_RESET [0:2] & SHUTTER [0:2] as a logical OR function. External pins as decoded as shown in figure #3 Row selected Shutter 0 Shutter 1 Reset 0 Reset 1 Row 3 -Programmed via internal registers Row Row Row None Figure #3: Two bit decoder for row reset & selection Before initiating a capture of the background value, line overhead timing must be initialized, the DAC & latches must be reset, and plus count mode initiated for preload. Line overhead timing is initialized by the user by providing an active high pulse to the external start pin. A start pulse is required for each line. The user may invoke the external start pulse asynchronously. The Start pin is re-synchronized internally to create a synchronized start pulse. This method reduces the requirements on the start pulse input. For example, a microprocessor could assert start simply from an output pin from the processor DLIS imager. The external start pin is asynchronous, as internal logic performs all proper synching, debounce and meta-stability handling. The START pulse requires a minimum pulse width of 4 clock cycles to debounce and resynchronize the signal, and properly initialize the overhead timing. DAC is set to maximum value by the PULL_UP_DAC signal at the same time the BIN_CNT_RST signal is issued. Latches are reset with RESET_LATCH. A preload value is typically initiated before background capture. The preload count is set to a default of 128 counts. The preload value is accomplished by issuing PRELOAD (active high) + COUNTER_CLK + PLUS_CNT. Count mode direction is set by: TOGGLE (active high) overlapping EXTRA_CLK (active high) and then setting PLUS_CNT to a logic high coincidentally with COUNTER_CLK. This sets count direction and clocks in preload count values. For more info on Preload, go to Advanced Options, page 33. The change count mode is initiated by clocking TOGGLE (active high) overlapping EXTRA_CLK (active high). MINUS_CNT is set logic high concurrently with BIN_CNT_CLK + COUNTER_CLK which resets count direction, generates DAC ramp, and clocks in latch values. Once the sense node is charged up to background level, the ROW_RESET [0:3] signal goes low, immediately, the background ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count and the comparator APP0002 Rev D.doc Page 6 7/10/2009

7 compares background value with ramp and triggers the counter to store background value. WRITE is set active high from start of background capture to end of video capture. Before initiating a capture of the video value, the count mode must be switched, and plus count mode initiated. It is important to allow hold time of approximately 1 microsecond before issuing the next ramp to allow for settling of the DAC output. The change count mode is initiated by clocking TOGGLE (active high) overlapping EXTRA_CLK (active high). PLUS_CNT is set logic high concurrently with BIN_CNT_CLK + COUNTER_CLK which resets count direction, generates DAC ramp, and clocks in latch values. Programming note: MINUS_CNT, PLUS_CNT, TOGGLE not be held high at the same time in any combination or overlapping. Once background value is sampled and background ramp is complete, user can transfer photo-diode value from current integration period. Integration period is set by a simultaneous ROW_RESET[0:3] and SHUTTER[0:3] (both active high) which resets the pixel and sense node, Programming a logic low to SHUTTER begins the integration period for the video value. User programs a logic low to ROW_RESET after resetting the sense node. Integration period for video value is completed by the following SHUTTER[0:3] pulse (falling edge) which sets end of integration time. During this SHUTTER pulse, the integrated photo-diode value is transferred onto the sense node while active high. After SHUTTER[0:3] signal is set low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares video value with video ramp and triggers the latches to store the DAC count of the video value. Final correlated double sampled photo-diode value is derived from subtracting background value from video value. Resulting value is then read out to outputs by toggling WRITE to logic low and initiating READOUT. Readout clock rates can be altered by changing the following internal register as shown in figure #4. Programming note ROW_RESET[0:3] to overlap SHUTTER[0:3] by a minimum of 20ns/100ns (see page 34) to allow for settling of the sense node. Overlap also applies to external control of Row Reset and Shutter Address Name Description/Bits 0x007 OPMODE Bits(10:8) RCLK_DIV: Divide down MCLK for Readout Frequency 000: Divided by 2 (default) 001: Divided by 4 * 010: Divided by 8 * 111: Divide by 1 * Default at Reset = 0x8070 * Contact Panavision Imaging if using other than default value Figure #4 Readout Clock Register APP0002 Rev D.doc Page 7 7/10/2009

8 DETAILED WAVEFORMS Default CDS Sample Timing- Setup file: fle_dlis4k_9bit_1x.txt APP0002 Rev D.doc Page 8 7/10/2009

9 REQUIRED REGISTER/GUI SETTINGS- TIMING REGISTER MAP Default Internal Register Settings (Valid up to 24MHz MCLK. All settings are counts based on MCLK, except for READOUT- default MCLK/2) Initial Available Edges Signal Signal Type Value Not programmed BIN_CNT_CLK Clock th -18 th : 0 COUNTER_CLK Clock th -18 th : 0 BIN_CNT_RST Active High PULL_UP_DAC Active High th -18 th : 0 AMP_ACTIVATE Active Low ZERO_RESET Active High FORCE_RESET Active Low PLUS Active High th -10 th : 0 MINUS Active High th -10 th : 0 TOGGLE Active High th -12 th : 0 READOUT Active High WRITE_IN Active High th -16 th : 0 EXTRA_CLK Active High th -12 th : 0 PRELOAD Active High RESET_LATCH Active Low SHUTTER0 Active High th -8 th : 0 SHUTTER1 Active High th -8 th : 0 SHUTTER2 Active High th -8 th : 0 SHUTTER3 Active High th -8 th : 0 ROW_RESET0 Active High th -8 th : 0 ROW_RESET1 Active High th -8 th : 0 ROW_RESET2 Active High th -8 th : 0 ROW_RESET3 Active High th -8 th : 0 DATA_VALID Active High APP0002 Rev D.doc Page 9 7/10/2009

10 Set Up File for Unified Demo Board/DLIS-4K: 9 Bit, Correlated Double Sampling (CDS) Mode (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! <PERIOD,9999,0, 10800, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <reg_pwrcon,2,cofo,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,3c8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,4004,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,512,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 2546, 10788, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BINCNT_RESET,16,0, 1200, 1228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PULLUP_DAC,48,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <AMPACT,72,1, 5900, 6200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1,50,100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <PRELOAD,160,0, 200, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER0,176,0, 2010, 2018, 6360, 6440, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER1,192,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST0,208,0, 1220, 1228, 6340, 6600, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST1,224,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1230, 1740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PLUS_CNT,272,1, 800, 2020, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <WRITEIN,288,1, 2542, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <TOGGLE,304,0, 1098, 1122, 1862, 1886, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <COUNTER_CLK,528,0, 200, 224, 1230, 1740, 2020, 2530, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 2546, 10788, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EXTRA_CLK,640,0, 1106, 1114, 1870, 1878, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BIN_CLK,368,0, 1230, 1744, 2020, 2534, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> APP0002 Rev D.doc Page 10 7/10/2009

11 2.) Ambient light subtraction (Double Sampling) CONCEPT DLIS 4k provides flexible control when sampling video. Ambient light subtraction is an example of the DLIS flexibility. In applications where there is a controlled flash or lighting in the presence of a ambient light level that adds a significant offset to the desired signal, modified timing allows for ambient light subtraction. The oversampling function can be realized by adjusting SHUTTER and RESET signal to integrate background light for subtraction. The following conceptual timing diagram illustrates the modified timing. CONCEPTUAL WAVEFORMS (Readout not shown for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) RAMP RESET SHUTTER Sample ambient light level Sample video Video exposure time Ambient exposure time Photo-Diode Reset Double Sample Timing Sample flash light level DETAILED OPERATION In double sampling mode, the sensor can sample different ambient light levels to get desired offset. In a practical application the user may want to integrate as long for the ambient light subtraction as the actual integration with controlled light. The user can access this mode by programming the serial-interface. A ambient light subtraction setup file is provided for reference only. As in the default mode setup, the user must first initiate the start sequence (see CDS default mode section). A preload value is typically initiated before background captures. (see CDS default mode) The double sampled mode begins with the pixel/sense node charged to background level by programming a logic high to ROW_RESET & SHUTTER signals for desired row [0:3]. Programming a logic low to SHUTTER begins the integration period for the ambient background. User programs a logic low to ROW_RESET after ( 100 ns hold time) resetting the sense node. APP0002 Rev D.doc Page 11 7/10/2009

12 Integration period for ambient light value is completed by the following SHUTTER[0:3] pulse (falling edge) which sets end of integration time. During this SHUTTER pulse, the integrated ambient light photo-diode value is transferred onto the sense node while active high. After SHUTTER[0:3] signal goes low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares ambient light value with video ramp and triggers the latches to store the DAC count of the ambient light value. Once video ramp has been completed, ROW_RESET[0:3] is pulsed logic high to charge sense node to background level Before initiating a capture of the video value, the count mode must be switched- (see CDS default mode section). Once ambient light value has been transferred to the sense node, the integration period for video value begins after programming a logic low to SHUTTER[0:3]. Integration period for video value is completed by the following SHUTTER[0:3] pulse (falling edge) which sets end of integration time. During this SHUTTER pulse, the integrated photo-diode value is transferred onto the sense node while active high. After SHUTTER[0:3] signal goes low video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares video value with video ramp and triggers the latches to store the DAC count of the video value. Resulting double sampled value is subtracted during readout to outputs by toggling WRITE to logic low and initiating READOUT. User will have selectable feedback to trigger flash source based upon the Sync signal selected to be outputted by the TM pin. APP0002 Rev D.doc Page 12 7/10/2009

13 DETAILED WAVEFORMS Setup file: fle_dlis4k_9bit_1x_amb.txt APP0002 Rev D.doc Page 13 7/10/2009

14 REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS Set Up File For Unified Demo Board/DLIS-4K: 9 Bit, Ambient light subtraction Mode (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! <PERIOD,9999,0, 9400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <reg_pwrcon,2,cofo,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,4c8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,4004,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,200,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 3426, 11658, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BINCNT_RESET,16,0, 400, 440, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PULLUP_DAC,48,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <AMPACT,72,1, 6900, 7200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1,50,100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <PRELOAD,160,0, 200, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER0,176,0, 1120, 1132, 1250, 1254, 2830, 2844, 7360, 7440, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER1,192,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST0,208,0, 1110, 1142, 2690, 2722, 7340, 7600, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST1,224,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1250, 1740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <PLUS_CNT,272,1, 800, 2830, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <WRITEIN,288,1, 3422, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <TOGGLE,304,0, 1098, 1122, 2652, 2676, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <COUNTER_CLK,528,0, 200, 260, 1250, 1740, 2830, 3320, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 3426, 11658, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EXTRA_CLK,640,0, 1106, 1114, 2660, 2668, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BIN_CLK,368,0, 440, 952, 1230, 1742, 2810, 3322, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> APP0002 Rev D.doc Page 14 7/10/2009

15 3.) High dynamic range (HDR) CONCEPT In this mode the sensor can sample and combine pixel data with short and long exposure times to extend dynamic range. High Dynamic Range (HDR) is accomplished by adding two rows with different exposure times in storage together and reading the average to extend dynamic rage of the image. CONCEPTUAL WAVEFORMS (Readout not shown for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) RAMP ROW RESET0 Sample Background0 Sample Video0 SHUTTER0 Exposure time ROW RESET1 SHUTTER1 Photo-Diode Reset Sample Background1 Sample Video1 Exposure time start - next frame Exposure time end Photo-Diode Reset High Dynamic Range (HDR) Timing DETAILED OPERATION In the high dynamic range mode, the sensor is programmed to combine two different exposures and readout either combined values or average values. Options depend on ramp bit depth settings as well as Imager array upper/lower bit settings. See figure #4. HDR-Sequential Row Method As in the default mode setup, the user must first initiate the start sequence (see CDS default mode section). The high dynamic range mode begins with the reading and storing the short integration row. The sense node charged to background level by programming a logic high to ROW_RESET signal for desired row [0:3]. Rows 0&1 are used for this example. Once the sense node is charged up to background level, the ROW_RESET0 signal goes low, immediately, the background ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count and the comparator compares background value with ramp and triggers the counter to store background values of the short integration row. APP0002 Rev D.doc Page 15 7/10/2009

16 Before initiating a capture of the short integration row video values, the count mode must be switched- (see CDS default mode section). It is important to allow hold time of approximately 1 microsecond between successive background/video ramps, and background to video transition, to allow for settling of the DAC output. See Detailed Waveforms Once short integration row background value is sampled and background ramp is complete, user can transfer photo-diode value from current integration period. Integration period- (see CDS default mode section). Once SHUTTER0 has been pulsed logic high which transfers photo-diode value to sense node, SHUTTER0 signal is set low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares video value with video ramp and triggers the latches to store the DAC count of the short integration row video values. To capture long integration row video values. The previous cycle is repeated for Row_Reset1 and Shutter1 signals without issuing Reset_Latch Resulting value is then read out to outputs by toggling WRITE to logic low and initiating READOUT. User can read HDR data in two ways. To read combined HDR values, user reads all bits +1 depending on DACCON & OPMODE register settings. See figure #4. To read average HDR values, user reads output shifted by 1 bit, controlled by DACCON & OPMODE register settings. See figure #4. OPMODE- 0x007 Ramp DACCON- 0x003 Register setting- Bits [14:12] Register setting- Bit[14] 0: Selects Bits [11:0] 1: Selects Bits [12:1] HDR Readout Output Assignment Notes 8 Bit 0x498C 0x8070 Full Value Bits [8:0] 9 Bit Output, 9 Bit 0x398C 0x8070 Full Value Bits [9:0] 10 Bit Output 10 Bit 0x298C 0x8070 Full Value Bits [9:0] MSB truncated 11 Bit 0x198C 0x8070 Full Value Bits [9:0] Lower 10 Bits only 12 Bit 0x098C 0x8070 Full Value Bits [9:0] Lower 10 Bits only 8 Bit 0x498C 0x8170 Average Value Bits [7:0] LSB truncated 9 Bit 0x398C 0x8170 Average Value Bits [8:0] LSB truncated 10 Bit 0x298C 0x8170 Average Value Bits [9:0] LSB truncated 11 Bit 0x198C 0x8170 Average Value Bits [9:0] Invalid Data 12 Bit 0x098C 0x8170 Average Value Bits [9:0] Invalid Data Figure #4- HDR DAC bit depth settings HDR-Variable Exposure Binning Method APP0002 Rev D.doc Page 16 7/10/2009

17 As in the default mode setup, the user must first initiate the start sequence (see CDS default mode section). The high dynamic range mode using a binning method begins with the reading and storing the background of the short integration row and the long integration row by binning both rows together. The sense node charged to background level by programming a logic high to ROW_RESET signal for desired rows [0:3]. Rows 0&1 are used for this example. Once the sense node is charged up to background level, the ROW_RESET0 + ROW_RESET1 signal goes low, immediately, the background ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count and the comparator compares background value with ramp and triggers the counter to store background values of the short integration row. Before initiating a capture of the binned long & short integration row video values, the count mode must be switched- (see CDS default mode section). It is important to allow hold time of approximately 1 microsecond between successive background/video ramps, and background to video transition, to allow for settling of the DAC output. See Detailed Waveforms Once short & long integration row background values are sampled and background ramp is complete, user can transfer photo-diode value from current integration period. Integration period for the long integration time begins typically during readout of the prior frame to take advantage of the proportionately longer readout period. The short integration time begins typically at the beginning of the frame before background is read. For both integration periods, resetting the sense node and pixel together starts the integration period. (see CDS default mode section). Once SHUTTER0 + SHUTTER1 has been pulsed logic high which transfers photo-diode value to sense node, SHUTTER0 + SHUTTER1 signal is set low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares the binned video value with video ramp and triggers the latches to store the DAC count of the binned short & long integration video values. Final high dynamic range photo-diode value is derived from subtracting background value from video value. Resulting value is then readout to outputs by toggling WRITE to logic low and initiating READOUT. User has the option to read the averaged CMS values by bit shifting and reading the upper bits, or read the lower bits for more sensitivity. In this mode, the user needs to ensure that the combined charge of the binned long- and short-exposed pixels does not exceed the saturation level. This limits the ratio between the long- and shortexposure times (depending on light), thusly limiting the extension in dynamic range to a lower limit as compared to the HDR mode described in the previous section. APP0002 Rev D.doc Page 17 7/10/2009

18 DETAILED WAVEFORMS HDR.0 Variable Exposure Binning with 2x CMS Sample Timing- Setup file: fle-dlis2k_9bit_hdr_cnt.txt APP0002 Rev D.doc Page 18 7/10/2009

19 REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS Set Up File For Unified Demo Board/DLIS-4K: 9 Bit, High Dynamic Range (HDR) Mode (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! <PERIOD,9999,0, 18300, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <reg_pwrcon,2,c0f0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,3e8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,4004,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,200,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 10026, 18258, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BINCNT_RESET,16,0, 300, 350, 3030, 3080, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <AMPACT,72,1, 12680, 12800, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1, 50, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PRELOAD,160,0, 200, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER0,176,0, 2160, 2168, 12440, 12560, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER1,192,0, 5200, 5320, 9490, 9498, 12440, 12560, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST1,208,0, 1250, 1258, 12420, 12860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST2,224,0, 5180, 5340, 8680, 8688, 12420, 12860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1260, 1770, 8690, 9200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PLUS_CNT,272,1, 240, 2170, 2680, 9500, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <WRITEIN,288,1, 10022, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <TOGGLE,304,0, 248, 272, 1908, 1932, 6000, 6024, 9338, 9362, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <COUNTER_CLK,528,0, 200, 224, 1260, 1770, 2170, 2680, 8690, 9200, 9500, 10010, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 10026, 18258, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EXTRA_CLK,640,0, 256, 264, 1916, 1924, 6008, 6016, 9346, 9354, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BIN_CLK,368,0, 350, 862, 1260, 1772, 2170, 2682, 8690, 9202, 9500, 10012, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> APP0002 Rev D.doc Page 19 7/10/2009

20 4.) Correlated Multi-Sampling (CMS) CONCEPT Correlated Multi-Sampling- Background and Video are over-sampled and then differentially averaged to combine the known benefits of both Over-Sampling and Correlated Double-Sampling. In correlated multi-sampling mode the sensor can combine multiple background and video samples in one readout (CMS). In this mode the output is an average of the valid signal, and the temporal noise is reduced. The corresponded timing diagram for 2x oversampling is shown below. The timing for 4x sampling is similar as shown with exception of 4 background and video samples instead of 2. The sample data listed below in figure #5 show achievable results of correlated multi-sampling. MCLK -15MHz, 10 bit readout DSNU (% FSD) Temporal Noise (%FSD) Normal sampling x oversampling x oversampling Figure #5 Correlated Multi-Sampling Data 1x(no) Correlated Multi-Sampling Setup file: fle_dlis2k_9bit_1x_dr.txt, 9 Bit Ramp, MCLK: 24 MHz, Row: 0 (32 um Pixel) 2x Correlated Multi-Sampling Setup file: fle_dlis2k_9bit_2x_dr.txt, 9 Bit Ramp, MCLK: 24 MHz, Row: 0 (32 um Pixel) 4x Correlated Multi-Sampling Setup file: fle_dlis2k_9bit_4x_dr.txt, 9 Bit Ramp, MCLK: 24 MHz, Row: 0 (32 um Pixel) APP0002 Rev D.doc Page 20 7/10/2009

21 CONCEPTUAL WAVEFORMS (Readout not shown for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) Timing Diagram of 2x Oversampling DETAILED OPERATION In the correlated multi-sampling mode, the sensor can be programmed to sample 2x, 3x or 4x background/video samples. The user can access this mode by programming the serial-interface. As in the default mode setup, the user must first initiate the start sequence (see CDS default mode section). The correlated multi-sampling mode begins with the sense node charged to background level by programming a logic high to ROW_RESET & SHUTTER signals for desired row [0:3]. Once the sense node is charged up to background level, the ROW_RESET [0:3] signal goes low, immediately, the background ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count and the comparator compares background value with ramp and triggers the counter to store background value. Depending on whether 2X, 3X, or 4X sampling is desired, the sequence of BIN_CNT_CLK plus COUNTER_CLK is repeated while MINUS_CNT is held at logic high. Before initiating a capture of the video value, the count mode must be switched- (see CDS default mode section). It is important to allow hold time of approximately 1 microsecond between successive background/video ramps, and background to video transition, to allow for settling of the DAC output. APP0002 Rev D.doc Page 21 7/10/2009

22 Once background value is sampled and background ramp is complete, user can transfer photo-diode value from previous integration period. Integration period- (see CDS default mode section). Once SHUTTER[0:3] has been pulsed logic high which transfers photo-diode value to sense node, SHUTTER[0:3] signal is set low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares video value with video ramp and triggers the latches to store the DAC count of the video value. Depending on whether 2X, 3X, or 4X sampling is desired, the sequence of BIN_CNT_CLK plus COUNTER_CLK is repeated while PLUS_CNT is held at logic high. Number of video samples must correspond to number of background samples. Final correlated multi-sampled photo-diode value is derived from subtracting background value from video value. Resulting value is then readout to outputs by toggling WRITE to logic low and initiating READOUT. User has the option to read the averaged CMS values by bit shifting and reading the upper bits, or read the lower bits for more sensitivity. User will have selectable feedback to trigger flash source based upon the Sync signal selected to be outputted by the TM pin. Programming note: As shown in detailed waveform, programming an additional BIN_CNT_CLK period before background sampling to set up a dummy ramp is beneficial for matching noise structure for background sample. APP0002 Rev D.doc Page 22 7/10/2009

23 DETAILED WAVEFORMS Correlated Multi-Sampling (CMS) Sample Timing- Setup file: fle_dlis4k_9bit_2x_cms.txt APP0002 Rev D.doc Page 23 7/10/2009

24 REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS Set Up File For Unified Demo Board/DLIS-4K: 9 Bit, 2X correlated multi-sampling Mode (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! <PERIOD,9999,0, 12400, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <reg_pwrcon,2,cofo,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,3c8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,4004,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,200,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 4126, 12368, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <BINCNT_RESET,16,0, 400, 440, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PULLUP_DAC,48,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <AMPACT,72,1, 8900, 9200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1,50,100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <PRELOAD,160,0, 200, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER0,176,0, 2830, 2844, 10360, 10440, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER1,192,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST0,208,0, 1250, 1254, 10340, 10600, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST1,224,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1250, 2530, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <PLUS_CNT,272,1, 800, 2830, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <WRITEIN,288,1, 4122, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <TOGGLE,304,0, 1098, 1122, 2652, 2676, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <COUNTER_CLK,528,0, 200, 260, 1250, 1740, 2040, 2530, 2830, 3320, 3620, 4110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 4126, 12368, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <EXTRA_CLK,640,0, 1106, 1114, 2660, 2668, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <BIN_CLK,368,0, 440, 952, 1230, 1742, 2020, 2532, 2810, 3322, 3600, 4112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> APP0002 Rev D.doc Page 24 7/10/2009

25 5.) Non-Destructive Read CONCEPT The sensor can be enabled thru timing to readout in the Non-Destructive mode. Non-Destructive Read is the function of reading out pixel data each line/frame time without resetting the pixels or disrupting active integration. The Non-Destructive Read function can be realized by adjusting SHUTTER and RESET signals. User can use this function to observe active video capture while integrating to achieve capture of low illumination scenes. Also useful for asynchronous strobe events. CONCEPTUAL WAVEFORMS (Readout not shown full scale for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) WRITE Frame Readout 1 Frame Readout 2 Frame Readout #n READOUT RAMP Exposure time Start ROW RESET0 Sample Background1 Sample Background2 Sample Background #n Sample Video1 Sample Video2 Sample Video #n SHUTTER0 Photo-Diode Reset Exposure time End START Non-Destructive Read Sample Timing DETAILED OPERATION To be detailed in future firmware release DETAILED WAVEFORMS To be detailed in future firmware release REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS To be detailed in future firmware release APP0002 Rev D.doc Page 25 7/10/2009

26 6.) Binning of different rows CONCEPT Binning of different rows is a mode to increase the sensitivity by increasing the effective pixel area. As stated previously the four pixels share the same sense node and when two or more shutter signals are operated in parallel the pixel charge is transferred on to the sense node. Binning rows if combined with CMS allows for further increases in sensitivity. CONCEPTUAL WAVEFORMS (Readout not shown for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) RAMP ROW RESET1 SHUTTER1 Sample Background Sample Video Exposure time Start for next frame ROW RESET2 SHUTTER2 Photo-Diode Reset Binning & Standard CDS Sample Timing DETAILED OPERATION Binning can be initiated in all readout modes without limitation, except for High Resolution Mode, and HDR (High Dynamic Range) mode. High Resolution Mode & HDR mode requires two independent rows, and binning is limited by remaining available rows. Binning Row 3 (offset by 2 microns) with any other row will reduce resolution and MTF (Modulation Transfer Function) Binning is achieved by simultaneously selecting more than one ROWRESET[3:0] and SHUTTER[3:0] at a time as required by desired readout mode. User duplicates timing (external Row Reset/Shutter) and or registers for desired rows to be binned. APP0002 Rev D.doc Page 26 7/10/2009

27 DETAILED WAVEFORMS Binning Sample Timing- Setup file: fle_dlis2k_9bit_bin01_1x.txt APP0002 Rev D.doc Page 27 7/10/2009

28 REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS Set Up File For Unified Demo Board/DLIS-4K: 9 Bit, 2X Binning Mode (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! <PERIOD,9999,0, 12600, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <reg_pwrcon,2,c0f0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,3e8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,4004,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,200,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 4226, 12458, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BINCNT_RESET,16,0, 300, 350, 3030, 3080, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PULLUP_DAC,48,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <AMPACT,72,1, 7680, 7800, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1, 50, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PRELOAD,160,0, 200, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER0,176,0, 3680, 3688, 7440, 7560, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER1,192,0, 3680, 3688, 7440, 7560, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST0,208,0, 1250, 1258, 7420, 7860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST1,224,0, 1250, 1258, 7420, 7860, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1260, 1770, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PLUS_CNT,272,1, 260, 3690, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <WRITEIN,288,1, 4222, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <TOGGLE,304,0, 272, 296, 2000, 2024, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <COUNTER_CLK,528,0, 200, 224, 1260, 1770, 3690, 4200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 4226, 12458, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EXTRA_CLK,640,0, 280, 288, 2008, 2016, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BIN_CLK,368,0, 350, 862, 1260, 1772, 3690, 4202, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> APP0002 Rev D.doc Page 28 7/10/2009

29 7.) High resolution readout CONCEPT The sensor features two adjacent rows of 4 micron square pixels with one of the rows offset by 2 microns. By reading out the two rows sequentially, the user can interpolate post process to achieve double the horizontal resolution provided by a single row of pixels. User can also read out both rows with overlapping integration to capture strobe events. CONCEPTUAL WAVEFORMS (Readout not shown full scale for clarity of acquisition timing. Readout typically adds 80-90% to single frame time) WRITE READOUT RAMP ROW RESET2 SHUTTER2 Sample Video0 Sample Background0 Exposure time Start for next Frame Row2 Exposure time Start for next Frame Row3 ROW RESET3 SHUTTER3 Sample Video1 Sample Background1 Photo-Diode Reset Photo-Diode Reset High Resolution (overlapping row integration) Sample Timing WRITE READOUT RAMP ROW RESET2 SHUTTER2 Sample Video0 Sample Background0 Exposure time Start for next Frame Row2 Exposure time Start for next Frame Row3 ROW RESET3 SHUTTER3 Sample Background1 Sample Video1 Photo-Diode Reset Photo-Diode Reset High Resolution (sequential row integration) Sample Timing APP0002 Rev D.doc Page 29 7/10/2009

30 DETAILED OPERATION In the high resolution mode, the user captures & reads out background and video value, and then repeats capture and readout on the second offset row before initiating the next external start pulse. User can program a rolling sequential scheme. Or program an overlapping scheme for strobed applications As in the default mode setup, the user must first initiate the start sequence (see CDS default mode section). The high resolution mode begins with the reading and storing the first row. The sense node charged to background level by programming a logic high to ROW_RESET signal for row2. Once the sense node is charged up to background level, the ROW_RESET2 signal goes low, immediately, the background ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count and the comparator compares background value with ramp and triggers the counter to store background values of the short integration row.. Before initiating a capture of the short integration row video values, the count mode must be switched- (see CDS default mode section). It is important to allow hold time of approximately 1 microsecond between successive background/video ramps, and background to video transition, to allow for settling of the DAC output. Once the first row background value is sampled and background ramp is complete, user can transfer photo-diode value from previous integration period. Integration period- (see CDS default mode section). Once SHUTTER2 has been pulsed logic high which transfers photo-diode value to sense node, SHUTTER2 signal is set low, video ramp generated by BIN_CNT_CLK plus COUNTER_CLK (counts that drive latches) starts counting from 1023-count. The comparator compares video value with video ramp and triggers the latches to store the DAC count of the first row video values. To program sequential row integration mode, reset the sense node & pixel by issue logic high to ROW_RESET2 and SHUTTER2 before capturing second offset row background and video values. To program in a overlapping integration mode, reset the sense node & pixel by issuing a logic high to ROW_RESET2 and SHUTTER2 after capturing second offset row background and video values. To capture background & video values for second offset row, the previous cycle to capture first row is repeated for ROW_RESET3 and SHUTTER3. Use combines both rows post process, to achieve high resolution output. DETAILED WAVEFORMS To be detailed in future firmware release APP0002 Rev D.doc Page 30 7/10/2009

31 REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS To be detailed in future firmware release APP0002 Rev D.doc Page 31 7/10/2009

32 8.) Auto Dynamic Threshold (ADT) CONCEPT ADT function is employed for binary output. The sensor can run in ADT mode when enabled. In this mode, two types of outputs are created: processed 10-bits video and 1-bit binary video. The 1-bit video is the result of a video threshold calculated by processed 10-bits video. In the ADT operation, the threshold for comparison is dynamically determined by the moving average of previous 4 or 8 pixels. The value can be the flat averages (1/4 or 1/8) or fixed weighted average. The weight values are as following, 4 Pixel Mode NewPixel = (Pixel[t-0] + Pixel[t-1] /2 + Pixel[t-2] /4 + Pixel[t-3] /8) /2 8 Pixel Mode NewPixel = ( Pixel[t-0] + Pixel[t-1] /2 + Pixel[t-2] /4 + Pixel[t-3] /8 + Pixel[t-4] /16 + Pixel[t-5] /32 + Pixel[t-6] /64 + Pixel[t-7] /128) /2 An adjustable Hysteresis (threshold) setting is used in ADT function to enhance the noise immunity. Eight Hysteresis values can be adjusted by SYSCON bits[2:0] as below: 000: 0 count 001: 4 count 010: 8 count 011: 16 count 100: 32 count (Default) 101: 64 count 110: 128 count 111: 256 count To get 10Bit digital threshold and 1Bit binary output user need to select 10 bit + 1bit Bout options from display mode pull down menu in Unified demo board GUI. 10-Bit Output 1-Bit Bout CONCEPTUAL WAVEFORMS Auto Dynamic Threshold can be invoke in combination with all available readout modes and no special timing is required DETAIL OPERATION A digital comparator compares outputs from the pixels and the ADT Processor to provide a result to BOUT pad. ADT output works as a dynamic threshold and user can select 4 or 8 pixel window (weighted, or unweighted)for threshold value. Use can select different Hysteresis settings for noise immunity. Default Hysteresis setting is +/-32 but can be increased to +/- 256 counts. The digital comparator compares the previous 4 or 8 pixel average to the current pixel value and APP0002 Rev D.doc Page 32 7/10/2009

33 compares if the current pixel value is above or below the average plus or minus a hysteresis value. If the current pixel is above the average plus a user programmed hysteresis value then a one is output. If the pixel value is below the average minus the hysteresis value than a zero is output to the BOUT (Binary OUT) pad. This calculated average becomes the digital threshold and can be outputted to the digital output pads in the upper 10 bits. REQUIRED MODIFICATIONS FROM DEFAULT GUI SETTINGS Set Up File For Unified Demo Board/DLIS-4K: 9 Bit (Settings Modified from default are bolded) <ECLIPSE_PANA09> #FORMAT IS #< NAME, TIMER-REGISTER-ADDRESS, INITIAL VALUE, EDGE#1, EDGE#2, EDGE#3, EDGE#4, EDGE#5, EDGE#6, EDGE#7, EDGE#8> # RESEVRED NAMES ARE BIAS,SWING,STEP,PERIOD,EOF # THE <ECLIPSE> MUST BE THE VERY FIRST LINE OF THIS FILE!! # THE <EOF> MUST BE THE VERY LAST LINE OF THIS FILE!! # USER PROGRAMMABLE HYSTERESIS FOR 1 BIT OUTPUT <HYST,9900,1,75, 110> <PERIOD,9999,0, 10800, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <reg_pwrcon,2,cofo,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_daccon,3,3c8c,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_syscon,4,da87,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_debug_con,5,77,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_opmode,7,8070,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <reg_sysconb,512,8002,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <DATAVALID,320,0, 2546, 10778, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BINCNT_RESET,16,0, 1200, 1228, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PULLUP_DAC,48,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <AMPACT,72,1, 5900, 6200, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0,0,0,0,0,0,,,,,,> <ZERORESET,80,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <FORCERESET,96,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ADT_RESET,112,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <RESET_Latch,144,1,50,100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <PRELOAD,160,0, 200, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER0,176,0, 2010, 2018, 6360, 6440, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <SHUTTER1,192,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER2,688,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <SHUTTER3,704,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST0,208,0, 1220, 1228, 6340, 6600, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <ROWRST1,224,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST2,720,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <ROWRST3,736,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,,,,,,> <MINUS_CNT,256,0, 1230, 1740, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <PLUS_CNT,272,1, 800, 2020, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <WRITEIN,288,1, 2542, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> APP0002 Rev D.doc Page 33 7/10/2009

34 <TOGGLE,304,0, 1098, 1122, 1862, 1886, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <COUNTER_CLK,528,0, 200, 240, 1230, 1740, 2020, 2530, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <READOUT,352,0, 2546, 10778, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EXTRA_CLK,640,0, 1106, 1114, 1870, 1878, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <BIN_CLK,368,0, 1230, 1742, 2020, 2532, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,,,,,,> <EOF> Advanced Options and Other Functions GAIN CONTROL & BIT DEPTH Multiple methods can be found for gain control for DLIS4k sensor. As described above, one easy access is to select the desired pins of 10 output bits. In DLIS4k, the ramp signal is generated using internal 12 bit DAC with adjustable reference voltages. For both Reference High and Low, 4 bits registers are used to control the reference value. By adjust 16 different voltage level of each signal, ramp range can be changed. Thus, the gain of the output can be adjusted. This function is controlled by register DACCON bits [4:11]. Besides reference voltage, the bits of ramp can also be adjusted form 8-bits to 12 bits. This is controlled by [12:14] bits of shift register DACCON. The lower bits selection results the smaller readout, which is equivalent to smaller gain but faster readout speed. On the other hand, the higher bits ramp results higher gain, but lower readout speed. PRELOAD A preload value can be applied to either or both background or video captures, the preload function can be initiated before or after background/video captures. Preload is typically initiated before background capture. The preload count is set to a default of 128 counts. The preload is effectively a digital offset applied to the resulting video value. The preload value is accomplished by issuing PRELOAD (active high) + COUNTER_CLK + PLUS_CNT or MINUS_CNT. Count mode is invoked by: TOGGLE (active high) overlapping EXTRA_CLK (active high) to change from a positive latched value PLUS_CNT to a negative latched value MINUS_CNT or visa versa, without corrupting held values in the latches. PLUS_CNT & MINUS_CNT are set logic high coincidentally with COUNTER_CLK which sets count direction and clocks in preload count values. Particular attention to count direction is essential to achieve desired offset. Programming note: MINUS_CNT, PLUS_CNT, TOGGLE may not be held high or overlap at the same time APP0002 Rev D.doc Page 34 7/10/2009

35 DLIS2k Timing requirements: Transfer Photodiode to Sense Node: Reset sense node: SHUTTER[3:0] 50ns ROW_RESET[3:0] 50ns Figure #6 Figure #7 Photodiode Reset: ROW_RESET[3:0] 220ns SHUTTER[3:0] T s 20ns 100ns T h 100ns Figure #8 End of Line: Amp_Activate 250ns 100ns Row_Reset T s 50ns T h 50ns Zero_Reset T s 50ns T h 50ns 100ns Figure #9 APP0002 Rev D.doc Page 35 7/10/2009

36 Propagation Delays: 12 Cycles-MCLK 2 Cycles-MCLK PD = 2ns 1 Fixed Delay from READ_OUT 2 Default Programming, delay can be set to count[nnnn] + PD 3 Cycles PIXCLK 1, 2 PD = 2ns Figure #10 APP0002 Rev D.doc Page 36 7/10/2009