Hewlett-Packard HDCS-2000 CMOS Image Sensor Circuit Analysis

Transcription

1 October 13, 2006 Hewlett-Packard HDCS-2000 CMOS Image Sensor Circuit Analysis Table of Contents Introduction... Page 1 List of Figures... Page 3 Device Summary Sheet... Page 11 Top Level Diagram...Tab 1 Analog Signal Path...Tab 2 ADCs and Parallel Data Output Path...Tab 3 Control Clocks...Tab 4 Reference & Biasing Generators...Tab 5 Test Circuitry...Tab 6 Signal Naming Conventions and Symbol Definitions...Tab 7 Signal Cross-Reference...Tab 8 Report Evaluation...Tab 9 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. Rev. 2.0

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3 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page 3 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture Sensor Cell Array Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions I Standard Cell Symbol Definitions II Standard Cell Symbol Definitions III Standard Cell Symbol Definitions IV Standard Cell Symbol Definitions IX Standard Cell Symbol Definitions V Standard Cell Symbol Definitions VI Standard Cell Symbol Definitions VII Standard Cell Symbol Definitions VIII Standard Cell Symbol Definitions X Standard Cell Symbol Definitions XI

4 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Top Level Diagram Sensor Pixel Array Analog Signal Path Analog Row Buffer Row Buffer Pair Row Buffer Bias & CMFB Bias Generator II & CMFB Bias Generator I Programmable Gain Amplifier (PGA) Op Amp I Programmable Capacitor PGA & Row Buffer Switch Control Row Buffer Switch Control PGA Switch Control Input Reference Signals Switches Output Buffers I Output Buffers II ADCs and Parallel Data Output Path Analog-to-Digital Converter ADC Resolution Decoder State Decoder ADC Sequencer Logic ADC Sequencer Logic I ADC Sequencer Logic II DAC Logic ADC Output Logic R Switch Decoder C Switch Decoder Capacitor Ladder

5 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page ADC Comparator Comparator Bias Comparator Stage I Comparator Stage II Comparator Stage III Comparator Stage IV Programmable VREF Divider RGB Averaging Register RGB Averaging Logic ADC Data Switches Direct/Round Up Data Converter Saturation Mode Data Converter Parallel Data Output Register Data Output Buffers I/O Buffer I Test Mode Clock Buffers Control Clocks Serial Interface Interface Mode Control Serial Data Input Synchronous Mode Control Serial Interface Control State Machine UART Mode Control Counter UART Baud Rate Counter UART Bit Time Counter UART Mode Data Input Register Set Programming Sequencer Register Programming Decoder Main Register Device Address Detector Register Data Transfer Enable

6 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Register Address Generator Register Address Counter Register Address Predecoder Register Address Decoder Parallel to Serial Converter Parallel to Serial Bit [7] Parallel to Serial Bit [6] Parallel to Serial Bit [5] Parallel to Serial Bit [4] Parallel to Serial Bit [3] Parallel to Serial Bit [2] Parallel to Serial Bit [1] Parallel to Serial Bit [0] Parallel to Serial Shift Register Serial Data Output Register Set Identification Register Status Register Interrupt Mask Register Pad Control Register Pad Drive Control Register Interface Control Register Interface Timing Register Baud Fraction Register Baud Rate Register ADC Control Register First Window Row Register First Window Column Register Last Window Row Register Last Window Column Register Timing Control Register Even Row, Even Column PGA Gain Register

7 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Even Row, Odd Column PGA Gain Register Odd Row, Even Column PGA Gain Register Odd Row, Odd Column PGA Gain Register Even Channel PGA Gain Register Odd Channel PGA Gain Register Row Exposure Low Register Row Exposure High Register Sub-Row Exposure Low Register Sub-Row Exposure High Register Configuration Register Control Register Register Register Register Register Register Register Register Register Set Decoders Pad Drive Control Decoder Baud Rate Decoder Register Data Combiner Main Control Sequencer Row Processing Sequencer Row Exposure Timer Counter Cell Timer I Overflow Detector Sub-Row Exposure Timer Counter Cell Counter Cell Timer II Overflow Detector Sub-Row Exposure Timer Control

8 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Exposure Control State Machine I Exposure Control State Machine II Row Sample/Reset Control I Row Sample/Reset Control II Exposure Registers [00] Detector bit Reverse Counter Main State Machine Exposure Duration Control Intermediate Logic Intermediate Control I Intermediate Control II Intermediate Control III Row Address Counter Control Column Processing Sequencer PGA Sample Duration Counter Column Processing State Machine Column Sampling Register Image Capture Status Shutter Sync Status Row Address Generator Row Address Counter Cells Row Address Increment Logic Row Predecoder Row Decoder Last Row Address Comparator Column Address Generator Column Address Counter Column Address Counter Cell Column Address Counter Cell Column Address Counter Cell Column Predecoder Column Decoder

9 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Last Column Address Comparator Status Signals Generator Image Processing Status nrow Generator nframe_nsync Generator nirq_ncc Generator I/O Buffer II Parallel Interface Control Data Setup/Hold Cycle Counter Data Setup/Hold State Control ADC Activity Detector Output Switch and Register Control System Reset/Standby Control Reset Signal Buffers System Clock Input Hard Wires Reference & Biasing Generators Bandgap Reference Generator Op Amp III Reference Voltage Amplifier Voltage Buffer I Voltage Buffer II Common Mode Reference Generator Biasing Current Sources Op Amp II Test Circuitry Row Address Test Row Address Test Output Test Signals Generator Column Address Test

10 Hewlett-Packard HDCS-2000 CMOS Image Sensor Page Test Test Test Test Test Test Test Test Test 10 A.1.0 Symbol Conventions A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation

11 Hewlett-Packard HDCS-2000 CMOS Image Sensor Report Evaluation We value your business relationship at Chipworks. Your feedback is very important to help us better serve your future needs. Please take a few minutes to complete this evaluation to let us know if you were satisfied with this report. The information you provide will be used to strengthen our service quality program. Please rate Chipworks on this report at the following: On-Line Evaluation Form Or use the attached Report Evaluation Fax Back version on the next page. Rev. 2.June 25, 2001 CAR