High Performance Computing

Transcription

1 High Performance Computing CS701 and IS860 Basavaraj Talawar

2 Course Syllabus Definition, RISC ISA, RISC Pipeline, Performance Quantification Instruction Level Parallelism Pipeline Hazards, Combating hazards, Scheduling, Branch Prediction, Superscalar Processors, Out-of- Order execution Memory hierarchy VLIW, Vector Processors Data Parallelism GPU Interconnection Networks Topics of current research

3 Course Structure Textbook John Hennessy and David Patterson, Computer Architecture, A Quantitative Approach, MK, 5ed. References Shen & Lipasti, Modern Processor Design About Course 2 assignments (before midterm) 15% Course Project (after midterm) 25% Midsem 20%, Final Exam 40% Guest Lectures Compilers, Memory Hierarchy, GPU

4 Course Objective Identify the trade-offs involved in designing a multiprocessor Why? Improve the execution time of our programs.

5 Computer Architecture Definition Specific requirements of the target machine ISA design Cache and memory hierarchy I/O, storage, disk Multi-processors, networked systems Max performance, within constraints: cost, power, availability

6 Computer Architecture Application Algorithm Programming Language Operating System/Virtual Machines Instruction Set Architecture Microarchitecture Register-Transfer Level Gates Circuits Devices Physics Computer architecture is the design of the abstraction/implement ation layers that allow us to execute information processing applications efficiently using manufacturing technologies David Wentzlaff, ELE 475 Computer Architecture, Princeton University

7 Wikipedia: Moore's Law

8 Single Processor Performance Move to multi-processor RISC Hennessy & Patterson, CA-QA, 5ed. MK, 2013

9 Architecture vs. Microarchitecture Architecture Instruction Set Architecture Programmer visible state (Memory & Register) Operations (Instructions and how they work) Execution Semantics (interrupts) Input/Output Data Types/Sizes Microarchitecture/Organization: Tradeoffs on how to implement ISA for some metric (Speed, Energy, Cost) Examples: Pipeline depth, number of pipelines, cache size, silicon area, peak power, execution ordering, bus widths, ALU widths

10 Same Architecture, Different Microarchitectures AMD Athlon II X4 Intel Atom X86 Instruction Set, Quad Core, Out-of-order, 2.9GHz, 125W Decode 3 Instructions/Cycle/Core 64KB L1 I Cache, 64KB L1 D Cache, 512KB L2 Cache X86 Instruction Set, Single Core, In-order, 1.6GHz, 2W Decode 2 Instructions/Cycle /Core 32KB L1 I Cache, 24KB L1 D Cache, 512KB L2 Cache David Wentzlaff, ELE 475 Computer Architecture, Princeton University

11 Different Architectures, Organizations AMD Vishera IBM POWER 8 X86 ISA 8 Core, 4.7 GHz, 125W 64KB L1Cache, 2MB L2 Cache, 8MB L3 Power ISA 12 cores, 4.5GHz, 250W 64KB L1Cache, 512KB L2 Cache, 8MB L3.

12 Coming up Processor Performance Machine Models

13 Concept of Time and Speed Frequency: Number of occurrences of a repeating event per unit time. SI unit: Hertz (Hz) The period is the duration of one cycle in a repeating event Period = Cycle time Cycle Time= 1 Frequency

14 On Processor Performance How is frequency related to performance? Program ExecutionTime = Execution Time per Instruction Total Program Instructions CPU Time=Execution Time per Instruction Instruction Count Execution Time per Instruction= Cycles spent per Instruction Cycle Time CPU Time= IC Cycles per Instruction Cycle Time Example What is is the execution time of of a program containing a million Instructions each occupying 4 cycles in in a 2 GHz processor?

15 Iron Law of Processor Performance CPU Time= IC Cycles per Instruction Cycle Time Time per Cycle= 1 Frequency CPU time= Instructions Program cycles Clock Instruction Seconds Clock cycle n CPI = i =1 IC i InstructionCount CPI i

16 On Processor Performance CPU time= Instructions Program cycles Clock Instruction Seconds Clock cycle COMPILER ARCHITECTURE AND ORGANIZATION

17 $gcc hello.c The GNU C Compiler The compiler and its working: Guest lecture by Dr. Janakiraman, IBM, August 2

18 Pipelining Recap Where do operands come from and where do results go?

19 PROCESSOR Operations and Operands Register File i1 i2 ALU Control o Memory

20 STACK Machine Models REGISTOR-MEMORY REGISTER-REGISTER ACCUMULATOR TOS ALU ALU ALU ALU

21 C = A + B STACK ACCUMULATOR REGISTOR-MEMORY REGISTER-REGISTER TOS ALU ALU ALU ALU Push A Push B Add Pop C Load A Add B Store C Load R1, A Add R3, R1, B Store R3, C Load R1, A Load R2, B Add R3, R1, R2 Store R3, C

22 Machine Models Comparison Number of explicitly named operands Number of instructions that can access data from memory Code size Amount of data transferred between memory and processor Complexity of hardware Ease of compilation (ease of generation of machine code).

23 Example The Stack Machine Model How is is the expression x = (a*b)+(c- (d/e) evaluated on a stack based machine? What is the sequence of instructions? Convert the equation to its Reverse Polish Notation form. ab*cde/-*

24 The Stack Machine Model Evaluate ab*cde/- on a stack based machine 0xFF 0xFE 0x06 0x05 0x04 0x03 0x02 0x01 0x00 STACK MEMORY a b c d de dx What is is the minimum size of of the stack required to to evaluate this expression?

25 Class Work Example Example For each machine model, write a code sequence to to evaluate the following expressions. b=a 3 +3 a 2 +2 a +7 c= x 3 +3 a 2 +2 b+7 For each machine model, what is is the (a) total instructions in in the code sequence, (b) Execution time in in clock cycles, (c) CPI? Given: Load, store, arithmetic and logic tasks take 1 cycle. Multiply completes in in 4 clock cycles.