APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS

Transcription

1 APPLICATION NOTE PACE175AE BUILT-IN UNCTIONS About This Note This applicatio brief is iteded to explai ad demostrate the use of the special fuctios that are built ito the PACE175AE processor. These powerful Built-I uctios (BIs) are above ad beyod the capabilities of the MIL- STD-175A istructio set, but are allowed by MIL-STD-175A as optios to ehace the performace of 175A processors i specialized applicatios. The desig of the PACE175AE is based o its successful high-performace predecessor, the PACE175A, ad is i fact pi ad software compatible with that part. However, certai architectural ehacemets allow the PACE175AE to gai a percet throughput icrease over the PACE175A at ay give clock frequecy, up to MHz, as measured o the DAIS istructio mix. The most sigificat of these ehacemets is the additio of a multiply accumulate array capable of completig a sigle precisio iteger (16-bit x 16-bit) or sigle precisio floatig poit (2-bit x 2-bit) multiply accumulate operatio i just two clocks. Besides improvig the performace of the iteger ad floatig poit arithmetic by as much as 7 percet over the PACE175A, the multiply accumulate array gave the desigers of the PACE175AE a importat buildig block from which to create the very powerful BIs that are the subject of this ote. I additio to the fuctios which utilize the multiply accumulate array, there are fuctios which improve the usefuless of the A ad B timers, ad a block move i the I/O address space which greatly improves the speed at which the memory map ca be chaged. These fuctios combied ca offer a sigificat improvemet i the system performace of the PACE175AE processor family i may typical embedded applicatios. DSP uctios The P175AE device icorporates a series of fuctios, utilizig the multiply accumulate array, iteded to vastly improve performace o the operatios most used i digital sigal processig applicatios. With the additio of these fuctios, the P175AE is able to perform some of the basic DSP fuctios with speeds rivalig those of may of the dedicated DSP processors curretly available. All of these fuctios utilize iput data i sigle or double precisio iteger format ad provide results i a double precisio iteger format or i a special 8-bit iteger format for improved accuracy. These istructios may be used i a wide variety of applicatios, icludig IR filters, covolutio, correlatio ad matrix multiplicatio. A IR filter implemeted usig the VDPS will execute i 8 clocks per tap. or the commoly used 3 x 3 matrix operatios (graphics, coordiate trasformatio, Euler rotatios, etc.) a special register based BI is provided. It will compute a 3 x 3 colum/row multiplicatio i oly 6 clocks. Descriptios of each of these fuctios are provided i the followig paragraphs. I all cases, for calculatig the effects of wait states, WD is the umber of data wait states used ad WI is the umber of istructio wait states used. Revised October 25

2 PACE175AE BUILT-IN UNCTIONS Parametric Memory to Memory Vector Dot Product (16-bit data, 32-bit result) VDPS RA uctio: Acc( : 31) Acc( : 31) + i= 1 Mi( :15) Ni( :15) CPU Registers Memory RA RA + 1 RA + 2 = M1 M2 M N1 N2 N The VDPS istructio computes the vector dot product of two 16-bit memory arrays. The address of the first elemet of the first vector must be placed i register RA, the address of the first elemet of the secod vector must be placed i register RA+1 ad the umber of elemets i each vector () must be placed i register RA+2. Whe executio begis, each elemet of the first vector is multiplied with the correspodig elemet of the secod vector ad the 32- bit result added to the accumulator. Whe executio is complete, the value i RA+2 will have chaged to zero ad the result will be stored i the accumulator, which ca be accessed via the STAC commad, to be discussed later. Overflowig the accumulator will result i the ixed-poit Overflow iterrupt. 1 + (8 ) clocks ( wait states) lags Affected: (WI-6) + (WD 2) additioal clocks P, Z, N Page 2 of 15

3 PACE 175AE BUILT-IN UNCTIONS Parametric Memory to Memory Dot Product (32-bit data, 8-bit result) VDPD RA uctio: Acc( : 7) Acc( : 7) + i= 1 Mi( :31) Ni( :31) CPU Registers Memory RA RA + 1 RA + 2 = M1(:15) M1(16:31) M2(:15) M2(16:31) 2 M(:15) M(16:31) N1(:15) N1(16:31) N2(:15) N2(16:31) 2 N(:15) N(16:31) The VDPD istructio computes the vector dot product of two 32 bit memory arrays. The address of the first elemet of the first vector must be placed i register RA, the address of the first elemet of the secod i RA+1 ad the umber of elemets i each vector i RA+2. The 32 bit elemets must be placed i two adjacet memory locatios with the most sigificat 16 bits residig i the memory locatio with the lower address. Both vectors must reside withi the same address state (if a MMU is used). Whe executio is complete, the cotets of register RA+2 will be zero ad the result will be i the 8-bit accumulator. There will be o iterrupt geerated o a overflow. lags Affected: clocks (WI-6) + (WD ) additioal clocks Page 3 of 15

4 PACE175AE BUILT-IN UNCTIONS 3 X 3 Register Dot Product (16-bit data, 32-bit result) R3DP uctio: Acc ( : 31) Acc( : 31) + ( R R3) + ( R1 R) + ( R2 R5) R R1 R2 CPU Registers R3 R R5 The R3DP istructio computes the dot product of the two 16-bit 3-elemet vectors formed by registers R-R2 ad R3- R5. R-R2 cotai the elemets of the first vector ad R3-R5 cotai the elemets of the secod vector. The 32-bit result is placed i the accumulator. A overflow of the accumulator will cause a ixed-poit Overflow Iterrupt to occur. logs Affected: 6 clocks (WI-2) additioal clocks Page of 15

5 PACE 175AE BUILT-IN UNCTIONS Double Precisio Multiply/Accumulate (32-bit data, 8-bit result) MACD uctio: Acc ( : 7) Acc( : 7) + ( R, R1) ( R2, R3) CPU Registers R R1 R2 R3 The MACD istructio is the basic double precisio multiply ad accumulate fuctio. It performs a 32-bit multiply of the data i two register pairs, R-R1 ad R2-R3, ad adds the 8-bit result to the value i the accumulator. The most sigificat 16 bits of the data to be multiplied must be placed i R for the first operad ad R2 for the secod, ad the least sigificat 16 bits must be placed i R1 ad R3. A overflow of the accumulator will ot cause a iterrupt to the processor. 8 clocks (WI-) additioal clocks 1 lags 2 Affected: Page 5 of 15

6 PACE175AE BUILT-IN UNCTIONS Trascedetal uctios The P175AE implemets a polyomial evaluatio BI which may be used to evaluate ay fuctio which may be expressed as a series expasio. This icludes fuctios such as sie, cosie, atural log, ad may others. The use of the POLY BI results i a sigificat performace improvemet over the calculatio of these fuctios with idividual multiply ad add istructios. Polyomial POLY uctio: Acc( : 31) i= A X CPU Registers Memory R R1 R2 = x = A A-1 A-2 +1 A The POLY istructio evaluates the polyomial of degree defied by the registers ad memory as depicted above. The values of X ad the costats A -A are represeted as u-ormalized 16-bit two s complemet fractios providig a rage i value of -1<X<1. The most sigificat bit is a sig bit, ad the remaiig 15 bits represet the fixed poit fractio. The result is represeted as a u-ormalized 2-bit two s complemet fractio, providig icreased accuracy. The address of A must be placed i register R, the value of X must be placed i R1 ad the value of, the degree of the polyomial, must be placed i R2. The coefficiets of the polyomial must be placed i memory with A i the first address ad A -1 through A followig i ascedig addresses. A overflow of the accumulator will ot cause a iterrupt to the processor. lags Affected: 6(+1)+8 clocks (WD(+1))+WI additioal clocks Page 6 of 15

7 PACE 175AE BUILT-IN UNCTIONS Example: Usig the POLY to evaluate SIN X The POLY istructio leds itself well to the evaluatio of fuctios which may be expaded ito series represetatios. Oe such fuctio is si x, which may be expaded ito the Taylor Series represeted below with x equal to the value of a agle i radias: ( 1 ) si x = = ( 1) x x x x = x + + (2 + 1)! 3! 5! 7! 5 7 This may be reorgaized ito the followig equatio: 2 ( 2 ) si x = A + A x + A x + A x + A x + A x + A x + A x which is the format accepted by the POLY istructio. Sice the series is ifiite, with icreasig accuracy for each additioal term, the particular umber of terms required for a acceptable error must be determied. It ca be show that for -1<x<1, a error of less tha.2 percet may be achieved by usig just four of the terms of equatio (1), which is acceptable i most applicatios. It is actually ot possible to use ay more tha four terms for the sie calculatio usig the POLY istructio sice the ext costat required (1/9!) is too small i magitude to represet as a 16-bit fixed poit fractio. Thus, the followig equatio will be used to approximate the sie fuctio: ( 3 ) x x x si x = x + 3! 5! 7! A1 x + A2 x + A3 x + A x + A5 x + A6 x A7 x = A + where: A = A = A 1 = 1 = 7 (hex) A 5 = 1/5! = 111 (hex) A 2 = A 6 = A 3 = -1/3! = EAAA (hex) A 7 = -1/7! = A (hex) Sice the above costats may oly be etered as 16-bit fractios, some additioal error is itroduced, but the accuracy of the result is still very reasoable, as this example will show. To calculate the value of si x with x =.75 radias (2.97 ) the followig must be performed: 1. Place the costats i the memory. (I this example, address (hex) is chose as the startig address) Address Data Address Data A EAAA Page 7 of 15

8 PACE175AE BUILT-IN UNCTIONS 2. Execute the followig program: LIM R, ; Load startig address of costat table LIM R1, 6 ; Load the value of x (.75) LIM R2, 7 ; Load the value of POLY ; Execute the POLY istructio 3. The result is i the accumulator ad may be retrieved as described later i this ote. or this example, the result is 573E3 (hex) which traslates to decimal. The actual value of si.75 is , resultig i a error of. percet. I the example above, the POLY istructio executes i 56 clocks. If the same fuctio were performed usig idividual multiply ad add istructios with greater tha 16 bits of precisio, the calculatio would require double precisio iteger register multiplies (36 clocks), 1 sigle precisio iteger memory multiply with 32-bit product (13 clocks) ad 3 double precisio iteger memory additios (8 clocks) for a total of 97 clocks. Thus, the POLY istructio calculates the sie fuctio 2 percet faster tha the discrete istructios. If floatig poit accuracy is required, the floatig poit adds ad multiplies must be used. The limitatios o the value of x require that some preprocessig of the data be performed before the POLY is executed. or values of x greater tha 1, the relatioships show below ca be of help: si x = cos (x-π/2) cos x = -si (x-π/2) si x = si (x-2π) cos x = cos (x-2π) uctios other tha sie may be evaluated by the POLY as well. Ay fuctio which may be expaded ito a series may be evaluated, however, for suitable accuracy the series must coverge rather quickly. The series approximatig some importat fuctio are show below: cos x = = ( 1) 2 2 x x x x = (2)! 2!! 6! 6 e x = = x! 2 x x x = 1+ x ! 3!! 3 Page 8 of 15

9 PACE 175AE BUILT-IN UNCTIONS Accumulator Maipulatio The PACE175AE provides a group of istructios to allow complete access to the 8-bit accumulator used i the BIs described above. This provides the user the flexibility to use the multiply/accumulate array to supplemet the performace of may custom applicatios. These istructios are described below: Clear Accumulator CLAC uctio: Acc( : 7) The 8-bit accumulator is loaded with. No registers are affected. clocks lags affected: WI additioal clocks Store Accumulator ito R, R STA Op code: uctio: R, R1 Acc( : 31) The most sigificat 32 bits of the accumulator are placed i the R,R1 register pair. The most sigificat 16 bits are placed i R ad the least sigificat 16 bits are placed i R1. lags Affected: 7 clocks (WI 3) additioal clocks Page 9 of 15

10 PACE175AE BUILT-IN UNCTIONS Store Accumulator Log ito R,R1,R2 STAL Op Code: uctio: R, R1, R2 Acc( : 7) The 8-bit accumulator is placed i the three register group, R,R1,R2. The most sigificat 16 bits are placed i R, ad the least sigificat 16 bits are placed i R2. lags Affected: 1 clocks (WI 6) additioal clocks Load Accumulator LAC uctio: The most sigificat 32 bits of the accumulator are loaded with the data cotaied i the register pair R ad R1. The most sigificat 16 bits are loaded from R ad the least sigificat from R1. lags Affected: 1 clocks (WI 6) additioal clocks Page 1 of 15

11 PACE 175AE BUILT-IN UNCTIONS Load Accumulator Log LACL uctio: Acc( : 7) R, R1, R2 The 8-bit accumulator is loaded with the cotets of the register group R,R1,R2. The most sigificat 16 bits are loaded from R ad the least sigificat 16 bits are loaded from R2. lags Affected: 9 clocks (WI 5) additioal clocks Timers 1 The A ad B timers are specified by MIL-STD-175A as optios which are implemeted by the PACE175AE. These timers 2 are iteded 3 to provide 5 periodic 6 7iterrupts 8 to 9the applicatio 1 11 software 12 for 13real time 1 operatio. 15 The ca be loaded (via XIO istructios) with a value from which to cout upward util reachig the value (hex), at which time they 7 roll over to ad geerate a iterrupt to the processor. rom this poit they will cotiue coutig up toward (hex) agai, uless loaded with a differet value. Thus, if a periodic iterrupt is desired with a period of less tha 65,536 couts, the timer must be reloaded after each iterrupt with a cout value other tha zero. The PACE175AE cotais two additioal registers, called reset registers, which may cotai a value differet tha zero for the timers to cout up from after reachig their termial couts. This provides a very simple method of creatig periodic real time iterrupts with ay period. The user must simply program each register oce to set the iterrupt period, after which the iterrupts will occur regularly util a differet value is writte ito oe of the registers. These two registers default to zero upo power-up, meaig that if they are ever chaged, full compatibility with the software developed for the PACE175AE ad other machies is maitaied. The registers are loaded by the BIs described below, but caot be read. Page 11 of 15

12 PACE175AE BUILT-IN UNCTIONS Load Timer A Reset Register LTAR uctio: TAR R The Timer A Reset Register is loaded with the value cotaied i R. Timer A will cout up util reachig (hex). The, o the ext cout, the timer will be loaded with the value i the reset register where it will begi coutig up. Timer A will cotiue to begi with the reset value after each termial cout util a ew value is loaded ito the reset register. To retur to the ormal MIL-STD-175A operatio mode, the reset register must be loaded with zero. No other timer fuctios are chaged. The default value at power o ad after each hardware reset is zero. Load Timer B Reset Register LTBR E uctio: The Timer B Reset Register is loaded with the value cotaied i R. Timer B will cout up util reachig (hex). The, o the ext cout, the timer will be loaded with the value i the reset register where it will begi coutig up. Timer B will cotiue to begi with the reset value after each termial cout util a ew value is loaded ito the reset register. To retur to the ormal MIL-STD-175A operatio mode, the reset register must be loaded with zero. No other timer fuctios are chaged. The default value at power o ad after each hardware reset is zero. lags Affected: clocks WI additioal clocks Page 12 of 15

13 PACE 175AE BUILT-IN UNCTIONS Iput/Output Speed Improvemet Oe factor which limits the performace of 175A systems is the large overhead associated with the XIO istructio. Sice this istructio is defied as privileged by MIL-STD-175A, there are special steps which must be take by the microcode each time a XIO or VIO istructio is ecoutered. This causes the legth of the XIO istructio to be 2 to 3 clocks, depedig o whether a output or a iput is to be performed, eve though the actual I/O bus cycle is oly clocks. This ca restrict performace whe large blocks of data must be trasferred from memory to I/O devices, such as durig loads of the MMU page registers. The PACE175AE provides a ew istructio which allows a quick write of large blocks of data from memory to the I/ O space. The privileged istructio overhead must be performed oly oce i this istructio. Thus, the overhead pealty is paid up frot, ad the icremetal executio time is oly 8 clocks per data trasfer. I the case of the MMU page register load, if the complete set of istructio ad operad page registers is loaded usig XIO output istructios, a total of 512 XIO istructios must be executed at 2 clocks each. I additio to the XIOs, 512 Load Register from Memory istructios must be performed to place the data to be trasferred ito registers where it may be output by the XIO istructios. These istructios require 12 clocks each. Thus, the total executio time is 18,32 clocks. The same task performed by the IOMV BI would execute i,118 clocks a 78 percet improvemet. The IOMV istructio is described below. Block Move Memory to I/O IOMV uctio: See diagram, ext page. The memory block begiig at the address stored i R2 is moved to the I/O block begiig at the address stored i R. The umber of data words to be trasferred is stored i R1. The maximum trasfer size is 32,768, which is the umber of legal I/O output addresses. All memory data must reside withi the same address state if MMU is used. lags Affected: (22 + 8) clocks WI + 2(WD) Additioal clocks Page 13 of 15

14 PACE175AE BUILT-IN UNCTIONS CPU Registers R R1 R2 = I/O I/O1 I/O2 I/O3 I/O I/O Memory M1 M2 M3 M M Coclusio Though the PACE175AE provides a sigificat improvemet over the PACE175A o existig software, the fullest potetial of the processor may be obtaied oly by makig use of the BI istructios. Depedig o the tasks performed by the applicatio software, substatial improvemet i the system performace of the 175AE may be achieved through the use of the BIs. System performace i embedded cotrol applicatios was our goal whe desigig the PACE175AE, ad we believe that the BIs are just oe of the ehacemets which allowed us, ad you, to achieve that goal. Page 1 of 15

15 PACE 175AE BUILT-IN UNCTIONS REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: ANP16-3 APPLICATION NOTE - P175AE BUILT-IN UNCTIONS REV. ISSUE DATE ORIG. O CHANGE DESCRIPTION O CHANGE ORIG May-89 RKK New Data Sheet A Oct-5 JDB Added Pyramid logo Page 15 of 15