Optimizing High-Speed Digital Channels Using State-of-the-art Signal Integrity Tools

Transcription

1 Optimizing High-Speed Digital Channels Using State-of-the-art Signal Integrity Tools

2 2 Welcome and Agenda Time Agenda Presenter 9:00-9:30 Registration & Continental Breakfast 9:30-10:00 Welcome and keynote presentation - A methodology for predictable design closure in the high-speed digital era Dr. Colin Warwick 10:00 11:00 Anticipate SI issues on your High Speed Digital PCBs using Virtual Prototypes and Advanced Channel Simulation for early evaluation and optimization of design trade-offs 11:00 12:00 De-Mystifying the 28 Gb/s PCB Channel: Design to Measurement 12:00 1:00 Lunch 1:00 2:00 How to characterize and debug high-speed digital links on your physical prototype. What part of your design is eating up your eye margins? 2:00 3:00 Breakthrough Developments in TDR/TDT Measurement Technology Dr. Colin Warwick Patrick Riffault, Xilinx George Crumrine Kevin Kershner Kevin Kershner 3:00 3:30 Question & Answer Giveaway 2014 Agilent Technologies

3 3 Speaker Bios Colin Warwick is high speed digital product manager at Agilent EEsof EDA, where he is focused on multigigabit per second design and analysis tools. Prior to joining Agilent, Colin was with Royal Signals and Radar Establishment in Malvern, England, Bell Labs in Holmdel, NJ, and The MathWorks in Natick, MA. He completed his bachelor, masters, and doctorate degrees in physics at the University of Oxford, England. He has published over 50 technical articles and holds thirteen patents. George Crumrine received his BSEE from the University of Cincinnati, and has been involved in the RF/uW industry for 30 years. He has been with HP/Agilent for 25 years, including 20 years as an Applications Engineer with the EEsof EDA group. Patrick Riffault is the Staff High Speed IO specialist at Xilinx. Patrick holds a BSEE and has been involved in the High Speed SERDES design and EDA analysis for more than 30 years. He has been with Xilinx for 5 years and has held positions at Altera, Cisco, Cadence and ATI prior to joining Xilinx.. Kevin Kershner received his BSEE from UCLA in 2005, with a focus on computer architecture. He has since been working for Agilent Technologies in a variety of roles, all focused on highspeed digital and embedded system validation. Areas of expertise include Physical Layer and Functional validation of DDR memory, PCIe, and USB interfaces Agilent Technologies

4 When Separated, Agilent s EM Business will be named Page 4

5 QUESTIONS? Agilent Technologies Page 5

6 Additional Resources If you have a current need for a signal integrity solution, you can request a quick quote, contact your field engineer, or call the Agilent Customer Care Center at the numbers below: integrit 6 United States: Agilent Technologies Canada:

7 7 High Speed Digital Design and Verification See the Cliff Edge (Or: A methodology for predictable design closure in the high speed digital era)

8 Keynote Agenda Why are we here? Methodologies for design and verification of HSD designs From Simulation to Compliance test Summary

9 Interconnect goes serial, fast, and multi-standard What are your companies business drivers? Reduce cost Faster time to market More features Higher speed Increase density Reduce power consumption More robust USB 3.0 HDMI DVI DP PCIe 3.0 SATA DDR3 4.8 Gb/s 5 Gb/s 8 Gb/s 8.6 Gb/s 5 Gb/s 3 Gb/s Gb/s

10 10 Interconnect goes Optical! What are your companies business drivers? Higher speed More robust Increase density Reduce power consumption More features Faster time to market Reduce cost

11 Signal Integrity is critical Source Signal Channel Response Received signal

12 Protocol is now of secondary importance I say old chap does one fancy a Do what? beer?

13 Signal Integrity engineering challenges Need microwave techniques to prevent eye closure and BER For 60 cm 1Gb/s flight time ~ 4ns bit period = 1ns Tx Output impedance ~50 Interconnect impedance ~50 RX Input impedance ~50 Implies 4 bits in transit = No time for reflections: Match impedances But Impedance problems are everywhere Backplanes Connectors PC Boards/DIMMS IC Packages / DDR Cables

14 HS PCB challenges Cost/Performance trade off FR4 is common, low cost and easy to manufacture BUT at multi GB/s it s like wet string! Gb/s 6.25 Gb/s 12.5 Gb/s

15 Introducing the cliff edge!

16 See the cliff edge - Speed and power margins

17 Keynote Agenda Why are we here? Methodologies for design and verification of HSD designs From Simulation to Compliance test Summary

18 Why don t our designs work first time? Are we done yet? System Design Interconnect Design Analysis Debug Compliance Test

19 What were the HSD Challenges on Your Last Design? Inherent jitter/noise of test equipment meant wasted design margins SI issues or lack of margin visibility (eg. Jitter, collapsed "eyes") Power Integrity (eg. Rail bounce, ground plane instability) EMI / EMC Source 2013 EMEA HSD seminars. Missing skills /"know-how" on HSD design Lack of simulation models and/ or accuracy Problems probing signals 2/3rds of last designs required 1 or more respins due to SI issues Data size: 411 respondents

20 The business issues Cost of a prototype respin: Cost of proto board build = $10k x 100 = $1M Extra Engineering time (2 months) = $100k/yr x 2 mths x 10 people = $170k Additional emergency test equipment rental = $ 200k Total $1.4M. Time to Market (TTM) Cost of being late: Risk: Are we done testing? How do we know? Can we fulfil compliance test? What happens after 1M units of component variation?

21 What were the HSD Challenges on Your Last Design? Inherent jitter/noise of test equipment meant wasted design margins SI issues or lack of margin visibility (eg. Jitter, collapsed "eyes") Power Integrity (eg. Rail bounce, ground plane instability) Missing skills /"know-how" on HSD design Lack of simulation models and/ or accuracy Problems probing signals

22 Agilent HSD solution for predictable design closure System Design Interconnect Design Active Signal Analysis Compliance Test Build accurate Models Accurate Simulation Refine Models & Simulations Accurate Design Analysis Correlation Accurate Design Analysis Measurement Automation Debug Correlation Stress test Protocol test Measurement Automation Compliance HSD Design: To optimise mutually exclusive cost, power consumption and robustness tradeoffs HSD Lab Verification: To prove trade-off decisions through margin analysis and compliance test

23 Channel Simulation with Agilent ADS Fast to Extremely Fast AND Accurate Waveforms/BER/Bathtubs Electrical & Optical S-parameters from EM/ VNA/ TDR/ LCA Easy to explore DSP vs. Channel

24 The importance of accurate Measurement Measurement system contribution Easier correlation! + Your competitive advantage! Safe design margin

25 SPI th IEEE Workshop on Signal and Power Integrity Paris (Correlation example)

26 Effect of predictable design closure Target spec. eg. BER, power, cost x x x x x x Bigger risk margin TTM saving Build visibility of cliff edge through Virtual Prototype. Target power/ cost /speed /robustness Development time Typical HW Prototype only design process Virtual and Physical prototype process

27 Why Did Cisco Choose ADS For Signal Integrity? Our systems include multi-gigabit per second chip-to-chip serial links across PCBs and backplanes. We selected ADS because it lets us couple simulations at the channel-, circuit-, and physical-levels with measured data from the instruments. The resulting workflow requires fewer respins of the physical prototypes. We get fewer unwanted surprises, and get to market quicker. -- Straty Argyrakis, CPP Integrity Engineer, Cisco Systems

28 What were the HSD Challenges on Your Last Design? Inherent jitter/noise of test equipment meant wasted design margins SI issues or lack of margin visibility (eg. Jitter, collapsed "eyes") Power Integrity (eg. Rail bounce, ground plane instability) Missing skills /"know-how" on HSD design Lack of simulation models and/ or accuracy Problems probing signals

29 The importance of accurate Models Component Models (IC Interface & Physical Channel) Simulation Engine Simulated Performance IC Models Connector / Cable Models PCB Models IBIS Encrypted Hspice IBIS AMI Verilog AMS S-param Models Mechanical data Materials data S-param Models PCB Layout data Materials/Stack-up data

30 Increasing Accuracy Creating accurate S-parameter Models Pre-Layout Simulation Model - Based on Analytic or Simple 2D EM Based Post-Layout Simulation Model Based on EM Simulation Post Manufacture Simulation Model Based on VNA Measurements

31 More coming up in part 2! 2) Anticipate SI issues on your high-speed digital PCBs using virtual prototypes and advanced channel simulation for early evaluation and optimization of design trade-offs

32 32 What were the HSD Challenges on Your Last Design? Inherent jitter/noise of test equipment meant wasted design margins SI issues or lack of margin visibility (eg. Jitter, collapsed "eyes") Power Integrity (eg. Rail bounce, ground plane instability) Missing skills /"know-how" on HSD design Lack of simulation models and/ or accuracy Problems probing signals Copyright 2013 Agilent Technologies, Inc.

33 Backplane Probing Signals Card FPGA Driver DDR Want to see here with scope Card FPGA Receiver De-embedding: Can only probe here Removes the effects of the measurement system + probes Use S-parameter model of the probing system Special solution for DDR! Embedding:.Or here? Is the reverse emulate the effects of an interconnect or channel, trace, etc. Use S-parameter model from EMPro or measured from ENA/TDR Another idea!: Change reference plane by re-characterising receiver card from connector (BERT)

34 Real Example - De-embedding DDR2 BGA Probe NB. Actually need this to comply with JEDEC Spec! (measure at solder balls)

35 Keynote Agenda Why are we here? Methodologies for design and verification of HSD designs From Simulation to Compliance test Summary

36 Compliance test - will optimized design still work when we build it? System Design Interconnect Design Analysis Debug Compliance Test Protocol-based Analysis tools SI Analysis

37 We know Standards Compliance Our solutions are driven and supported by Agilent experts involved in international standards committees: Memory Perry Keller Brian Fetz Jim Choate Min-Jie Chong Thomas Dippon OPT TRX (WAN) Stefan Loeffler Rick Eads OPT TRX (Computing) Greg Le Cheminant Roland Scherzinger Mobile computing Program Thomas Goetzl Lightpeak Program Andreas Gerster

38 Introducing 2014 HSD flow! Compliance test NEW! InfiniiView application PCB design

39 Design and Lab measurement - Share data easily InfiniiView application InfiniiView scope analysis software to share measurement environment with designers. ADS users can import simulation data to compare in same environment ADS T&M tools

40 What were the HSD Challenges on Your Last Design? Inherent jitter/noise of test equipment meant wasted design margins SI issues or lack of margin visibility (eg. Jitter, collapsed "eyes") Power Integrity (eg. Rail bounce, ground plane instability) Missing skills /"know-how" on HSD design Lack of simulation models and/ or accuracy Problems probing signals

41 Design cost HSD SI Design is a classic engineering trade off Optimal design point Robust design point Initial design point Feasible (safe) RX tolerance boundary (jbert) Unfeasible (failed) Design performance (/Power / speed)

42 Agilent HSD - A Global Presence to Support You Santa Rosa, California Colorado Springs Boeblingen, Germany Beijing, China Santa Clara, California Hachioji, Japan Westlake Village, California Alpharetta, Georgia Ghent, Belgium New Delhi, India

43 45 Agilent HSD Services & Support Agilent EEsof Services & Support Local Language/Time Zone Technical Support Telephone, , web On-site Premium Support Proactive support to help projects go smoothly Comprehensive Training Solution Self-paced & live courses Consulting Bridge the gap between product and application

44 Agilent tools and methodology helped solve this visibility challenge allowing xxx to see the cliff edge and create more robust design. ROI: 6 weeks debug versus 6 months Technology Deployment Agilent Private Page 46 September 22nd, 2008

45 Summary HSD designs create new problems for Digital Designers - We understand your challenges! Agilent Technologies is your design partner for HSD Design through to Compliance test! Our people can help you see the Cliff Edge and optimise your next design!