FPGA IMPLEMENTATION OF SUM OF ABSOLUTE DIFFERENCE (SAD) FOR VIDEO APPLICATIONS

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1 FPG IMPLEMENTTION OF UM OF OLUTE DIFFERENCE (D) FOR VIDEO PPLICTION D. V. Manjunatha 1, Pradeep Kumar 1 and R. Karthik 2 1 Department of Electrical and Computer Engineering, lvas Institute of Engineering and Technology, Moodbidri, India 2 Department of Electrical and Computer Engineering, MLR Institute of Technology, Hyderabad, India dvmanjunatha@gmail.com TRCT dvances in multimedia have expanded the boundaries of communication systems and changed the communication industry over the past a few decades in the applications such as digital TV, DVD video, HDTV, internet video streaming, video conferencing, mobile technology, patrolling, object tracking, and medical applications. Video compression (VC) placed a significant part in the realization of these technologies by bridging the gap between the demand for quality, performance and limitations of current storage and transmission capabilities. Motion estimation (ME) is the power hungry block in the video compression system (VC). The sum of absolute difference (D) is the most repeated operation in the motion estimation subsystem. This paper proposed the field programmable gate array (FPG) Implementation of 4X4 D architecture. The design is simulated using Xilinx integrated software environment (IE) and synthesized using Xilinx synthesis tool (XT) on partan-3 FPG board. The proposed D estimates area acquired and latency. Keywords: VC, ME, VC, D, FPG, IE, XT. 1. INTRODUCTION Video compression systems are very helpful in commercial products, from consumer electronic devices as digital camcorders, cellular phones to video teleconferencing systems. lock ased motion estimation searches for the best matching block between the current and reference macro blocks (Ms), for the operation, the sum of absolute difference is one of the most frequent employed criteria as a result, motion estimation produces a motion vector, which represents the motion of the macro block. um of absolute difference is an algorithm for measuring the similarity between the image blocks. It works by taking the absolute difference between each pixel in the original block and the corresponding pixel in the block being used for comparison. These differences are summed to create a simple metric of block similarity. For example the sum of absolute differences to identify which part of a search image is most similar to a template image. In the example, the template image is 3 by 3 pixels in size, while the search image is 3 by 5 pixels in size. Each pixel is represented by a single integer from 0 to 9. The template and the search image pixel values are as shown in Table-1. There are exactly three unique locations within the search image where the template may fit: the left side of the image, the centre of the image, and the right side of the image. To calculate the D values, the absolute value of the difference between each corresponding pair of pixels is used: the difference between 2 and 2 is 0, 4 and 1 is 3, 7 and 8 is 1, and so forth. Table-1. Pixel values of the image / frame. Template image earch image Calculation of D values for each of these locations is given below: Table-2. bsolute difference values of three images. Left Centre Right For each of these three image patches, the absolute differences are added together, giving a D value of 20, 25, and 17, respectively, from these D values, it is apparent that the right side of the search image is the most similar to the template image, because it has the least difference as compared to the other locations. The rest of the paper is organized as follows: ection 2 describes the related work in the sum of absolute differences as a metric of motion estimation to find the motion vectors. Proposed adder architecture is described in section3. ection 4 gives the details sum absolute difference architecture. ection 5 describes the results and discussion, finally we conclude in section

2 2. RELTED WORK There are varieties of methods available in the literature to find the motion vectors where there is lot of tradeoffs between the speed, power and area during the hardware implementation. The work presented by [1-6] shows that motion estimation aims at reducing the temporal redundancy between successive frames in a video sequence using high speed D. The work in [7] proposed that D architecture and compared much architecture in terms of area and delay. The work in [8] presented H.264/VC encoder which employs 1024 D processing units (PE) which use 305k gates. The work in [9] proposed that D architecture and compared much architecture in terms of area and delay. The authors in [10] proposed that the D architecture with 1 and 2stage pipeline, the work done in [8]-[12] presented the D architectures in terms of gate count and delay optimization, but the aspects of power consumption focusing on low power devices were not presented. In this work the rea in terms of LUTs from FPG implementation and the power consumption, area and delay are presented from the IC implementation using RTL Compiler with 180nm technology. 3. PROPOED DDER RCHITECTURE The addition of two binary numbers is the fundamental and most commonly used arithmetic operation in video compression for determining the motion vectors in the video codec. Hence, binary adders are critical building block of most of the video systems. The key challenge addressed in the adder design is the carry propagation operation involving all operand bits. Various different architectures for binary addition have been proposed, based upon the delay, there are two fundamental adder architectures: 3.1 Ripple carry adder It is the simplest architecture. For an n-bit adder, intermediate carries are generated sequentially. It has smallest area, longest delay & consumes lowest power. The 4 bit ripple carry adder is as shown in Figure-1 as below: architecture. It consumes more area & power. The 4 bit carry look ahead adder is as shown in Figure-2 as below: C it P0 2 P3 G3 C3 P2 G2 C2 P1 G1 C1 G0 C0 1it Figure-2. 4 bit carry look ahead adder architecture. In this work we have to develop the low power 4X4 sum of absolute difference algorithm so we use the ripple carry adder architecture. 4. UM OF OLUTE DIFFERENCE (D) D algorithm is used for measuring the similarities between the images by calculating the absolute differences between the pixels of the image (Template image) and their corresponding ones (earch Image) in the macro block, then these differences are added up to result in the similarity block. It requires only two basic mathematical operations addition & shifting. The D algorithm is the simplest metric which considers all the pixels in the block for computation and also separately, which makes its implementation easier and parallel. Due to its simplicity this algorithm is one of the fastest and can be used widely in block motion estimation and object recognition. In this work we implemented the 4X4 sum of absolute difference algorithm on both FPG (partan -3) for prototyping using Xilinx IE simulation tool and the Xilinx XT synthesis tool for the area in terms of LUTs, to find the latency and on IC using cadence RTL Compiler to find the power consumed, area occupied and the delay taken. The block diagram of sum of absolute difference is as shown in Figure-4 and the D hierarchy is shown in Figure-3 below: 1 1 1it 4 it Carry Look head r 0 0 1it C 0 C C3 2 2 C2 1 1 C1 0 0 C0 Template Image 4X4 D Process or Compar ator imilari ty D 4X4 4 3 Figure-1. 4 bit ripple carry adder architecture. 3.2 Carry look ahead adder Here the carry is generated in parallel to reduce the processing delay; hence it is faster than ripple carry 1 0 earch Image 4X4 Figure-3. lock diagram of 4x4 D architecture. The application of sum of absolute difference architecture includes the following: 7193

3 Object recognition Video Compression The generation of disparity maps for stereo images. Video Conferencing. 5. REULT ND DICUION Here first the template image and the search images of the video sequence are given to absolute difference block to find the absolute of the difference and then all the absolute difference values are added up for the entire macro block. Further, the same procedure is repeated for all the macro blocks of the video sequence and saved the added value finally the out of many saved added values of the whichever is having the smallest value that will correspond to the motion vector and the motion estimation can then be performed. The work in this paper is implemented in both IC design using RTL compiler and the FPG implementation done on partan-3 device. The results are presented in the following two sections 5.1. FPG results In this work we developed the verilog code for low power 4X4 um of bsolute Difference algorithm and synthesized using Xilinx synthesis Tool. Xilinx IE (Integrated oftware Environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. The synthesis results are mentioned below Table-3. FPG synthesis results of adders. adder 8-bit RC 9-bit RC 10-bit RC No. Of slices 1 out of out of out of out of input LUTs 2 out of out of out of out of 7168 Delay ns ns ns ns Total memory Kbytes Kbytes Kbytes Table-4. FPG synthesis results of 4X4 D Kbytes particulars 8-bit sum of absolute difference (bs) 4x4 D No. of slices 14 out of out of 3584 No. Of 4 input LUTs 25 out of out of 7168 IO uffers Memory usage Kbyte Kbyte Observing the above Tables 3 and 4 the above table clearly gives the area consumed in terms of Look up Tables the memory usage the design implemented and the delay. In FPG implementation we can only find out the area in terms of LUTs and the delay but we need to find the power so we go for IC design IC DEIGN REULT Here the synthesis is done using the RTL Compiler of Cadence ED tools. Cadence RTL Compiler (Cadence RC) is a logic synthesizer. It takes a HDL model, a library of standard logic cells, a set of synthesis commands and it generates a network of interconnected logic cells (a net list). The designs are targeted using 180 nm technology for Cadence RTL compiler. In IC Design the power consumed area acquired, Delay of the 1 bit adder and 4X4 sum of absolute dif ference are implemented which are tabulated in Tables 5 and 6 as below: Table-5. ynthesis results 1 bit adder.. No Particulars adder which uses EXOR & Nand gates 01 Leakage Power in nw Dynamic Power in nw Total Power in nw Delay T in Ps rea in Q Microns

4 5.3. NPHOT REULT VOL. 12, NO. 24, DECEMER 2017 IN The simulation results of 4X4 D Table-6. ynthesis results low power 4X4 D.. No Particulars Low power 4X4 D 01 Leakage Power in nw Dynamic Power in nw Total Power in nw Delay T in Ps rea in Q Microns 6397 The 4X4 D consists of 1) bsolute difference block 2) r 3) 8 bit Ripple Carry adder 4) 9 bit ripple carry adder 5) 9 bit ripple carry adder 6) 10 bit ripple carry adder 7) 11bit ripple carry adder 8) 12 bit ripple carry adder circuits Figure-4. imulation results of 4X4 sad. 7195

5 Figure-5. ynthesis results of absolute difference block. Figure-6. ynthesis results of full adder. Figure-7. ynthesis results of 8 bit ripple carry adder. Figure-8. ynthesis results of 12 bit ripple carry adder. 7196

6 Figure-9. ynthesis results of 4X4 D. 6. CONCLUION The heavy computational cost of the block matching algorithms (M) can be significant problem in real -time coding applications. To reduce the computational complexity, different VLI architectures are designed to speed up the associated massive arithmetic calculation. Usually VLI architecture means the FPG design and the IC Design which works at very high speed as they are semicustom designs. In this work the low power 4X4 D both in FPG and IC are implemented, the results are as shown in the results and discussion section. Finally the conclusion is that the prototypes can be developed using FPG and their implementation to find the actual area power and the delay parameters, can be found out by many methods but in this work, the considerable reduction in power and area with the corresponding speed is achieved. Further, improvements can be achieved using the proper power, area and speed optimization techniques. REFERENCE [1] Y. Wang et al Hilbert scanning search algorithm for motion estimation. IEEE transactions on circuits and systems for video technology. 9(5): [2]. Lee et al New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLI architecture for MPEG2 video encoding. IEEE transactions on circuits and systems for video technology. 8(6): [3] M. Pickering et al n adaptive search algorithm for block matching motion estimation. IEEE transactions on circuits and systems for video technology. 7(6): [4] J. Y. Tham et al novel unrestricted center biased diamond search algorithm for block motion estimation. IEEE transactions on circuits and systems for video technology. 8(4): [5] H. Wang et al Fast algorithm for the estimation of motion vectors. IEEE transactions on image processing. 8(3): [6] J. W. Kim et al Hierarchical variable block size motion estimation technique for motion sequence coding. Optical engineering. 33: [7]. Wong,. Vassiliadis,. Cotofana um of bsolute Differences Implementation in FPG Hardware. 28 th Euromicro Conference. pp [8] T. C. Chen, et al nalysis and rchitecture Design of an HDTV720p 30 Frames/s H.264/VC Encoder. IEEE TCVT. 16(6): [9] J. Vanne, E ho, T D Hamalainen and K Kuusilinna High-Performance um of bsolute Difference Implementation for Motion Estimation. IEEE TCVT. 16(7): [10] Yufei L, Feng Xiubo and Wang Qin High- Performance Low Cost D rchitecture for Video Coding. Consumer Electronics IEEE Transactions. 53(2): [11] Z. Liu, et al Parallel D Tree Hardwired Engine for Variable lock ize Motion Estimation in HDTV 1080P Real-Time Encoding pplication. IEEE ip. pp [12] tephan Wong, tamatis Vassiliadis, and orin Cotofana um of bsolute Differences Implementation in FPG Hardware. International Journal of Electrical and Computer Engineering. 4: