A 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS

Transcription

1 A 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS ABSTRACT We describe L1 cache designed for digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported. Dual access is achieved by banking the cache in a way that minimizes bank conflict to less than 1%. The cache operates at 600 MHZ under worst-case PVT conditions and dissipates pjoule per access at 1.2V. A low-leakage multithreshold-voltage (MTV) 65nm foundry process technology [10,11] is used for fabrication.. The cache supports simultaneous dual double-word access, and four-double-word evict and fill operations. The memory system includes a tag array and data array: both are designed using single-ported 6T SRAM cell, with an area of 0.54 mm 2 and leakage per cell of less than 10 pa. Three threshold voltages are used with foot and head switches to trade off leakage, active power, and performance. The design of the tag and data array uses novel circuit approaches to enable high coverage on testability through data bypassing with minimum impact to speed. It also employs self-timed circuit with process-dependent senseamp tracking for high speed and low power low by a small pull-down nmos which is driven by a sleep signal. This paper is organized as follows: Section II discusses the tag array design point and physical organization; Section III describes the data array organization and floorplanning; Section IV describes the low power design including clock gating, active and leakage power saving techniques; Section V describe a novel approach to implement the multiplexing of the data out; Section VI discuss the timer and self-timed control circuitry; and Section VII describe special circuit for testability. I. INTRODUCTION A Level 1 data cache (L1D) is described for a high-speed DSP core targeted for mobile applications. The cache design is optimized for both dynamic and static power consumption. Low dynamic power consumption is achieved through serial cache access, extensive clock gating, and the use of static logic in most of the tag and data arrays. A self-timed processdependent tracking timer circuit ensures low power consumption across different process, temperature, voltage (PVT), and frequency operating points. The design features described are targeted for current-and-future DSP cores The DSP architecture tolerates high latency on the L1D cache access. This decision was made to enable the cache access to be fully serial (TLB->Tag->Data) as shown in Figure 1 [6]. The data array is not accessed except when both the TLB and the tag output determines a hit, in which case the access is limited to the exact sub-array selected by decoding the lower bits of the virtual address. Figure 1 illustrates the data flow of the L1D cache subsystem, beginning with the address lookup from the register file (RF), and ending with the data write back to the RF. To reduce leakage power during both standby and normal operation, the 6T cell used in both arrays is selected to be a low-leakage cell with high threshold voltage (HVT). The periphery circuit uses the low threshold voltage (LVT) devices, with alternate head and foot switch for the wordline, and with a foot switch on all input/output related circuitry. The power supply for all the 6T cells is separated from the periphery circuit supply to enable holding the state when standby mode is selected. The wordline is guaranteed to be Figure 1 L1D data flow starting from RF address lookup into load data II. TAG ARRAY The cache tag array design uses an SRAM-based tag. This design choice resulted from a detailed analysis of the trade-offs between using CAM-based and SRAM-based tag, which concluded that an SRAM-based tag is more efficient for the target architecture in terms of area, power, and speed [2] for the following reasons: 1. A CAM tag uses more area than an SRAM tag because CAM cells are 4x larger than 6T cells. This leads into an overall area increase of 20% for the L1D. 2. A CAM tag is more complex and less flexible for timing because the tag output is the wordline. An SRAM tag has greater flexibility with respect to parallelism, because it outputs only a hit signal which can be factored in many different ways depending on the timing and power tradeoffs.

2 3. A CAM tag needs to be tightly coupled with the data array, while an SRAM tag need not be tightly coupled to all sets of the data array (and therefore can be optimized independently). With a CAM tag, distributing the physical page number (PPN) to the tag array dominates the active power value, making the CAM tag organization less power-efficient. cache sizes, the enable signal gates the hit signal and ensures that it is zero for the ways unselected. For example, if an application specifies an 8-way 16KB cache, the tag disables the access and sets to zero the hit signals for the unused 8 ways of the tag. This reduces tag power by half (which itself is half the power of the L1D). Figure 3 shows the 16-way tag array floorplan and placements of main block The DSP is designed for applications beyond usual modem code such as: audio, video, and gaming with different power/performance tradeoffs. Therefore we have arranged the L1D cache to support way prediction and variable associativity with different cache sizes. The default is a 16-way set-associative tag; if an application specifies fewer ways, the way read enable can be deasserted and the hit way for the unselected ways is set to 0. Figure 2 shows the Tag main building blocks and control circuitry, including the generation of all required signals. Figure 3: Tag array chip view Figure 2: Tag array main blocks, detail control and timer circuitry The tag accepts 16 enable signals (one for each way) and uses these signals to enable the internal clocks and comparator for each way. To enable variable associativity and The L1 pipeline requires the tag lookup and compare to finish in single cycle. The tag gets accessed in parallel with the TLB which generate the ppn bus. The two operand one from the tag stored data and one from the TLB get compared using static comparator to generate hit signal per way. The tag access starts from rising edge clock and uses asynchronous timer (discuss in section VIIII) to generate the read/write control signals. III. DATA ARRAY ORGANIZATION The 32KB data array is composed of 4 identical 8KB quadrants (i.e, Quad0/1/2/3) and each quadrant includes 4 2KB sub-arrays (i.e, subarray0/1/2/3). The external L2 cache bus (which reads and writes the array) travels from the top part of the array. The array data (which reads and writes the register file), address bits, way index, and control signals travel from the right side of the memory array. A central shorted clock driver is located at the right side of the array. The regional clocks are distributed to each quadrant of the

3 core via top-level shielded metal, with appropriate width and space to reduce potential coupling noise, process variation, and power. The detailed floorplan and main sub-block placement are shown in Figure 4 speed and low power consumption, the wordline drivers are implemented with a 4-conditional-clock system using a dynamic circuit approach as shown in Figure 5. Each clock drives 16 wordlines qualified by the index. Sharing the common virtual ground input reduces the gate capacitance on the critical signals which result in lower power and higher speed. Figure 5: Wordline driver with 4-conditional clocks Figure 4: Data array chip view IV. DESIGN FOR LOW POWER The cache data array incorporates various circuit and architecture techniques to achieve high speed and low power: Self-time circuit with process-dependent sense-amp tracking for power reduction 16-way group-4 dynamic wordline driver with multiple conditional clocks to reduce the clock loading and access time High-speed, ATPG-compatible, tri-state-withdefault-pull-up, output bus-multiplexing circuit The data array applies a bi-level power-saving scheme: the first level is for each quadrant, and the second level is for each sub-array within a quadrant. Each quadrant has its enable signal, which is based on the index decoding, to gate off the raw clocks that feed into the quadrants. And, each sub-array under the quadrant has its associated enable signals (2 nd level decoding from the index) to disable the quadrant clock feeding into the sub-array. The data array read and writes operations use a selfreset circuit with multiple voltage-differential settings to optimize speed, yield, and power (discuss in more detail in section VI). To achieve the design requirements for high One consideration for a multiple-clock system is routing resources. We observed that in the current layout dimension, clock routing tracks are not an issue. Compared with the single clock system for wordline drivers, this implementation reduces the gate loading of the clock by a factor of four. The conditional-enable-clock circuit can also serve as buffer drivers, which reduces the PVT effect with shorter stage of buffer chain. In addition, using the appropriate layout approach increases the capacitance coupling by logical shielding. Leakage control is a primary goal in power design for mobile applications. The cache design implements two levels of leakage control: A peripheral header/footer is used to maintain the data stored in the array when the DSP core enters sleep mode. Deep sleep mode is implemented as a global footer which gates off the Vdd source with HVT PFET. The memory state is kept through the usage of different supply for the 6T SRAM cell. The sleep transistor shown in Figure 5 is driven from sleep signal to guarantee the isolation of the SRAM state wordline is in low state when the part is in deep sleep. In addition, a multiple-vth process design is used to achieve the speed and leakage goals. V. Data Multiplexing Various output multiplexing schemes were considered and evaluated during the early stages of the

4 design. A static multiplexing scheme was unable to fulfill the aggressive timing goals. The self-reset time circuit brings the difficulty and complexity of implementing a two-phase domino-circuit type of multiplexing, with various delay settings. By fully utilizing the sense-amplifier s dual outputs (which are followed by dual tri-state multiplexing drivers as in Figure 6) within each 2KB sub-array, 2-read output tri-state buses are implemented with a simplified multiplexing structure (as shown in Figure 7). In Figure 7 (which indicates only one read bus structure), when one of the 2KB sub-array inside Quad0 is selected, the associated output driver (as in Figure 6) drives the Quad0_busA. At the same time, none of the 2KB sub-arrays inside Quad1 should be selected to drive quad1_busa, which indicates Quad1_enable inside Quad1 as logic_0/vss and Quad1_busA will be pulled up to logic_1/vdd by the PFET (as P1 in Figure 7). By forcing the three inactive Quads output buses as logic_1/vdd, we were able to implement each Quads output multiplexer as AND structures to achieve better timing and area consumption. Figure 6: Dual-output-tri-state driver circuits inside 2KB subarray Figure 7: Data Array tri-state-with-default-pull-up output bus multiplexing scheme VI. Timer Design Both Tag array and Data array uses similar timer design. The timer is software programmable (through the JTAG) with accelerating bits (ACC) to select the proper timing margin between the different signals. One of the critical margins is the time from wordline asserted to the time the sense amp is enable, which determines the bitline differential. The self-timing scheme is based on the clock rising edge, with various self-delay selections to compensate for the process variation and to reach the deserved voltage differential. An additional dummy column of 6-T SRAM cells is used to mimic the diffusion capacitance of the memory cells. On memory write operations, the delay setting is adjusted to ensure that the wordline pulse with a smaller timing window than is used on read operations; this ensures that the unselected bit lines do not drop too much for powersaving purposes. During read operation the ACC bits controls the number of SRAM cells wordline turns on to pulldown on the dummy bitline which is normally precharged high like all other bitlines. The dummy bitlne drives an inverter which generates the READY signal to enable the sense amp and to turn off the wordline. We choose to use a dummy column with SRAM cells as the driver to closely match the 6T SRAM transistors which are different from the logic transistor. The addition of the programmability and the use of the same type transistor in the timer ensure close tracking of the actual bitline development cross process, voltage, and temperature which prevents over design of the margine and saves on both timing and power. The dummy column is placed near the edge of the array closer to the wordline driver to enable the usage of lower level metal for dummy wordline signals. Figure 8 shows the simulation result of post layout netlist of the array access and the bitline differential as a function of the number of dummy SRAM cells which turns on based on the ACC bus selection. Because the bitline development has big impact on power, speed, and yield this enables the product to tradeoff between these metrics.

5 bit line seperation and tot delay vs # of cells on 3.00E E E-01 bitline_seperation tot_delay_from_clk 1.40E E-09 bit line seperation (v) 2.00E E E E E E-10 tot_delay (s) 4.00E E E E # of cells on 0.00E+00 Figure 8: Development voltage and total delay for different ACC bit setting VII. Design for Test Memory arrays for both the tag array and data arrays need to support bypassing during Automatic Test Pattern Generation (ATPG). This enables improved coverage on the periphery circuits that are used between the IO and the data flop out of the memory. For the tag array the tag read from the array passes directly into the comparator; therefore, it is important to be able to control the data going into the comparator and the data out mux (as shown in Figure 8). Since the hit signal timing is highly critical, adding a mux or gate for DFT is costly during functional mode. We used the novel approach of controlling the output data by bypassing the write data into the output data, with no impact to timing except adding a small load. This was possible due to the use of the SR latch (which was originally selected for low power operation), and by utilizing the precharge nature of the sense amplifier output. This approach results in full controllability and observablility of the output path of the memory, without accessing the arrays. The arrays were tested using BIST. For ATPG enhancement, each data array s quadrant tristate output buses are embedded with NFET pull downs (as N1 and N2 shown in Figure 9). During ATPG mode, all subarrays sense-amplifiers output tri-state drivers are disabled and the four quadrants output buses are statically-driven by different Quad-enable signals thru the associated PFET and NFETs (as P1 and N1/N2 in Figure 9); this increases the DFT coverage with minimum timing penalty of additional NFET s diffusion capacitance ( from N1). As in Figure 9, an ATPG scan pattern can scan through Quad0_enable Flip-Flop (x0) and output buses (Quad0_busA, Quad01_busA, BusA_output) to the final scanable Flip-Flop (x1), and can be generated by commercial DFT tools (such as TetraMax). Figure 8: Tag array sense amp with write data bypass Figure 9 : Data Array Mux out with DFT bypass enable REFERENCES [1] Alex Veidenbaum, Dan Nicolaescu, Low Energy, Highly Associative Cache Design for Embedded Processors, Proceedings of the IEEE International Conference on Computer Design, October 2004 [2] Baker Mohammad et al, Cache Organizations for Embedded Processors: CAM-vs-SRAM, Proceeding of System on Chip, IEEE conference, 2006 [3] G. Albera, I. Bahar, Power and performance tradeoffs using various cache configurations. In Power Driven Microarchitecture Workshop at ISCA98, Barcelona, Spain, June 1998

6 [4] Jonathan R. Haigh et al, A Low-Power 2.5-GHz 90-nm Level 1 Cache and Memory Management Unit, IEEE JSSC, MAY 2005 [5] J. Montanaro et al, A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE JSSC, November [6] J. Hennessy and D. Patterson, Computer Design & Organization, 3rd ed. Morgan Kaufmann, [7] Lawrence T. Clark,, An Embedded 32-b Microprocessor Core for Low-Power and High-Performance Applications, IEEE JSSC, NOVEMBER 2001 [8] K. Pagiamtzis, A. Sheikholeslami, Content-Addressable Memory (CAM) Circuits and Architecture, IEEE JSSC, March 2006 [9] N. Weste and D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective. Addison-Wesley, [10] Samuel K. et al, 65nm CMOS High Speed, General Purpose and Low power Transistor Technology for High Volume Foundry Application, Symposium on VLSI Technology, June 2004 [11] Steegen, A et al, 65nm CMOS technology for low power applications, Electron Devices Meeting, IEDM Technical Digest. IEEE International, December 2005