MICRO Graphicionado. A High-Performance and Energy-Efficient Graph Analytics Accelerator

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1 MICRO 2016 Graphicinad A High-Perfrmance and Energy-Efficient Graph Analytics Acceleratr Tae Jun Ham Lisa Wu Narayanan Sundaram Nadathur Satish Margaret Martnsi Slide:

2 Graph Analytics A key wrklad f mdern-day cmputing Applicatin Dmains Scial Netwrks, Biinfrmatics, Healthcare, Cybersecurity, Simulatin, etc. Algrithms Path Analysis (e.g., BFS, SSSP) Centrality Analysis (e.g., PageRank, Betweenness Centrality) Recmmendatin systems (e.g., Cllabrative Filtering) Cmmunity Analysis

Graph Analytics is difficult t cde Graph Analytics has Irregular data access patterns Extremely lw cmputatin-t-cmmunicatin rati Pr spatial/tempral data lcality

(i.e., vertex prgram) Framewrks rchestrate data mvements fr given cmputatin using efficient backend SW Pregel GraphMat PGX Graph Engine Industry ( ) Extended

3 Graph Analytics is difficult t cde Graph Analytics has Irregular data access patterns Extremely lw cmputatin-t-cmmunicatin rati Pr spatial/tempral data lcality Difficult-t-extract parallelism Memry-bund perfrmance Slutin: Sftware Graph Prcessing Framewrks Prgrammers express graph algrithms using a prgramming abstractin (i.e., vertex prgram) Framewrks rchestrate data mvements fr given cmputatin using efficient backend SW Pregel GraphMat PGX Graph Engine Industry ( ) Extended Giraph nvgraph System G GraphLab Create Pegasus (ICDM 09) Galis (SOSP 13) Ligra (PPPP 13) Academia X-Stream (SOSP 13) TurbGraph (KDD 13) GraphX (OSDI 14) Gunrck (PPPP 16)...

4 Sftware Framewrks have limitatins = Insufficient tailring t HW Applicatin-blivius memry system in cnventinal prcessrs Caches blindly cache all data at a carse granularity including... Lw tempral lcality data Lw spatial lcality data (i.e., nly 4B ut f 64B is utilized) Our measurement shws that SW framewrks cnsume 2x-27x mre memry bandwidth than the ptimal cmmunicatin case Expensive data mvement in cnventinal prcessrs Graph analytics has extremely lw cmputatin-t-cmmunicatin rati Mst algrithms: < 6% f instructins are used fr actual cmputatin; 94% used fr data mvements; results in huge energy cnsumptin.

5 Graphicinad Apprach Graphicinad: A high-perfrmance, energy-efficient graph analytics HW acceleratr which vercmes the limitatins f sftware framewrks while retaining the prgrammability benefit f SW framewrks Retains Prgrammability Specialized-while-flexible HW pipeline Overcmes Limitatin Applicatin-specific memry system Applicatin-specific pipeline design

6 Presentatin Outline Why Graphicinad? Vertex Prgramming Abstractin Cnstructing Graphicinad Pipeline frm Abstractin Optimizing Graphicinad Optimizing Data Mvement Scaling On-Chip Memry Usage Parallelizatin Perfrmance/Energy Evaluatin Cnclusins

7 Graph Data Structure Graph cnsists f vertices & edges Each Vertex has an ID and and a prperty (r state) Each Edge is defined as a tuple (SRC ID, DST ID, edge prperty) Graph analytics: an iterative cmputatin t calculate the desired vertex prperty fr each vertex

8 Vertex Prgramming Abstractin 1 Fr each active Vertex U 2 Fr each utging edge E(U,V) Prcessing Phase 3 4 Res = Prcess_Edge (E weight, U prp ) V temp = Reduce (V temp, Res) 5 End 6 End Apply Phase Fr each Vertex V V prp = Apply(V temp, V prp ) End Prcess_Edge Reduce Apply Vertex prgramming abstractin is cmmnly used in SW framewrks (e.g., Intel GraphMat, Ggle Pregel, etc.) Prgrammers express graph analytics algrithm with three custm functins Graphicinad uses the same abstractin t retain the prgrammability f SW framewrks

9 Vertex Prgramming Abstractin Prcessing Phase Apply Phase Fr each active Vertex U End Fr each utging edge E(U,V) End Res = E weight + U prp V temp = min(v temp, Res) Fr each Vertex V End V prp = min(v temp, V prp ) Prcess_Edge Reduce Apply V prp : minimum distance t V n last iteratin V temp : minimum distance t V n this iteratin Single Surce Shrtest Path (SSSP) Example Prcess_Edge: E weight + U prp Reduce: min(v temp, Res) Apply: min(v temp, V prp )

10 Vertex Prgramming Abstractin Prcessing Phase Apply Phase Fr each active Vertex U End Fr each utging edge E(U,V) End Res = E weight + U prp V temp = min(v temp, Res) Fr each Vertex V End V prp = min(v temp, V prp ) Calculate a distance t V thrugh this edge Update the current minimum distance t V Cmpare the current minimum distance with the value frm the last iteratin; If it changes its value, add V t the active vertex set fr the next iteratin V prp : minimum distance t V n last iteratin V temp : minimum distance t V n this iteratin Single Surce Shrtest Path (SSSP) Example Prcess_Edge: E weight + U prp Reduce: min(v temp, Res) Apply: min(v temp, V prp )

11 Frm abstractin t HW fr (i=0; i<activevertex.size(); i++) { vid = ActiveVertexID[i]; vprp = ActiveVertexPrp[i]; eptr = PtrTEdgeList[vid]; fr (e = Edges[eptr]; e.src == vid; e = Edges[++eptr]) { res = Prcess_Edge(e.weight, vprp); temp = TempVertexPrp[e.dst]; temp = Reduce(temp, res); TempVertexPrp[e.dst] = temp; } } // Apply Phase updates ActiveVertexPrp with TempVertexPrp Read the active (SRC) vertex Traversing edges f the given active vertex Updating the destinatin vertex with the prgrammer supplied cmputatin Prcessing Phase Blck Diagram Line 2-3 Line 4 Line 5 Line 6 Read Active SRC Prperty Read Edge Pinter Read Edges fr given SRC Prcess Edge Read Temp. Reduce Write Temp. Line 7 Line 8 Line 9

12 Frm abstractin t HW fr (i=0; i<activevertex.size(); i++) { vid = ActiveVertexID[i]; vprp = ActiveVertexPrp[i]; res = Prcess_Edge(e.weight, vprp); temp = TempVertexPrp[e.dst]; temp = Reduce(temp, res); TempVertexPrp[e.dst] = temp; } } // Apply Phase updates ActiveVertexPrp with TempVertexPrp Custm Cmputatin Prcessing Phase Blck Diagram Line 2-3 Line 4 Line 5 Line 6 Sequential (vertex) Memry Access eptr = PtrTEdgeList[vid]; Nn-sequential (edge ptr) Memry Access fr (e = Edges[eptr]; e.src == vid; e = Edges[++eptr]) { Nn-sequential and then Sequential (edge) Memry Access Nn-sequential (vertex) Memry Access Read Active SRC Prperty Read Edge Pinter Read Edges fr given SRC Prcess Edge Sequential Memry Access Unit Nn-Sequential Memry Access Unit Read Temp. Reduce Write Temp. Custm Cmputatin Unit Line 7 Line 8 Line 9

13 Frm abstractin t HW fr (i=0; i<activevertex.size(); i++) { vid = ActiveVertexID[i]; vprp = ActiveVertexPrp[i]; eptr = PtrTEdgeList[vid]; fr (e = Edges[eptr]; e.src == vid; e = Edges[++eptr]) { res = Prcess_Edge(e.weight, vprp); temp = TempVertexPrp[e.dst]; temp = Reduce(temp, res); TempVertexPrp[e.dst] = temp; Read-Mdify-Write Update needs t be atmic fr the same destinatin vertex (e.dst) } } // Apply Phase updates ActiveVertexPrp with TempVertexPrp Prcessing Phase Pipeline Line 2-3 Line 4 Line 5 Line 6 Read Active SRC Prperty Read Edge Pinter Read Edges fr given SRC Prcess Edge Sequential Memry Access Unit Nn-Sequential Memry Access Unit Cntrl Read Temp. Reduce Write Temp. Line 7 Line 8 Line 9 Custm Cmputatin Unit Cntrl Unit

14 Optimizing Data Mvement Prcessing Phase Pipeline S1: Read Active SRC Prperty S2: Read Edge Pinter S3: Read Edges fr given SRC S4: Prcess Edge Sequential Memry Access Unit Nn-Sequential Memry Access Unit S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. Custm Cmputatin Unit Cntrl Unit 1. Nn-sequential access; lw-spatial-lcality PtrtEdgeList[vid] TempVertexPrp[e.dst] Only use 4-16B ut f 64B ff-chip memry access granularity; leads t ff-chip memry BW waste 2. High-tempral lcality TempVertexPrp[e.dst] Data will be used again fr edges with the same destinatin vertex Use fine-grained n-chip SPM fr data used fr these mdules

15 Optimizing Data Mvement Prcessing Phase Pipeline S1: Read Active SRC Prperty S2: Read Edge Pinter S3: Read Edges fr given SRC S4: Prcess Edge On-chip SPM Access Unit Sequential Memry Access Unit Nn-Sequential Memry Access Unit S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. Custm Cmputatin Unit Cntrl Unit 1. Nn-sequential access; lw-spatial-lcality PtrtEdgeList[vid] TempVertexPrp[e.dst] Only use 4-16B ut f 64B ff-chip memry access granularity; leads t ff-chip memry BW waste 2. High-tempral lcality TempVertexPrp[e.dst] Data will be used again fr edges with the same destinatin vertex Use fine-grained n-chip SPM fr data used in these mdules

16 Optimizing Data Mvement Prcessing Phase Pipeline S1: Read Active SRC Prperty S2: Read Edge Pinter S3: Read Edges fr given SRC S4: Prcess Edge On-chip SPM Access Unit Sequential Memry Access Unit Nn-Sequential Memry Access Unit S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. Custm Cmputatin Unit Cntrl Unit 1. Sequentially accessed; high-spatial lcality Has predictable access pattern ActiveVertexPrp[i] Edges[eptr++] All 64B laded frm the ff-chip memry will be used 2. Lw-tempral lcality Each active vertex r an edge is prcessed nly nce. This data will nt be accessed again fr the current iteratin. Use prefetcher; D nt use n-chip SPM fr data used fr these mdules

17 Scaling On-chip Memry Usage Graphicinad utilizes an n-chip strage t avid wasting ff-chip BW Often requires 4-16B n-chip strage per vertex Nt enugh n-chip strage fr 10M+ vertices Slutin: Partitin a graph befre the executin; Then, prcess each subgraph at a time Assign edges t different slices based n their destinatin vertices Original Graph

18 *Paper has additinal scaling techniques Scaling On-chip Memry Usage Graphicinad utilizes an n-chip strage t avid wasting ff-chip BW Often requires 4-16B n-chip strage per vertex Nt enugh n-chip strage fr 10M+ vertices Slutin: Partitin a graph befre the executin; Then, prcess each subgraph at a time Assign edges t different slices based n their destinatin vertices Slice 1 (Edges with DST vertices 1,2,3) Original Graph Slice 2 (Edges with DST vertices 4,5,6) Only half f the vertices t be stred in n-chip strage at a time

19 Parallelizing Graphicinad Pipeline S1: Read SRC Active SRC Vertex Prperty 0 S2: Read Edge ID Table S3: Read Edges fr Edge given (0,3) SRC S4: Prcess Edge S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. S1: Read Active SRC Prperty S1: Read SRC Active SRC Vertex Prperty 2 S2: Read Edge ID Table S2: Read Edge ID Table S3: Read Edges fr given SRC S3: Read Edges Edge (2,3) fr given SRC N NxN x N Switch S4: Prcess Edge S4: Prcess Edge S5: Cntrl S5: Cntrl S6: Read Temp. S6: Read Temp. S7: Reduce S7: Reduce S8: Write Temp. S8: Write Temp. S1: Read Active SRC Prperty S2: Read Edge ID Table S3: Read Edges fr given SRC S4: Prcess Edge S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. Naive Parallelizatin Apprach Replicate Pipeline Tw mdules trying t read the same address (TempVertexPrp[3]) Each pipeline stream prcesses a prtin f the active (SRC) vertices (e.g., a mdul f the SRCID determines which stream fr prcessing) Different streams will try t read/write the same memry address (TempVertexPrp[]) at the same time n S6 & S8 Design cmplexity (SPM prt cunt) and perfrmance degradatin

20 Parallelizing Graphicinad Pipeline SRC Access Prtin DST Access Prtin S1: Read SRC Active SRC Vertex Prperty 0 S2: Read Edge ID Table S3: Read Edges Edge (0,3) fr given SRC S4: Prcess Edge S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. S1: Read Active SRC Prperty S1: Read SRC Active SRC Vertex Prperty 2 S2: Read Edge ID Table S2: Read Edge ID Table S3: Read Edges fr given SRC S3: Read Edges fr Edge given (2,3) SRC N NxN x N Switch S4: Prcess Edge S4: Prcess Edge S5: Cntrl S5: Cntrl S6: Read Temp. S6: Read Temp. S7: Reduce S7: Reduce S8: Write Temp. S8: Write Temp. S1: Read Active SRC Prperty S2: Read Edge ID Table S3: Read Edges fr given SRC S4: Prcess Edge S5: Cntrl S6: Read Temp. S7: Reduce S8: Write Temp. Graphicinad Apprach Each pipeline stream is separated t tw pieces: SRC access / DST access prtin Nw each unit access an exclusive prtin f the scratchpad memry Each unit accesses an exclusive memry regin N x N switch rutes data t the crrect DST stream (e.g., a mdul f the DSTID) Reductin in design cmplexity and imprvement in thrughput

21 Presentatin Outline Why Graphicinad? Vertex Prgramming Abstractin Cnstructing Graphicinad Pipeline frm Abstractin Optimizing Graphicinad Optimizing Data Mvement Scaling On-Chip Memry Usage Parallelizatin Perfrmance/Energy Evaluatin Cnclusins

22 Overall Graphicinad Perfrmance 7 6 Sftware Framewrk Graphicinad Graphicinad Sftware Framewrk Speedup ver Sftware Framewrk FR FB Wiki LJ RMAT TW AVG FR FB Wiki LJ RMAT TW AVG FR FB Wiki LJ RMAT TW AVG NF SB AVG PageRank (PR) Breadth-First Search (BFS) (BFS) Single Surce Single-Surce Shrtest Path Cllabrative (SSSP) (CF) Shrtest Path (SSSP) Filtering (CF) Graphicinad achieves ~3x speedup ver state-f-the-art sftware framewrk (Intel GraphMat) acrss different wrklads Sftware framewrk was run n a 32-cre Haswell Xen server Bth system were prvisined the same theretical peak memry BW (78GB/s)

23 Graphicinad Energy Cnsumptin Nrmalized Energy Cnsumptin edram Static Energy edram Dynamic Energy edram Static Energy edram Dynamic Energy Graphicinad Pipeline Static Energy Graphicinad Pipeline Dynamic Energy Custm Cmputatin Energy Graphicinad Pipeline Static Energy Graphicinad Pipeline Dynamic Energy Custm Cmputatin Energy 0 FR FB Wiki LJ RMAT TW FR FB Wiki LJ RMAT TW FR FB Wiki LJ RMAT TW NF SB PageRank (PR) Breadth-First Search (BFS) Single Surce Single-Surce Shrtest Path (SSSP) Cllabrative Shrtest Path (SSSP) Filtering (CF) Graphicinad cnsumes < 2% f the energy (50x-100x) cmpared t the sftware prcessing framewrk Mst f the energy (70%+) was spent fr the edram static energy 20-25x pwer saving & 2-5x speedup

24 Effect f Parallelizatin & Optimizatin Nrmalized Perfrmance Baseline Baseline CFG 1 = Stream Parallelizatin(x2) CFG 2 = Stream Parallelizatin(x4) CFG 3 = Stream Parallelizatin(x8) CFG1 = Stream Parallelizatin (2x) CFG2 = Stream Parallelizatin (4x) CFG3 = Stream Parallelizatin (8x) CFG4 = CFG3 + Prefetching CFG 4 = CFG 3 + Prefetching CFG 5 = CFG 4 + Pipeline Balancing* PageRank (PR) Breadth-First Search (BFS) Single Surce Shrtest Path (SSSP) Cllabrative Filtering (CF) PageRank (PR) Breadth-First Search (BFS) Single-Surce Shrtest Path (SSSP) CFG5 = CFG4 + Pipeline Balancing* Cllabrative Filtering (CF) The parallelizatin and ptimizatin f Graphicinad achieves up t 27x speedup ver the baseline single-stream pipeline Withut effective parallelizatins and ptimizatins, simply using HW des nt necessarily bring any benefit

25 Cnclusins Sftware graph prcessing framewrks has limitatins Inefficient n-chip memry (cache) usage Expensive data mvement Graphicinad: Specialized HW acceleratr fr graph analytics Efficient use f n-chip memry Specialized pipeline tailred fr graph analytics data mvement Effective parallelism ~3x speedup and 50x+ energy saving ver state-f-the-art sftware framewrk

26 MICRO 2016 Graphicinad A High-Perfrmance and Energy-Efficient Graph Analytics Acceleratr Tae Jun Ham Lisa Wu Narayanan Sundaram Nadathur Satish Margaret Martnsi

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