CPU_EU. 256x16 Memory

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1 Team Members We are submitting our own work, and we understand severe penalties will be assessed if we submit work for credit that is not our own. Print Name Print Name GRADER ID Number ID Number Estimated Work Hours Point Scale : Exemplary 3: Complete 2: Incomplete 5%will be deducted from total score for each day late 1: Minor effort 0: Not submitted Score = Points awarded (Pts) x Weight (Wt) # Demonstration Wt Pts Score Grader Signature Date 1 Demo working Integer Datapath 2 Documentation / Source Code 6 Testbench / Simulation-Verification 2 Days Late Total In Lab Score General Statement: Your team (2 people) is to complete the 301 -bit RISC Processor. This is done by connecting the CPU_EU with a timing and control unit (CU) verilog module and the 256x Memory (developed in lab7). The CU will be a Moore implementation of a finite state machine, where the outputs (control signals for the CPU_EU and Memory) are a function of the present state. The CU will control the execution of instructions defined for the 301 RISC Processor (see -bit RISC Processor specifications document). At reset, the 301 RISC Processor will begin fetching and executing instructions starting at memory location 0x00. CU (Finite State Machine) W_Adr rw_en R_Adr S_Adr Alu_Op s_sel adr_sel ir_ld pc_ld pc_inc pc_sel IR_out ALU_Status Address CPU_EU D_out D_in Address D_in D_out mw_en 256x Memory 301 -bit RISC Processor 301 Lab Assignment 8 Page 1

2 Top Level and I/O and Specifications: Your top level verilog module will interconnect the (1) -bit RISC Processor, (2) Memory, (3) Display Controller and (4) Debounce modules. The Display Controller is to display the Address outputs and the D_in inputs from/to the CPU_EU module based upon the AD_sel input (sw7). Additional control signals not provided by the CU are shown below. The reset signal is to be provided to every logic block using synchronous logic. Both the CU and CPU_EU modules are to be clocked using the step clk button (debounced). The step_mem button (debounced), AD_sel and dump_mem signals will be used for displaying the contents of Memory after the 301 RISC Processor executes a Halt instruction. Memory is clocked with the 50Mhz FPGA board clock. Memory is to be generated (CoreGen) with the three initialization files (e.g. ram_256x_lab8a.coe). reset step step AD dump mem clk sel mem btn btn btn sw sw Verification: To verify that all instructions of your RISC Processor are working, you must execute (by stepping through) the instructions for all three memory modules. The binary content of the memory modules that you will generate are shown on pages 9 to 11. Your team must complete those three pages by disassembling the machine code, fill in the Register Written column (where applicable), fill in the Final Contents of CPU and Memory registers that were written to by the program that is executed as well as the exact number of instructions that were executed, including the HALT instruction. Deliverables: Your team must turn in (1) pages 1-2 of these cover sheets, followed by (2) the print outs from all verilog modules, logically sequenced in a top-down manner, starting with the top-level module, followed by (3) all three memory modules (pages 9-11) completed with applicable assembly instructions, completed Register Written column (where applicable), completed Final Contents of CPU and Memory registers along with the number of instructions executed, and lastly, (4) the completed Team Accountability Reporting Sheet (p. 12). As always, you will be penalized for each violation related to inputs, outputs, and operation specifications. You will be penalized for not adhering to documentation specifications of the deliverables, as well as substandard documentation practices (i.e. meaningless or inaccurate comments, wrap-around in print outs, illegible documentation, etc.). Due Date: Wednesday, April 29, 2015 {Wednesday of Week 14} 301 Lab Assignment 8 Page 2

3 Control Unit Design Specifications: The control signals for the CU module are described below: Inputs: IR_out: ALU_Status: Outputs: W_Adr: rw_en: R_Adr: S_Adr: This is the -bit instruction code currently in the IR, which consists of the 4-bit opcode and three 3-bit register select codes. The 4-bit opcode is used in the decode state to determine what instruction to execute (i.e. what execute state to go to). The W_Adr, R_Adr, and S_Adr outputs will be derived from the three 3-bit register select codes, based upon the 4-bit opcode (e.g. for add W_Adr = IR[8:6], R_Adr = IR[5:3] and S_Adr = IR[2:0]). These three 1-bit values are the N, Z and C status indicators from the ALU, based upon the current ALU opcode. These 3 bit values may or may not be stored in the actual RISC Processor s flag register based upon what state the processor is current in (e.g. the add state versus the store state). The 3-bit Write Address to specify which register (R0 to R7) to write to (if rw_en is asserted). The register file write enable. When rw_en=1, the register specified by W_Adr will be written to. The 3-bit R Address to specify which register (R0 to R7) will be output from the R port of the register file. Note that addresses for Memory registers to be read from or written to must come from the R port of the register file. The 3-bit S Address to specify which register (R0 to R7) will be output from the S port of the register file. Note that data to be written to Memory must come from the S port of the register file. Alu_Op: s_sel: adr_sel: ir_ld: pc_ld: pc_inc: pc_sel: mw_en: This is the 4-bit ALU opcode (specified in lab 6) to control which ALU operation to perform. If s_sel=0 the S-port of the ALU gets data from the S-port of the register file. If s_sel=1 the S-port of the ALU gets data from the memory (i.e. the DS datapath inputs). If adr_mux=0, the Address outputs from CPU_EU come from the PC, else they come from the R-port of the register file. If clk), the instruction register (IR) will be loaded, presumably with an instruction from Memory. If clk), the IR will remain the same. If clk), PC PC + sign_extension (IR[7:0]). This operation is an addition to the CPU_EU logic needed for jump instructions. If clk), PC PC + 1. Note that pc_ld and pc_inc are mutually exclusive outputs. If pc_sel=0, inputs to the PC come from the PC+sign_extension logic. If pc_sel=1, the inputs to the PC come from the Datapath (Alu_out). Refer to the PC Modifications page. The Memory write enable. If mw_en=1, the Memory register specified by the Address outputs of CPU_EU will be written with the data on the D_Out outputs of the CPU_EU. If mw_en=0, Memory will not be written to. It is IMPORTANT to note that ALL of the CU outputs must be assigned values in EVERY state! Memory Address Multiplexing: In order for us to display the contents of Memory, indepent of CPU_EU generated addresses, there is the need for the top level verilog module to multiplex an address to the Memory module. This is the purpose of the dump_mem switch. The top level module is to have an -bit mem_counter register (initialize to 00h at reset). If dump_mem = 0, the address given to Memory comes from the CPU_EU Address outputs. If dump_mem = 1, the address given to Memory comes from the -bit mem_counter. Use a conditional continuous assignment statement to implement this 2-to-1 mux function, as follows: assign madr = dump_mem? mem_counter : Address; where the LHS (madr) is the wire used in the instantiation of the Memory module and the two RHS arguments are the mem_counter (defined in the top level module) and the Address outputs of the CPU_EU module. Note: since the Memory module has only 256 locations (8-bit addr), instantiate it using madr[7:0]. The step_mem button is used to increment the -bit mem_counter. Thus, at every positive edge of step_mem, the mem_counter is to be incrememted by 1. The AD_sel selects displaying either -bit Data (AD_sel=0) or -bit address (AD_sel =1). 301 Lab Assignment 8 Page 3

4 RESET: PC = 00h; {nf, zf, cf} = 3 b0 FETCH: IR M[PC] PC PC +1 CU State Diagram (Partial) ADD: R[d] R[d] + R[s] {nf,zf,cf}={n,z,c} IR[15:9] = 70h DECODE: IR[15:9] = 7Fh JMP: PC R[s] IR[15:9] = 74h IR[15:9] = 7Ch SHL: R[d] R[s] << 1 {nf,zf,cf}={n,z,c} IR[15:9] = 78h IR[15:9] = 7Bh JE: if (zf==1) PC PC + seir LOAD: R[d] M[ R[s1] ] HALT: IR[15:9] = 79h STORE: M[ R[d] ] R[s1] IR[15:9] = 7Ah LOAD_ imm: R[d] M[PC] PC PC +1 FETCH `timescale 1ps / 100fs /*********************************************************************** * Date: August 11, 2014 * File: 301_control_unit.v * * A Moore finite state machine that implements the major cycles for * fetching and executing instructions for the 301 -bit RISC Processor. ************************************************************************/ //******************************************************************* module cu (clk, reset, IR, N, Z, C, // control unit inputs W_Adr, R_Adr, S_Adr, // these are adr_sel, s_sel, // the control pc_ld, pc_inc, pc_sel, ir_ld, // word output mw_en, rw_en, alu_op, // fields status); // LED outputs //******************************************************************* input clk, reset; // clock and reset input [15:0] IR; // instruction register input input N, Z, C; // datapath status inputs output [2:0] W_Adr, R_Adr, S_Adr; // register file address outputs output adr_sel, s_sel; // mux select outputs output pc_ld, pc_inc, pc_sel, ir_ld; // pc load, pcinc, pc select, ir load output mw_en, rw_en; // memory_write, register_file write output [3:0] alu_op; // ALU opcode output output [7:0] status; // 8 LED outputs to display current state 301 Lab Assignment 8 Page 4

5 /**************************** * data structures * ****************************/ reg [2:0] W_Adr, R_Adr, S_Adr; //these 12 reg adr_sel, s_sel; // fields reg pc_ld, pc_inc; // make up reg pc_sel, ir_ld; // the reg mw_en, rw_en; // control word reg [3:0] alu_op; // of the control unit reg [4:0] state; // present state register reg [4:0] nextstate; // next state register reg [7:0] status; // LED status/state outputs reg ps_n, ps_z, ps_c; // present state flags register reg ns_n, ns_z, ns_c; // next state flags register parameter RESET=0, FETCH=1, DECODE=2, ADD=3, SUB=4, CMP=5, MOV=6, INC=7, DEC=8, SHL=9, SHR=10, LD=11, STO=12, LDI=13, JE=14, JNE=15, JC=, JMP=17, HALT=18, ILLEGAL_OP=31; /********************************* * 301 Control Unit Sequencer * *********************************/ // synchronous state register assignment clk or posedge reset) if (reset) state = RESET; else state = nextstate; // synchronous flags register assignment clk or posedge reset) if (reset) {ps_n,ps_z,ps_c} = 3'b0; else {ps_n,ps_z,ps_c} = {ns_n,ns_z,ns_c}; // combinational logic section for both next state logic // and control word outputs for cpu_execution_unit and memory state ) case ( state ) RESET: begin // Default Control Word Values -- LED pattern = 1111_111 W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000; adr_sel = 1'b0; s_sel = 1'b0; pc_ld = 1'b0; pc_inc = 1'b0; pc_sel=1 b0; ir_ld = 1'b0; mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000; {ns_n,ns_z,ns_c} = 3'b0; status = 8'hFF; FETCH: begin // IR <-- M[PC], PC <- PC+1 -- LED pattern = 1000_000 W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000; adr_sel = 1'b0; s_sel = 1'b0; pc_ld = 1'b0; pc_inc = 1'b1; pc_sel=1 b0; ir_ld = 1'b1; mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000; {ns_n,ns_z,ns_c} = {ps_n,ps_z,ps_c}; // flags remain the same status = 8'h80; nextstate = DECODE; 301 Lab Assignment 8 Page 5

6 DECODE: begin // Default Control Word Values -- LED pattern = 1100_0000 W_Adr = 3'b000; R_Adr = 3'b000; S_Adr = 3'b000; adr_sel = 1'b0; s_sel = 1'b0; pc_ld = 1'b0; pc_inc = 1'b0; pc_sel=1 b0; ir_ld = 1'b0; mw_en = 1'b0; rw_en = 1'b0; alu_op = 4'b0000; {ns_n,ns_z,ns_c} = {ps_n,ps_z,ps_c}; // flags remain the same status = 8'hC0; case ( IR[15:9] ) 7'h70: nextstate = ADD; 7'h71: nextstate = SUB; 7'h72: nextstate = CMP; 7'h73: nextstate = MOV; 7'h74: nextstate = SHL; 7'h75: nextstate = SHR; 7'h76: nextstate = INC; 7'h77: nextstate = DEC; 7'h78: nextstate = LD; 7'h79: nextstate = STO; 7'h7a: nextstate = LDI; 7'h7b: nextstate = HALT; 7'h7c: nextstate = JE; 7'h7d: nextstate = JNE; 7'h7e: nextstate = JC; 7'h7f: nextstate = JMP; default: nextstate = ILLEGAL_OP; case ADD: begin // R[ir(8:6)] <-- R[ir(5:3)] + R[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b00000} // PUT CONTROL WORD FOR EXECUTION OF ADD HERE!!! SUB: begin // R[ir(8:6)] <-- R[ir(5:3)] - R[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b00001} // PUT CONTROL WORD FOR EXECUTION OF SUB HERE!!! CMP: begin // R[ir(5:3)] - R[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b00010} // PUT CONTROL WORD FOR EXECUTION OF CMP HERE!!! MOV: begin // R[ir(8:6)] <-- R[ir(2:0)] - LED pattern = {ns_n,ns_z,ns_c,5 b00011} // PUT CONTROL WORD FOR EXECUTION OF MOV HERE!!! SHL: begin // R[ir(8:6)] <-- R[ir(2:0)] << 1 - LED pattern = {ps_n,ps_z,ps_c,5 b00100} // PUT CONTROL WORD FOR EXECUTION OF SHL HERE!!! SHR: begin // R[ir(8:6)] <-- R[ir(2:0)] >> 1 - LED pattern = {ps_n,ps_z,ps_c,5 b00101} // PUT CONTROL WORD FOR EXECUTION OF SHR HERE!!! INC: begin // R[ir(8:6)] <-- R[ir(2:0)] LED pattern = {ps_n,ps_z,ps_c,5 b00110} // PUT CONTROL WORD FOR EXECUTION OF INC HERE!!! 301 Lab Assignment 8 Page 6

7 DEC: begin // R[ir(8:6)] <-- R[ir(2:0)] LED pattern = {ps_n,ps_z,ps_c,5 b00111} // PUT CONTROL WORD FOR EXECUTION OF DEC HERE!!! LD: begin // R[ir(8:6)] <-- M[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b01000} // PUT CONTROL WORD FOR EXECUTION OF LOAD HERE!!! STO: begin // M[ir(8:6)] <-- R[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b01001} // PUT CONTROL WORD FOR EXECUTION OF STO HERE!!! LDI: begin // R[ir(8:6)] <-- M[PC], PC <-- PC LED pattern = {ps_n,ps_z,ps_c,5 b01010} // PUT CONTROL WORD FOR EXECUTION OF LDI HERE!!! JE: begin // if (ps_z=1) PC <-- PC + se_ir[7:0] - LED pattern = {ps_n,ps_z,ps_c,5 b01100} // PUT CONTROL WORD FOR EXECUTION OF JE HERE!!! JNE: begin // if (ps_z=0) PC <-- PC + se_ir[7:0] - LED pattern = {ps_n,ps_z,ps_c,5 b01101} // PUT CONTROL WORD FOR EXECUTION OF JNE HERE!!! JC: begin // if (ps_c=1) PC <-- PC + se_ir[7:0] - LED pattern = {ps_n,ps_z,ps_c,5 b01110} // PUT CONTROL WORD FOR EXECUTION OF JC HERE!!! JMP: begin // PC <-- R[ir(2:0)] - LED pattern = {ps_n,ps_z,ps_c,5 b01111} // PUT CONTROL WORD FOR EXECUTION OF JMP HERE!!! HALT: begin // Default Control Word Values - LED pattern = {ps_n,ps_z,ps_c,5 b01011} // PUT CONTROL WORD FOR HALT HERE!!! nextstate = HALT; // loop here forever ILLEGAL_OP: begin // Default Control Word Values -- LED pattern = 1111_0000 // PUT CONTROL WORD FOR ILLEGAL OPCODE HERE!!! nextstate = ILLEGAL_OP; // loop here forever case module Note that the 8-bit status register is used to drive the eight LED s (LD7 to LD0) with unique patterns to display what state the CU is in. In addition, for the execution states for all opcodes, we display the concatenation of the present state of the flags register and the instruction opcode. Once the RISC Processor executes a Halt instruction, press reset. Then set the dump_mem switch to 1. Memory will now display location M[00h]. To step through memory, just press the step_mem button to increment the internal mem_counter. This will allow you to verify the address (AD_sel=1) and contents (AD_sel=0) of memory. 301 Lab Assignment 8 Page 7

8 Lab #8 PC Modifications General Statement: In order for your RISC processor to be able to execute both conditional and unconditional jump instructions, there must be some modifications to the CPU_EU module developed in Lab #7. The conditional jump instructions require the PC to be loaded with -bit values that are relative to its current value. Almost all processors do relative jumps by adding the current contents of the PC to a signed offset. If the offset is expressed in less bits than the PC itself (as is usually the case) then there must be a sign extension of the offset to make it the same size as the PC before the addition. The logic diagram showing the modifications that must be made to accommodate this kind of arrangement is show below. The sign extension function is easily done in Verilog using the replication operator: {n{exp}} is equal to n copies of exp concatenated together. Thus, for example, {5{IR[7]}} = {IR[7], IR[7], IR[7], IR[7], IR[7]}. The SignExt logic in the diagram becomes nothing more than one conditional assignment statement that uses the replication operator for sign exting our 8-bit signed offset to a -bit signed offset that is added to the PC. Note, all logic color coded in yellow is combinational logic, whereas all logic color coded in blue is sequential logic. Also note that the only extra control line needed for CPU_EU is the pc_sel control for the 2-to-1 MUX. CPU_EU Integer Datapath DS Reg_Out ALU_Out -bit add pc_sel 1 0 PC_mux pc_ld pc_inc SignExt PC 8 IR ir_ld adr_sel 1 0 adr_mux Address D_out D_in 301 Lab Assignment 8 Page 8

9 Lab #8 Top Level Diagram 301 -bit RISC Processor Address D_out D_in Mem Dump Counter Dump_mem 1 0 mux Address D_in D_out 256x Memory AD_sel 1 0 mux Display Controller 301 Lab Assignment 8 Page 9

10 Memory Address Binary Content Instruction Register Written _000_000_ _1100_1010_ _001_000_ _0011_0101_ _010_000_ _0000_0011_ _011_000_ _100_001_ _011_000_ _011_000_011 0A 0B 0C 0D 0E _101_000_ _011_000_ _110_000_ _110_000_ _000_000_100 0F _ _ _101_000_ _111_110_ _111_000_ _ A 1B 1C 1D 1E 1F Final Contents of CPU Reg s and Memory: Detailed contents of ram_256x8_lab8a.coe initialization file R0 = R4 = M[15] = R1 = R5 = M[] = R2 = R6 = M[17] = R3 = R7 = M[18] = Total # of instructions executed = 301 Lab Assignment 8 Page 10

11 Memory Address Binary Content Instruction Register Written _000_000_ _0000_0001_ _001_000_ _0000_0000_ _010_000_ _0000_0000_ _011_000_ _0000_1111_ _011_011_ _000_000_011 0A 0B 0C _000_000_ _011_000_ _001_000_001 0D _ E _ F _ A 1B 1C 1D 1E 1F Final Contents of Memory M[10] = M[14] = M[11] = M[15] = M[12] = M[] = M[13] = M[17] = Detailed contents of ram_256x8_lab8b.coe initialization file Total # of instructions executed = 301 Lab Assignment 8 Page 11

12 Memory Address Binary Content Instruction Register Written _000_000_ _0000_0001_ _001_000_ _000_000_ _010_000_ _000_000_ _0000_0001_ _011_000_ _0000_0000_ _000_000_001 0A 0B 0C _001_000_ _000_000_ _000_000_010 0D _ E _000_000_011 0F _ _1111_1111_ _0000_0001_1000 1A 1B 1C 1D 1E 1F Final Contents of Memory Detailed contents of ram_256x8_lab8c.coe initialization file M[10] = M[14] = M[18] = M[11] = M[15] = M[19] = M[12] = M[] = M[13] = M[17] = Total # of instructions executed = 301 Lab Assignment 8 Page 12

13 CECS 301 Team Accountability Reporting Sheet Team Member #1: Signature: Modules/dates you worked on: Modules/dates you debugged: Team Member #2: Signature: Modules/dates you worked on: Modules/dates you debugged: Percentage of Work Summary: Team Member#1 Team Member#2 301 Lab Assignment 8 Page 13

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations