CSE140L: Components and Design Techniques for Digital Systems Lab. RTL design. Tajana Simunic Rosing. Source: Vahid, Katz

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1 CSE140L: Components and Design Techniques for Digital Systems Lab RTL design Tajana Simunic Rosing Source: Vahid, Katz 1

2 Lab #4 due next week Outline Report due at the beginning of class (2pm) Demo hours posted on the class website Today: RTL CPU design Next week: CPU design cont. Synthesis from Verilog 2

3 Register Transfer Level (RTL) Design Method 5.2

4 Step 1 Example: Laser-ased Distance Measurer T (in seconds) laser sensor D 2D = T sec * 3*10 8 m/sec Object of interest Example of how to create a high-level state machine to describe desired processor behavior Laser-based distance measurement pulse laser, measure time T to sense reflection Laser light travels at speed of light, 3*10 8 m/sec Distance is thus D = T sec * 3*10 8 m/sec / 2

5 Step 1 Example: Laser-ased Distance Measurer Inputs:, S(1 bit each) Outputs: L (bit), D ( bits) from button D to display Laserbased distance measurer L to laser S from sensor S0? a L = 0 (laser off) D = 0 (distance = 0) Step 1: Create high-level state machine egin by declaring inputs and outputs Create initial state, name it S0 Initialize laser to off (L=0) Initialize displayed distance to 0 (D=0)

6 Step 1 Example: Laser-ased Distance Measurer Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) (button not pressed) from button D to display Laserbased distance measurer L to laser S from sensor a S0 L = 0 D = 0 S1? (button pressed) Add another state, call S1, that waits for a button press stay in S1, keep waiting go to a new state S2 6

7 Step 1 Example: Laser-ased Distance Measurer Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) from button D to display Laserbased distance measurer L to laser S from sensor S0 S1 S2 L = 0 D = 0 L = 1 (laser on) Add a state S2 that turns on the laser (L=1) Then turn off laser (L=0) in a state S3 S3 L = 0 (laser off) a 7

8 Step 1 Example: Laser-ased Distance Measurer Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) Local Registers: Dctr ( bits) S (no reflection) from button D to display Laser-based distance measurer L to laser S from sensor S0 S1 S2 S3 L = 0 D = 0 Dctr = 0 (reset cycle count) Stay in S3 until sense reflection (S) To measure time, count cycles for which we are in S3 To count, declare local register Dctr Increment Dctr each cycle in S3 L = 1 L = 0 Dctr = Dctr + 1 (count cycles) S (reflection)? Initialize Dctr to 0 in S1. S2 would have been O.K. too a 8

9 Step 1 Example: Laser-ased Distance Measurer Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) Local Registers: Dctr ( bits) from button D to display Laser-based distance measurer L to laser S from sensor S S0 S1 S2 S3 S L = 0 Dctr = 0 L = 1 L=0 D = 0 Dctr = Dctr + 1 Once reflection detected (S), go to new state S4 Calculate distance Assuming clock frequency is 3x10 8, Dctr holds number of meters, so D=Dctr/2 After S4, go back to S1 to wait for button again S4 D = Dctr / 2 (calculate D) a 9

10 Step 2: Create a Datapath Datapath must Implement data storage Implement data computations Look at high-level state machine, do three substeps (a) Make data inputs/outputs be datapath inputs/outputs (b) Instantiate declared registers into the datapath (also instantiate a register for each data output) (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations Instantiate: to introduce a new component into a design. 10

11 Step 2 Example: Laser-ased Distance Measurer (a) Make data inputs/outputs be datapath inputs/outputs (b) Instantiate declared registers into the datapath (also instantiate a register for each data output) (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) Local Registers: Dctr ( bits) S0 S1 S2 S3 L = 0 D = 0 Dctr = 0 Datapath clear count S Q Dctr: -bit up-counter S L = 1 L=0 Dctr = Dctr + 1 clear load I Q S4 D = Dctr / 2 (calculate D) Dreg: -bit register D a 11

12 Step 2 Example: Laser-ased Distance Measurer (c) (continued) Examine every state and transition, and instantiate datapath components and connections to implement any data computations Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) Local Registers: Dctr ( bits) Datapath clear count S S0 S1 S2 S3 L = 0 D = 0 Dctr = 0 Q Dctr: -bit up-counter S L = 1 L=0 Dctr = Dctr + 1 clear load >>1 I Q Dreg: -bit register D S4 D = Dctr / 2 (calculate D) 12 a

13 Step 2 Example Showing Mux Use Localregisters: E,F, G, R ( bits) E F G E F G E F G T0 R = E + F A + A + add_a_s0 add s T1 R = R + G a R R A + (a) (b) (c) R Introduce mux when one component input can come from more than one source (d) 13

14 Step 3: Connecting the Datapath to a Controller from button to display D Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt 300 MHz Clock Datapath L S to laser from sensor Laser-based distance measurer example Easy just connect all control signals between controller and datapath Datapath Dreg_clr Dreg_ld Dctr_clr Dctr_cnt clear count Q Dctr: -bit up-counter clear load I Q Dreg: -bit register D 14

15 from but ton to displ ay D Controller FSM has same structure as highlevel state machine Inputs/outputs all bits now Replace data operations by bit operations using datapath Step 4: Deriving the Controller s FSM Dreg_clr Dreg_ld Dctr_clr Dctr_cnt 300 Hz MClock Datapath L to laser from sensor S Inputs:, S (1 bit each) Outputs: L (bit), D ( bits) Local Registers: Dctr ( bits) S S0 S1 S2 S3 S L = 0 Dctr = 0 L = 1 L=0 D = 0 Dctr = Dctr + 1 Inputs:, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt S S0 S1 S2 S3 L = 0 L = 0 Dreg_clr = 0 L = 1 Dreg_clr = 0 L = 0 Dreg_ld = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_clr = 0 Dctr_cnt = 0 Dctr_cnt = 0 (clear count) (laser on) Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up) S S4 S4 D = Dctr / 2 (calculate D) L = 0 Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) 15 a

16 Step 4: Deriving the Controller s FSM S S0 S1 S2 S3 S S4 L = 0 L = 0 Dreg_clr = 0 L = 1 Dreg_clr = 0 L = 0 Dreg_ld = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_clr = 0 Dctr_cnt = 0 Dctr_cnt = 0 (clear count) (laser on) Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up) L = 0 Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) Using shorthand of outputs not assigned implicitly assigned 0 Inputs:, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt S S0 S1 S2 S3 L = 0 Dctr_clr = 1 L = 1 L = 0 Dreg_clr = 1 (clear count) (laser on) Dctr_cnt = 1 (laser off) (laser off) (clear D reg) (count up) S S4 Dreg_ld = 1 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) a

17 Step 4 from button to display D Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt 300 MHz Clock Datapath L to laser from sensor S Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Datapath clear count Dctr: -bit up-counter Q clear load I Dreg: -bit register Q Inputs:, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt D S S0 S1 S2 S3 L = 0 Dctr_clr = 1 L = 1 L = 0 Dreg_clr = 1 (clear count) (laser on) Dctr_cnt = 1 (laser off) (laser off) (clear D reg) (count up) S S4 Dreg_ld = 1 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting) Implement FSM as state register and logic (Ch3) to complete the design 17

18 Laser distance Verilog signals 18

19 Laser distance Verilog FSM S S0 S1 S2 S3 S4 S L = 0 Dctr = 0 L = 1 L=0 D = Dctr / 2 D = 0 Dctr = Dctr + 1(calculate D) 19

20 CSE140L: Components and Design Techniques for Digital Systems Lab CPU design Tajana Simunic Rosing Source: Vahid, Katz, Culler 20

21 Introduction Programmable (general-purpose) processor Mass-produced, then programmed to implement different processing tasks Well-known common programmable processors: Pentium, Sparc, PowerPC Lesser-known but still common: ARM, MIPS, 8051, PIC Low-cost embedded processors found in cell phones, blinking shoes, etc. Instructive to design a very simple programmable processor Real processors can be much more complex Instruction memory Data memory PC0 IR n-bit 2x1 Controller Control unit Register file RF ALU Datapath General-purpose processor 21

22 asic Architecture Processing generally consists of: Loading some data Transforming that data Storing that data Datapath: Can read/write data to/from memory Has register file to hold data locally Has ALU to transform local data Data memory n-bit 2x1 Register file RF ALU Datapath 22

23 asic Datapath Operations Load operation: Load data from data memory to RF ALU operation: Transforms data by passing one or two RF register values through ALU, performing operation (ADD, SU, AND, OR, etc.), and writing back into RF. Store operation: Stores RF register value back into data memory Each operation can be done in one clock cycle Data memory D Data memory D Data memory D n-bit 2x1 n-bit 2x1 n-bit 2x1 a Register file RF Register file RF Register file RF ALU ALU ALU Load operation ALU operation Store operation 23

24 asic Datapath Operations Is this a valid single-cycle operation for the given datapath? Move D[1] to RF[1] (i.e., RF[1] = D[1]) Store RF[1] to D[9] and store RF[2] to D[10] Add D[0] plus D[1], store result in D[9] Data memory D Data memory D Data memory D n-bit 2x1 n-bit 2x1 n-bit 2x1 Register file RF Register file RF Register file RF ALU ALU ALU Load operation ALU operation Store operation 24

25 asic Architecture Control Unit D[9] = D[0] + D[1] requires a sequence of four datapath operations: 0: RF[0] = D[0] 1: RF[1] = D[1] 2: RF[2] = RF[0] + RF[1] 3: D[9] = RF[2] Each operation is an instruction Sequence of instructions program Store program in Instruction memory Control unit reads each instruction and executes it on the datapath PC: Program counter address of current instruction IR: Instruction register current instruction Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC Controller IR signals to control the datapath Data memory D n-bit 2x1 Register file RF ALU Control unit Datapath 25

26 asic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 0 >1 Controller IR RF[0]=D[0] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 Controller IR RF[0]=D[0] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 IR RF[0]=D[0] Data memory D D[0]: 99 n-bit 2x1 Register file RF R[0]:?? 99 Control unit (a) Fetch Control unit (b) Decode "load" Controller Control unit Execute (c) Datapath ALU 26

27 asic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 1 >2 Controller IR RF[1]=D[1} Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 Controller IR RF[1]=D[1] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 IR RF[1]=D[1] Data memory D D[1]: 102 n-bit 2x1 Register file RF R[1]:?? 102 Control unit (a) Fetch Control unit (b) Decode "load" Controller Control unit Execute (c) Datapath ALU 27

28 asic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 2 >3 Controller Control unit (a) Fetch IR RF[2]=RF[0]+RF[1] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 Controller Control unit (b) Decode IR RF[2]=RF[0]+RF[1] "ALU (add)" Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 Controller Control unit IR RF[2]=RF[0]+RF[1] Execute (c) Data memory D n-bit 2x1 Register file RF R[2]:?? 201 Datapath ALU

29 asic Architecture Control Unit To carry out each instruction, the control unit must: Fetch Read instruction from inst. mem. Decode Determine the operation and operands of the instruction Execute Carry out the instruction's operation using the datapath Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 3 >4 Controller IR D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 4 Controller IR D[9]=RF[2] Instruction memory I 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] PC 4 IR D[9]=RF[2] Data memory D D[9]=?? 201 n-bit 2x1 Register file RF R[2]: 201 Control unit (a) Fetch Control unit (b) Decode "store" Controller Control unit Execute (c) Datapath ALU 29

30 Creating a Sequence of Instructions Create sequence of instructions to compute D[3] = D[0]+D[1]+D[2] One possible sequence Alternative sequence First load data memory First load D[0] and D[1] and locations into register file add them R[3] = D[0] R[1] = D[0] R[4] = D[1] R[2] = D[1] R[2] = D[2] R[1] = R[1] + R[2] (Note arbitrary register locations) Next, perform the additions Next, load D[2] and add R[2] = D[2] R[1] = R[3] + R[4] R[1] = R[1] + R[2] Finally, store result D[3] = R[1] R[1] = R[1] + R[2] Finally, store result D[3] = R[1] 30

31 Three-Instruction Programmable Processor 8.3 Instruction Set List of allowable instructions and their representation in memory, e.g., Load instruction 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2} Instruction memory 0: : : : I Instructions in 0s and 1s machine code opcode operands 31

32 Program for Three-Instruction Processor Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2} Instruction memoryi 0: : : : Computes D[9]=D[0]+D[1] Data memory D PC IR n-bit 2 1 Register file RF Controller ALU Control unit Datapath 32

33 Program for Three-Instruction Processor Another example program in machine code Compute D[5] = D[5] + D[6] + D[7] 0: // RF[0] = D[5] 1: // RF[1] = D[6] 2: // RF[2] = D[7] 3: // RF[0] = RF[0] + RF[1] // which is D[5]+D[6] 4: // RF[0] = RF[0] + RF[2] // now D[5]+D[6]+D[7] 5: // D[5] = RF[0] Load instruction: 0000 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Store instruction: 0001 r 3 r 2 r 1 r 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 Add instruction: 0010 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 33

34 Assembly Code Machine code (0s and 1s) is hard to work with Assembly code Uses mnemonics Load instruction MOV Ra, d specifies the operation RF[a]=D[d]. a must be 0,1,..., or 15 so R0 means RF[0], R1 means RF[1], etc. d must be 0, 1,..., 255 Store instruction MOV d, Ra specifies the operation D[d]=RF[a] Add instruction ADD Ra, Rb, Rc specifies the operation RF[a]=RF[b]+RF[c] Desired program 0: RF[0]=D[0] 1: RF[1]=D[1] 2: RF[2]=RF[0]+RF[1] 3: D[9]=RF[2] 0: : : : : MOV R0, 0 1: MOV R1, 1 2: ADD R2, R0, R1 3: MOV 9, R2 machine code assembly code 34

35 Control-Unit and Datapath for Three-Instruction Processor To design the processor, we can begin with a high-level state machine description of the processor's behavior Init PC=0 Fetch IR=I[PC] PC=PC+1 Decode op=0000 op=0001 op=0010 Load Store Add RF[ra]=D[d] D[d]=RF[ra] RF[ra] = RF[rb]+ RF[rc] 35

36 Control-Unit and Datapath for Three-Instruction Processor Create detailed connections among components Load Init PC=0 RF[ra]=D[d] Fetch Decode Store D[d]=RF[ra] IR=I[PC] PC=PC+1 op=0000 op=0001 op=0010 Add RF[ra] = RF[rb]+ RF[rc] addr PC clr up rd I Controller data IR Id I I RF_s RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd alu_s0 D_addr 8 addr D_rd rd D_wr 256x wr W_data R_data s 1 -bit 2x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd Rp_data 0 D x RF Rq_data Control unit Datapath s0 A ALU 36

37 Convert high-level state machine description of entire processor to FSM description of controller that uses datapath and other components to achieve same behavior Init PC=0 PC_ clr=1 Load RF[ra]=D[d] D_addr=d D_rd=1 RF_s=1 RF_W_addr=ra RF_W_wr=1 Control-Unit and Datapath for Three-Instruction Processor Fetch Decode op=0000 op=0001 op=0010 Store D[d]=RF[ra] D_addr=d D_wr=1 RF_s=X RF_Rp_addr=ra RF_Rp_rd=1 IR=I[PC] PC=PC+1 I_rd=1 PC=PC+1 PC_inc=1 IR_ld=1 Add RF[ra] RF[ra] = RF[rb]+ = RF[rb]+ RF[rc] RF_Rp_addr=rb RF[rc] RF_Rp_rd=1 RF_s=0 RF_Rq_addr=rc RF_Rq _rd=1 RF_W_addr=ra RF_W_wr=1 alu_s0=1 addr PC clr up rd data Controller IR Id Control unit I RF_W_addr RF_W_wr RF_Rp_addr RF_Rp_rd RF_Rq_addr RF_Rq_rd alu_s0 D_addr 8 addr D_rd rd D_wr 256x wr W_dataR_data RF_s s Datapath 1 0 -bit 2x1 W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd D x RF Rp_data Rq_data s0 A ALU 37

A Six-Instruction Programmable Processor Let's add three more instructions: Load-constant instruction 0011 r 3 r 2 r 1 r 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 MOV Ra, #c specifies the operation RF[a]=c

38 A Six-Instruction Programmable Processor Let's add three more instructions: Load-constant instruction 0011 r 3 r 2 r 1 r 0 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 MOV Ra, #c specifies the operation RF[a]=c Subtract instruction 0100 ra 3 ra 2 ra 1 ra 0 rb 3 rb 2 rb 1 rb 0 rc 3 rc 2 rc 1 rc 0 SU Ra, Rb, Rc specifies the operation RF[a]=RF[b] RF[c] Jump-if-zero instruction 0101 ra 3 ra 2 ra 1 ra 0 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 JMPZ Ra, offset specifies the operation PC = PC + offset if RF[a] is 0 38

39 Extending the Control-Unit and Datapath 1: Load constant loads data from IR[7..0] + 3b a+b-1 PC_ld ld addr PC clr up PC_clr PC_inc IR[7..0] rd data IR Id IR_ld D_addr D_rd D_wr 1 8 RF_W_data 1 RF_s1 RF_s0 8 addr rd 256x wr W_data R_data 2 s1 s0 1 -bit 3x1 0 D 2: ALU subtract instruction control signal. 3: JMPZ: 3a: Detect if the register file s Rp is zero 3b: Let PC load also with PC + IR[7..0]. Controller RF_W_addr RF_Rp_addr RF_Rq_addr W_data W_addr W_wr Rp_addr Rp_rd Rq_addr Rq_rd x RF RF_Rp_zero 3a =0 Rp_data Rq_data Control unit alu_s1 alu_s0 2 Datapath s1 s0 A ALU s s ALU operation pass A through A+ A- 39

40 40 Controller FSM for the Six-Instruction Processor Fetch Decode Init PC_clr=1 Store I_rd=1 PC_inc=1 IR_ld=1 Load Add D_addr=d D_wr=1 RF_s1=X RF_s0=X RF_Rp_addr=ra RF_Rp_rd=1 RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_add=rc RF_Rq_rd=1 RF_W_addr_ra RF_W_wr=1 alu_s1=0 alu_s0=1 D_addr=d D_rd=1 RF_s1=0 RF_s0=1 RF_W_addr=ra RF_W_wr=1 Subtract Loadconstant Jump-if-zero RF_Rp_addr=rb RF_Rp_rd=1 RF_s1=0 RF_s0=0 RF_Rq_addr=rc RF_Rq_rd=1 RF_W_addr=ra RF_W_wr=1 alu_s1=1 alu_s0=0 RF_Rp_addr=ra RF_Rp_rd=1 RF_s1=1 RF_s0=0 RF_W_addr=ra RF_W_wr=1 Jump-ifzero-jmp PC_ld=1? op=0100 op=0101 op=0010 op=0011 op=0001 op=0000 RF_Rp_zero RF_Rp_zero'

41 Program for the Six-Instruction Processor Count number of non-zero words in D[4] and D[5] Result will be either 0, 1, or 2 Put result in D[9] MOV R0, #0; // initialize result to 0 MOV R1, #1; // constant 1 for incrementing result MOV R2, 4; // get data memory location 4 JMPZ R2, lab1; // if zero, skip next instruction ADD R0, R0, R1; // not zero, so increment result lab1:mov R2, 5; // get data memory location 5 JMPZ R2, lab2; // if zero, skip next instruction ADD R0, R0, R1; //not zero, so increment result lab2:mov 9, R0; // store result in data memory location 9 (a) (b) 41

42 Program Using Input/Output Extensions Underlying assembly code for C expression I0 &&!I1. 0: MOV R0, 240 // move D[240], which is the value at pin I0, into R0 1: MOV R1, 241 // move D[241], which is that value at pin I1, into R1 2: NOT R1, R1 // compute!i1, assuming existence of a complement instruction 3: AND R0, R0, R1 // compute I0 &&!I1, assuming an AND instruction 4: MOV 248, R0 // move result to D[248], which is pin P0 void main() { while (1) { P0 = I0 &&!I1; // F = a and!b, } } addr rd wr 0: 1: 2: 239: 240: 241: 248: 256x D I0 I1 P0 255: P7 W_data R_data 42

43 Summary Programmable processors are widely used Easy availability, short design time asic architecture Datapath with register file and ALU Control unit with PC, IR, and controller Memories for instructions and data Control unit fetches, decodes, and executes Three-instruction processor with machine-level programs Extended to six instructions Real processors have dozens or hundreds of instructions Extended to access external pins Modern processors are far more sophisticated 43

Chapter 8: Programmable Processors

Chapter 8: Programmable Processors Slides to accompany the textbook, First Edition, by, John Wiley and Sons Publishers, 2007. http://www.ddvahid.com Copyright 2007 Instructors of courses requiring Vahid's