Chapter 15: Design Examples. CPU Design Example. Prof. Soo-Ik Chae 15-1
|
|
- Barnaby Waters
- 5 years ago
- Views:
Transcription
1 CPU Design Example Prof. Soo-Ik Chae 5-
2 Partitioned Sequential Machine Datapaths Datapath Unit External Control Inputs Control Unit Finite State Machine Control signals Datapath Logic Clock Datapath Registers Status signals Clock 5-2
3 Application-Driven Architecture Application Architecture Instruction Set Control Sequence Control Unit FSM 5-3
4 RISC ALU Chapter 5: Design Examples Digital circuits are designed to perform arithmetic and/or logic operations, or in general a mixture of them Arithmetic operations : ADD, SUB, MUL, DIV etc. Logic operations : NOT, AND, OR etc. A mathematical problem usually can be decomposed into a number of arithmetic and/or logic operations which may be executed serially or in parallel. However, to save the cost of hardware circuits, usually only one copy of circuit is built for each specific arithmetic or logic function. As a result, the mathematical problem is rearranged into a sequential order of the combinations of these operations. E.g. : partition D = A + B + C into D A + B followed by D D + C These arithmetic or logic circuits are collected together to form an arithmetic and logic unit (ALU), and a set of systematic methods are created for this ALU to invoke the functions built in the ALU These methods are collectively referred to as the instruction set, which may also involve memory access and/or data movement 5-4
5 RISC vs CISC Chapter 5: Design Examples To support the functions of ALU, a number of data elements such as registers and counters are also necessary to help bring data from memory/register to the inputs of ALU and store the output of ALU to memory or registers The entire set of supporting elements plus the ALU as well as its accompanying instruction set is referred to as the central processing unit (CPU) Central processing unit (CPU) As it is suggested by its name, all arithmetic operations are executed by this unit one instruction a time. There are two types of design methodologies for the instruction sets of CPU Reduced instruction-set computers (RISC), which features o A small number of instructions that execute in short cycles o A small number of cycles per instruction Complex instruction-set computers (CISC) 5-5
6 RISC Stored Program Machine (SPM) A RISC store-program machine (SPM) consists of three functional units : a processor, a controller and memory Program instructions and data are stored in memory Instructions are fetched from memory synchronously, decoded and executed to Operate on data with ALU Change the contents of storage registers Change the content of the program counter (PC), instruction register (IR) and the address register (ADD_R) Change the content of memory Retrieve data and instructions from memory Control the movement of data on the system busses 5-6
7 RISC Stored Program Machine (SPM) Chapter 5: Design Examples 5-7
8 Control Functions Functions of the control unit: Determine when to load registers Select the path of data through the multiplexers Determine when data should be written to memory Control the three-state busses in the architecture. 5-8
9 Control Signals Control Signal Action Load_Add_Reg Loads the address register RISC_SPM Load _PC Load_IR Loads Bus_2 to the program counter Loads Bus_2 to the instruction register Controller Load_R Load_R Processor R R PC IR Inc_PC Increments the program counter Load_R2 R2 Sel_Bus Mux Selects among the Program_Counter, Load_R3 Load_PC R3 Sel_Bus_2_Mux R, R, R2, and R3 to drive Bus_ Selects among Alu_out, Bus_, and Inc_PC instruction Sel_Bus Mux Load_IR Mux_ Bus_ memory to drive Bus_2 Load_Add_Reg Load_Reg_Y Reg_Y Load_R Loads general purpose register R Load_R Loads general purpose register R opcode ALU Memory Load_R2 Load_R3 Load_Reg_Y Load Reg_Z Loads general purpose register R2 Loads general purpose register R3 Loads Bus_2 to the register Reg_Y Stores output of ALU in register Reg_Z Load_Reg_Z zero Sel_Bus_2_Mux write alu_zero_flag Zflag Reg_Z Bus_2 2 Mux_2 mem_word Add_R ad dr es s write Loads Bus_ into the SRAM memory 5-9
10 RISC SPM: Instruction Set [] The design of the controller depends on the processor's instruction set. RISC SPM has two types of instructions. Short Instruction 8 bits (basic arithmetic) opcode source destination Long Instruction 6 bits (accessing memory) opcode source destination address don't care don't care 5-
11 RISC SPM: Instruction Set [2] Instruction Set Single-Byte instruction NOP ADD : Dest Source + Des AND : Dest Source & Des. NOT : Dest Source SUB : Dest Source - Des Two-Byte instruction RD : Dest Memory WR : Memory Source BR : PC Address BRZ : PC Address if zero flag == Opcode Source Dest. Opcode Source Dest. X X Address 5-
12 RISC SPM: Instruction Set [3] Instr Instruction Word Action opcode src dest NOP???? none ADD src dest dest <= src + dest SUB src dest dest <= dest - src AND src dest dest <= src && dest NOT src dest dest <= ~src RD*?? dest dest <= memory[add_r] WR* src?? memory[add_r] <= src BR*???? PC <= memory[add_r] BRZ*???? PC <= memory[add_r] HALT???? Halts execution until reset * Requires a second word of data;? denotes a don't care. 5-2
13 Controller Design Three phases of operation: fetch, decode, and execute. Fetching: Retrieves an instruction from memory (2 clock cycles) Decoding: Decodes the instruction, manipulates datapaths, and loads registers ( cycle) Execution: Generates the results of the instruction (,, or 2 cycles) 5-3
14 Controller States [] S_idle State entered after reset is asserted. No action. S_fet S_fet2 Load the Add_R with the contents of the PC Load the IR with the word addressed by the Add_R, Increment the PC S_dec Decode the IR Assert signals to control datapaths and register transfers. S_ex Execute the ALU operation for a single-byte instruction, Conditionally assert the zero flag, Load the destination register 5-4
15 Controller States [2] S_rd S_rd2 Load Add_R with the second byte of an RD instruction Increment the PC. Load the destination register with memory[add_r] S_wr S_wr2 Load Add_R with the second byte of a WR instruction, Increment the PC. Write memory[add_r] with the source register S_br S_br2 Load Add_R with the second byte of a BR instruction Increment the PC. Load the PC with the memory[add_r] S_halt Default state to trap failure to decode a valid instruction Which states are similar? 5-5
16 RISC-SPM controller : The machine has three phases of operation: fetch, decode and execute A total states S_idle: initial state S_fet: addr reg PC, S_fet2: load instruction mem[addr] S_dec: decode the instr and assert control signals to datapath S_ex: execute the ALU for single-byte instr and load dest reg S_rd: addr reg 2nd byte of a RD instruction and PC ++ S_rd2: dest mem [S_rd] S_wr: addr reg 2nd byte of a WR instruction and PC ++ S_wr2: mem [S_wr] source S_br: addr reg 2nd byte of a BR instruction and PC++ S_br2: PC mem [S_br] S_halt : trap failure to decode a valid instruction 5-6
17 Instruction Sequence Fetch instruction from memory Decode instruction and fetch operands Execute instruction ALU operations Update storage registers Update program counter (PC) Update the instruction register (IR) Update the address register (ADD_R) Update memory Control datapaths 5-7
18 Controller ASM: NOP/ADD/SUB/AND S_idle rst Instruction Fetch RISC_SPM S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller Load_R Processor R PC Load_R R IR Instruction Decode Execute Load_R2 R2 S_dec 3 Load_R3 Load_PC Inc_PC R3 NOP src = R Sel_R Sel_Bus_ Load_Reg_Y S_ex 4 dest = R Sel_R Sel_ALU Load_R Load_Reg_Z instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y Reg_Y Mux_ Bus_ ADD src = R Sel_R Sel_Bus_ Load_Reg_Y dest = R Sel_R Sel_ALU Load_R Load_Reg_Z opcode ALU Memory SUB AND src = R2 Sel_R2 Sel_Bus_ Load_Reg_Y Sel_R3 Sel_Bus_ Load_Reg_Y dest = R2 Sel_R2 Sel_ALU Load_R2 Load_Reg_Z Sel_R3 Sel_ALU Load_R3 Load_Reg_Z Load_Reg_Z zero Sel_Bus_2_Mux write alu_zero_flag Reg_Z Zflag Bus_2 2 Mux_2 mem_word Add_R ad dr es s
19 Controller ASM: NOT S_idle rst RISC_SPM Instruction Fetch Controller Processor S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Load_R Load_R R R PC IR Load_R2 R2 Instruction Decode Execute Load_R3 Load_PC R3 S_dec 3 Inc_PC instruction Sel_Bus Mux Mux_ Load_IR Bus_ NOP src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z Load_Add_Reg Load_Reg_Y Reg_Y opcode ALU Memory... src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s NOT src = R2 Sel_R2 Sel_Bus_ dest = R2 Load_R2 Sel_ALU Load_Reg_Z zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R... Sel_R3 Sel_Bus_ Load_R3 Sel_ALU Load_Reg_Z 5-9
20 Controller ASM: RD S_idle rst Instruction Fetch RISC_SPM S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller Load_R Processor R PC Load_R R IR Instruction Decode Load_R2 R2 S_dec 3 NOP Sel_PC Sel_Bus_ Load_Add_R 5 Execute S_rd / Sel_Mem Load_Add_R Inc_PC S_rd2 6 dest = R Sel_Mem Load_R Load_R3 Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y R3 Reg_Y Mux_ Bus_... dest = R Sel_Mem Load_R opcode ALU Memory Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s RD dest = R2 Sel_Mem Load_R2 Sel_Mem Load_R3 zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R
21 Controller ASM: WR S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Controller RISC_SPM Processor Load_R R PC Instruction Decode Load_R Load_R2 R R2 IR S_dec 3 NOP Sel_PC Sel_Bus_ Load_Add_R 7 Execute S_wr / Sel_Mem Load_Add_R Inc_PC S_wr2 8 src = R Sel_R write Load_R3 Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y R3 Reg_Y Mux_ Bus_... src= R Sel_R write opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s WR src = R2 Sel_R2 write Sel_R3 write zero Sel_Bus_2_Mux write Zflag Bus_2 2 Mux_2 Add_R
22 Controller ASM: BR/BRZ S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 RISC_SPM Controller Processor Instruction Decode Load_R Load_R R R PC IR S_dec Load_R2 R2 3 Execute Load_R3 Load_PC R3 NOP Sel_PC Sel_Bus_ Load_Add_R 9 S_br / Sel_Mem Load_Add_R S_br2 Sel_Mem Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y... opcode ALU Memory BR zero Inc_PC Load_Reg_Z alu_zero_flag Reg_Z mem_word ad dr es s zero Sel_Bus_2_Mux Zflag 2 Mux_2 Add_R BRZ Bus_2 S_halt write 5-22
23 RISC Stored Program Machine (SPM) RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-23
24 RISC-SPM [] module RISC_SPM (clk, rst); parameter word_size = 8; parameter Sel_size = 3; parameter Sel2_size = 2; wire [Sel_size-: ] Sel_Bus Mux; wire [Sel2_size-: ] Sel_Bus_2_Mux; input clk, rst; // Data Nets wire zero; wire [word_size-: ] instruction, address, Bus_, mem_word; // Control Nets wire Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR; wire Load_Add_R, Load_Reg_Y, Load_Reg_Z; wire write; 5-24
25 RISC-SPM [2] Processing_Unit M_Processor (instruction, zero, address, Bus_, mem_word, Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst); Control_Unit M_Controller (Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); Memory_Unit M2_MEM (.data_out(mem_word),.data_in(bus_),.address(address),.clk(clk),.write(write) ); endmodule /* For parameters that occur in multiple modules, include them in a separate file (e.g., definitions.v) and then use `include definitions.v */ 5-25
26 5-26
27 Processing unit of the RISC SPM RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Mux_ Bus_ Load_Add_Reg Load_Reg_Y opcode Reg_Y ALU Memory 7 signals except rst and clk alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-27
28 Processing Unit [] module Processing_Unit (instruction, Zflag, address, Bus_, mem_word, Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst); parameter word_size = 8; parameter op_size = 4; parameter Sel_size = 3; parameter Sel2_size = 2; output [word_size-: ] output input [word_size-: ] input input [Sel_size-: ] input [Sel2_size-: ] input input instruction, address, Bus_; Zflag; mem_word; Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC; Sel_Bus Mux; Sel_Bus_2_Mux; Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z; clk, rst; 5-28
29 Processing Unit [2] wire Load_R, Load_R, Load_R2, Load_R3; wire [word_size-: ] Bus_2; wire [word_size-: ] R_out, R_out, R2_out, R3_out; wire [word_size-: ] PC_count, Y_value, alu_out; wire alu_zero_flag; wire [op_size- : ] opcode = instruction [word_size-: word_size-op_size]; Register_Unit R (R_out, Bus_2, Load_R, clk, rst); Register_Unit R (R_out, Bus_2, Load_R, clk, rst); Register_Unit R2 (R2_out, Bus_2, Load_R2, clk, rst); Register_Unit R3 (R3_out, Bus_2, Load_R3, clk, rst); Register_Unit Reg_Y (Y_value, Bus_2, Load_Reg_Y, clk, rst); 5-29
30 Processing Unit [3] D_flop Reg_Z (Zflag, alu_zero_flag, Load_Reg_Z, clk, rst); Address_Register Add_R (address, Bus_2, Load_Add_R, clk, rst); Instruction_Register IR (instruction, Bus_2, Load_IR, clk, rst); Program_Counter PC (PC_count, Bus_2, Load_PC, Inc_PC, clk, rst); Multiplexer_5ch Mux_ (Bus_, R_out, R_out, R2_out, R3_out, PC_count, Sel_Bus Mux); Multiplexer_3ch Mux_2 (Bus_2, alu_out, Bus_, mem_word, Sel_Bus_2_Mux); Alu_RISC ALU (alu_zero_flag, alu_out, Y_value, Bus_, opcode); endmodule 5-3
31 Register unit, D_flop, and address register Chapter 5: Design Examples 5-3
32 Register unit, D_flop, and address register Chapter 5: Design Examples 5-32
33 Instruction register 5-33
34 Program Counter module Program_Counter (count, data_in, Load_PC, Inc_PC, clk, rst); parameter word_size = 8; output [word_size-: ] count; input [word_size-: ] data_in; input Load_PC, Inc_PC; input clk, rst; reg count; (posedge clk or negedge rst) if (rst == ) count <= ; else if (Load_PC) count <= data_in; else if (Inc_PC) count <= count +; endmodule 5-34
35 5-Input Multiplexor module Multiplexer_5ch (mux_out, data_a, data_b, data_c, data_d, data_e, sel); parameter word_size = 8; output [word_size-: ] mux_out; input [word_size-: ] data_a, data_b, data_c, data_d, data_e; input [2: ] sel; assign mux_out = endmodule (sel == )? data_a: (sel == )? data_b : (sel == 2)? data_c: (sel == 3)? data_d : (sel == 4)? data_e : 'bx; /* Implementation for Multiplexer_3ch is similar */ What would happen if we left out 'bx? 5-35
36 ALU Chapter 5: Design Examples module Alu_RISC (alu_zero_flag, alu_out, data_, data_2, sel); parameter word_size = 8, op_size = 4; // Opcodes parameter NOP = 4'b, ADD = 4'b, SUB = 4'b, AND = 4'b, NOT = 4'b, RD = 4'b, WR = 4'b, BR = 4'b, BRZ = 4'b; output alu_zero_flag; output [word_size-: ] alu_out; input [word_size-: ] data_, data_2; input [op_size-: ] sel; reg alu_out; assign alu_zero_flag = ~ alu_out; (sel or data_ or data_2) case (sel) NOP: alu_out = ; ADD: alu_out = data_ + data_2; SUB: alu_out = data_2 - data_; AND: alu_out = data_ & data_2; NOT: alu_out = ~ data_2; default: alu_out = ; endcase endmodule 5-36
37 Control unit of the RISC SPM RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R Bus_2 write 5-37
38 Control Unit [] module Control_Unit (Load_R, Load_R, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); parameter word_size = 8, op_size = 4, state_size = 4; parameter src_size = 2, dest_size = 2, Sel_size = 3, Sel2_size = 2; // State Codes parameter S_idle =, S_fet =, S_fet2 = 2, S_dec = 3; parameter S_ex = 4, S_rd = 5, S_rd2 = 6; parameter S_wr = 7, S_wr2 = 8, S_br = 9, S_br2 =, S_halt = ; // Opcodes parameter NOP =, ADD =, SUB = 2, AND = 3, NOT = 4; parameter RD = 5, WR = 6, BR = 7, BRZ = 8; // Source and Destination Register Codes parameter R =, R =, R2 = 2, R3 = 3; // See textbook for output, input, and reg declarations 5-38
39 Control Unit [2] 5-39
40 Control Unit [3] // Mux selectors assign Sel_Bus Mux[Sel_size-: ] = Sel_R? : Sel_R? : Sel_R2? 2: Sel_R3? 3: Sel_PC? 4: 3'bx; assign Sel_Bus_2_Mux[Sel2_size-: ] = Sel_ALU? : Sel_Bus_? : Sel_Mem? 2: 2'bx; (posedge clk or negedge rst) begin: State_transitions if (rst == ) state <= S_idle; else state <= next_state; end (state or opcode or src or dest or zero) begin: Output_and_next_state // set default values for control signals Sel_R = ; Sel_R = ; Sel_R2 = ; Sel_R3 = ; Sel_PC = ; Load_R = ; Load_R = ; Load_R2 = ; Load_R3 = ; Load_PC = ; Load_IR = ; Load_Add_R = ; Load_Reg_Y = ; Load_Reg_Z = ; Inc_PC = ; Sel_Bus_ = ; Sel_ALU = ; Sel_Mem = ; write = ; err_flag = ; // Used for de-bug in simulation next_state = state; 5-4
41 Control Unit [4] case (state) S_idle: next_state = S_fet; S_fet: begin next_state = S_fet2; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // S_fet S_fet2: begin next_state = S_dec; Sel_Mem = ; Load_IR = ; Inc_PC = ; end // S_fet2 S_dec: case (opcode) NOP: next_state = S_fet; ADD, SUB, AND: begin next_state = S_ex; Sel_Bus_ = ; Load_Reg_Y = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase end // ADD, SUB, AND 5-4
42 Control Unit [5] NOT: begin next_state = S_fet; Load_Reg_Z = ; Sel_Bus_ = ; Sel_ALU = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase case (dest) R: Load_R = ; R: Load_R = ; R2: Load_R2 = ; R3: Load_R3 = ; default: err_flag = ; endcase end // NOT 5-42
43 Control Unit [6] RD: begin next_state = S_rd; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // RD WR: begin next_state = S_wr; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // WR BR: begin next_state = S_br; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end // BR BRZ: if (zero == ) begin next_state = S_br; Sel_PC = ; Sel_Bus_ = ; Load_Add_R = ; end else begin next_state = S_fet; Inc PC = ; end // BRZ default : next_state = S_halt; endcase // (opcode) S_ex: begin next_state = S_fet; Load_Reg_Z = Sel_ALU = ; case (dest) R: begin Sel_R = ; Load_R = ; end R: begin Sel_R = ; Load_R = ; end R2: begin Sel_R2 = ; Load_R2 = ; end R3: begin Sel_R3 = ; Load_R3 = ; end default : err_flag = ; endcase end // S_ex 5-43
44 Control Unit [7] S_rd: begin next_state = S_rd2; Sel_Mem = ; Load_Add_R = ; Inc_PC = ; end // S_rd S_wr: begin next_state = S_wr2; Sel_Mem = ; Load_Add_R = ; Inc_PC = ; end // S_wr S_rd2: begin next_state = S_fet; Sel_Mem = ; case (dest) R: Load_R = ; R: Load_R = ; R2: Load_R2 = ; R3: Load_R3 = ; default : err_flag = ; endcase end // S_rd2 S_wr2: begin next_state = S_fet; write = ; case (src) R: Sel_R = ; R: Sel_R = ; R2: Sel_R2 = ; R3: Sel_R3 = ; default : err_flag = ; endcase end // S_wr2 S_br: begin next_state = S_br2; Sel_Mem = ; Load_Add_R = ; end S_br2: begin next_state = S_fet; Sel_Mem = ; Load_PC = ; end S_halt: next_state = S_halt; default: next_state = S_idle; endcase end //state case and always block endmodule 5-44
45 Memory Unit module Memory_Unit (data_out, data_in, address, clk, write); parameter word_size = 8; parameter memory_size = 256; output [word_size-: ] data_out; input [word_size-: ] data_in; input [word_size-: ] address; input clk, write; reg [word_size-: ] memory [memory_size-: ]; assign data_out = memory[address]; (posedge clk) if (write) memory[address] = data_in; endmodule /* How would a more realistic memory differ? */ 5-45
46 Questions on RISC SPM Why not include memory as part of the processing unit? How could the design be simplified? 5-46
47 Testing RISC SPM Clear the memory Load the memory with a simple program and data Execute simple program Reads values from memory into registers Perform subtraction to decrement a loop counter Add register contents while executing the loop Branch to a halt when the loop index is Probe memory locations and control signals to ensure correct execution 5-47
48 Testing RISC SPM Verilog [] module test_risc_spm (); reg rst; wire clk; parameter word_size = 8; reg [8: ] k; Clock_Unit M (clk); RISC_SPM M2 (clk, rst); // define probes wire [word_size-: ] word, word,, word4; // instructions wire [word_size-: ] word28, word29,, word4; // data assign word = M2.M2_SRAM.memory[]; // words to 3 assign word4 = M2.M2_SRAM.memory[4]; assign word28 = M2.M2_SRAM.memory[28]; // words 29 to 39 assign word4 = M2.M2_SRAM.memory[4]; 5-48
49 Testing RISC SPM Verilog [2] initial #28 $finish; initial begin: Flush_Memory // set end point for simulation #2 rst = ; for (k=; k<=255; k=k+) M2.M2_SRAM.memory[k] = ; # rst = ; end // Flush_Memory initial begin: Load_program #5 // opcode_src_dest M2.M2_SRAM.memory[] = 8'b ; M2.M2_SRAM.memory[] = 8'b ; // NOP // Read Mem[3] to R2 M2.M2_SRAM.memory[2] = 3; // R2 = 2 M2.M2_SRAM.memory[3] = 8'b ; // Read Mem[3] to R3 M2.M2_SRAM.memory[4] = 3; // R3 = M2.M2_SRAM.memory[5] = 8'b ; // Read Mem[28] to R M2.M2_SRAM.memory[6] = 28; // R = 6 M2.M2_SRAM.memory[7] = 8'b ; // Read Mem[29] to R M2.M2_SRAM.memory[8] = 29; // R = 5-49
50 Testing RISC SPM Verilog [3] M2.M2_SRAM.memory[9] = 8'b ; // Sub R-R to R M2.M2_SRAM.memory[] = 8'b ; // BRZ M2.M2_SRAM.memory[] = 34; // Holds address for BRZ (39) M2.M2_SRAM.memory[2] = 8'b ; // Add R2+R3 to R3 M2.M2_SRAM.memory[3] = 8'b ; // BR M2.M2_SRAM.memory[4] = 4; // Holds address for BR (9) // Load data M2.M2_SRAM.memory[28] = 6; M2.M2_SRAM.memory[29] = ; M2.M2_SRAM.memory[3] = 2; M2.M2_SRAM.memory[3] = ; M2.M2_SRAM.memory[34] = 39; M2.M2_SRAM.memory[35] = ; M2.M2_SRAM.memory[39] = 8'b ; // HALT M2.M2_SRAM.memory[4] = 9; // Repeat Loop end endmodule 5-5
Design and Verification of a 16-bit RISC Processor using Universal Verification Methodology (UVM)
25 IJEDR Volume 3, Issue 2 ISSN: 232-9939 Design and Verification of a 6-bit RISC Processor using Universal Verification Methodology (UVM) Ajit Shridhar Gangad, 2 Prof.C.Prayline Rajabai M.Tech-VLSI Design,
More informationSynthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis
Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1
More informationCPU Design. 4. There are three status flags, zero (Z), carry (C), and sign (S) which are affected by the arithmetic and logical instructions.
CPU Design Naveen Kr. Sharma - 07CS307 Assignment 9 - th November 009 Avishek Banerjee - 07CS04 Computer Organisation & Architecture Lab Group 8 5th Semester, Autumn 009 ISA Specification. There are 6
More informationComputer Organization. Structure of a Computer. Registers. Register Transfer. Register Files. Memories
Computer Organization Structure of a Computer Computer design as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + Control = finite
More informationThe overall datapath for RT, lw,sw beq instrucution
Designing The Main Control Unit: Remember the three instruction classes {R-type, Memory, Branch}: a) R-type : Op rs rt rd shamt funct 1.src 2.src dest. 31-26 25-21 20-16 15-11 10-6 5-0 a) Memory : Op rs
More informationAdvanced Digital Design with the Verilog HDL
Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu
More informationComputer Organization
Computer Organization! Computer design as an application of digital logic design procedures! Computer = processing unit + memory system! Processing unit = control + datapath! Control = finite state machine
More informationsession 7. Datapath Design
General Objective: Determine the hardware requirement of a digital computer based on its instruction set. Specific Objectives: Describe the general concepts in designing the data path of a digital computer
More informationBlock diagram view. Datapath = functional units + registers
Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs = machine instruction,
More information8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN 0 1 Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box 0 1 START Register operation or output
More informationCPE 335. Basic MIPS Architecture Part II
CPE 335 Computer Organization Basic MIPS Architecture Part II Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE232 Basic MIPS Architecture
More informationVerilog for Synthesis Ing. Pullini Antonio
Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits
More informationCPE300: Digital System Architecture and Design
CPE300: Digital System Architecture and Design Fall 2011 MW 17:30-18:45 CBC C316 Pipelining 11142011 http://www.egr.unlv.edu/~b1morris/cpe300/ 2 Outline Review I/O Chapter 5 Overview Pipelining Pipelining
More informationEE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
More information8-1. Fig. 8-1 ASM Chart Elements 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
8-1 Name Binary code IDLE 000 Register operation or output R 0 RUN Condition (a) State box (b) Example of state box (c) Decision box IDLE R 0 From decision box START Register operation or output PC 0 (d)
More informationLevels in Processor Design
Levels in Processor Design Circuit design Keywords: transistors, wires etc.results in gates, flip-flops etc. Logical design Putting gates (AND, NAND, ) and flip-flops together to build basic blocks such
More informationRTL Design (Using ASM/SM Chart)
Digital Circuit Design and Language RTL Design (Using ASM/SM Chart) Chang, Ik Joon Kyunghee University Process of Logic Simulation and Synthesis Design Entry HDL Description Logic Simulation Functional
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationTopic #6. Processor Design
Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More informationComputer Architecture (part 2)
Computer Architecture (part 2) Topics: Machine Organization Machine Cycle Program Execution Machine Language Types of Memory & Access 2 Chapter 5 The Von Neumann Architecture 1 Arithmetic Logic Unit (ALU)
More informationCSE140 L. Instructor: Thomas Y. P. Lee. March 1, Agenda. Computer System Design. Computer Architecture. Instruction Memory design.
CSE4 L Instructor: Thomas Y. P. Lee March, 26 Agenda Computer System Design Computer Architecture Instruction Memory design Datapath Registers Program Counter Instruction Decoder Lab4 Simple Computer System
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationMicroprogrammed Control Approach
Microprogrammed Control Approach Considering the FSM for our MIPS subset has 10 states, the complete MIPS instruction set, which contains more than 100 instructions, and considering that these instructions
More informationPin Description, Status & Control Signals of 8085 Microprocessor
Pin Description, Status & Control Signals of 8085 Microprocessor 1 Intel 8085 CPU Block Diagram 2 The 8085 Block Diagram Registers hold temporary data. Instruction register (IR) holds the currently executing
More informationECE260: Fundamentals of Computer Engineering
Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction
More informationThe Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationThe MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
More informationRISC Processor Design
RISC Processor Design Single Cycle Implementation - MIPS Virendra Singh Indian Institute of Science Bangalore virendra@computer.org Lecture 13 SE-273: Processor Design Feb 07, 2011 SE-273@SERC 1 Courtesy:
More informationInf2C - Computer Systems Lecture Processor Design Single Cycle
Inf2C - Computer Systems Lecture 10-11 Processor Design Single Cycle Boris Grot School of Informatics University of Edinburgh Previous lectures Combinational circuits Combinations of gates (INV, AND, OR,
More informationEE 2700 Project 2 Microprocessor Design
EE 2700 Project 2 Microprocessor Design This project may be done individually or in teams of two. You may consult others for general questions but not for specific issues. Cheating will not be tolerated
More informationLecture Topics. Announcements. Today: Single-Cycle Processors (P&H ) Next: continued. Milestone #3 (due 2/9) Milestone #4 (due 2/23)
Lecture Topics Today: Single-Cycle Processors (P&H 4.1-4.4) Next: continued 1 Announcements Milestone #3 (due 2/9) Milestone #4 (due 2/23) Exam #1 (Wednesday, 2/15) 2 1 Exam #1 Wednesday, 2/15 (3:00-4:20
More informationCC 311- Computer Architecture. The Processor - Control
CC 311- Computer Architecture The Processor - Control Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor
More informationInitial Representation Finite State Diagram Microprogram. Sequencing Control Explicit Next State Microprogram counter
Control Implementation Alternatives Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently;
More informationChapter 4. The Processor Designing the datapath
Chapter 4 The Processor Designing the datapath Introduction CPU performance determined by Instruction Count Clock Cycles per Instruction (CPI) and Cycle time Determined by Instruction Set Architecure (ISA)
More informationGrundlagen Microcontroller Processor Core. Günther Gridling Bettina Weiss
Grundlagen Microcontroller Processor Core Günther Gridling Bettina Weiss 1 Processor Core Architecture Instruction Set Lecture Overview 2 Processor Core Architecture Computes things > ALU (Arithmetic Logic
More informationCS 2461: Computer Architecture I
Computer Architecture is... CS 2461: Computer Architecture I Instructor: Prof. Bhagi Narahari Dept. of Computer Science Course URL: www.seas.gwu.edu/~bhagiweb/cs2461/ Instruction Set Architecture Organization
More informationChapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations
Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations
More informationImplementing the Control. Simple Questions
Simple Questions How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label add $t5, $t2, $t3 sw $t5, 8($t3) Label:... #assume not What is going on during the
More informationCSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
More informationChapter 10. case studies in sequential logic design
Chapter. case studies in sequential logic design This is the last chapter of this course. So far, we have designed several sequential systems. What is the general procedure? The most difficult part would
More informationR-type Instructions. Experiment Introduction. 4.2 Instruction Set Architecture Types of Instructions
Experiment 4 R-type Instructions 4.1 Introduction This part is dedicated to the design of a processor based on a simplified version of the DLX architecture. The DLX is a RISC processor architecture designed
More informationVerilog introduction. Embedded and Ambient Systems Lab
Verilog introduction Embedded and Ambient Systems Lab Purpose of HDL languages Modeling hardware behavior Large part of these languages can only be used for simulation, not for hardware generation (synthesis)
More informationCSE140L: Components and Design
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam
More informationChap 6 Introduction to HDL (d)
Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module
More informationSISTEMI EMBEDDED. Computer Organization Central Processing Unit (CPU) Federico Baronti Last version:
SISTEMI EMBEDDED Computer Organization Central Processing Unit (CPU) Federico Baronti Last version: 20170516 Processing Unit A processor reads program instructions from the computer s memory and executes
More informationLab Assignment No. 1: 4-Bit Binary Full Adder & Subtractor
Lab Assignment No. 1: 4-Bit Binary Full Adder & Subtractor Half Adder: module half_adder(sum,carry,a,b); input a,b; output sum,carry; xor g1(sum,a,b); and g2(carry,a,b); Full Adder: module full_adder(sum,carry,a,b,c);
More informationProblem Set # 6 (Assigned 27 February, Due 9 March)
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2007 R. H. Katz Problem Set # 6 (Assigned 27 February, Due 9 March)
More information361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationDesign of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan)
Microarchitecture Design of Digital Circuits 27 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_7 Adapted from Digital
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationMCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD.
MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD. Tim Böscke, cpldcpu@opencores.org 02/2001 - Revised 10/2004 This documents describes a successful attempt to fit a simple VHDL - CPU into a 32 macrocell
More informationInitial Representation Finite State Diagram. Logic Representation Logic Equations
Control Implementation Alternatives Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently;
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationLC-3 Instruction Processing. (Textbook s Chapter 4)
LC-3 Instruction Processing (Textbook s Chapter 4) Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Usually combine Execute operation
More informationSimple Microprocessor Design By Dr Hashim Ali
Simple Microprocessor Design By Dr Hashim Ali This application note gives an introduction to microprocessor architecture. The goal of the project is to build a 4-bit processor at logic level and then simulate
More informationCISC Processor Design
CISC Processor Design Virendra Singh Indian Institute of Science Bangalore virendra@computer.org Lecture 3 SE-273: Processor Design Processor Architecture Processor Architecture CISC RISC Jan 21, 2008
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationLaboratory 5 Processor Datapath
Laboratory 5 Processor Datapath Description of HW Instruction Set Architecture 16 bit data bus 8 bit address bus Starting address of every program = 0 (PC initialized to 0 by a reset to begin execution)
More informationTHE MICROPROCESSOR Von Neumann s Architecture Model
THE ICROPROCESSOR Von Neumann s Architecture odel Input/Output unit Provides instructions and data emory unit Stores both instructions and data Arithmetic and logic unit Processes everything Control unit
More informationEECS150. Implement of Processor FSMs
EECS5 Section Controller Implementations Fall Implement of Processor FSMs Classical Finite State Machine Design Divide and Conquer Approach: Time-State Method Partition FSM into multiple communicating
More informationRegister Transfer Level in Verilog: Part I
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for
More informationCPU_EU. 256x16 Memory
Team Members We are submitting our own work, and we understand severe penalties will be assessed if we submit work for credit that is not our own. Print Name Print Name GRADER ID Number ID Number Estimated
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationCS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015
CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if
More informationComputer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 3 Fundamentals in Computer Architecture Computer Architecture Part 3 page 1 of 55 Prof. Dr. Uwe Brinkschulte,
More informationTDT4255 Computer Design. Lecture 4. Magnus Jahre. TDT4255 Computer Design
1 TDT4255 Computer Design Lecture 4 Magnus Jahre 2 Outline Chapter 4.1 to 4.4 A Multi-cycle Processor Appendix D 3 Chapter 4 The Processor Acknowledgement: Slides are adapted from Morgan Kaufmann companion
More informationCPU Design Steps. EECC550 - Shaaban
CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the
More informationA-PDF Split DEMO : Purchase from to remove the watermark
A-PDF Split DEMO : Purchase from www.a-pdf.com to remove the watermark 14 Design of SAYEH Processor This chapter shows design of a small computer in Verilog and implementation of it on UP2 using Quartus
More informationIsmail Saad, Pukhraj Vaya, Abu Bakar AR Microelectronics & Photonics Group School of Engineering & IT Universiti Malaysia Sabah (UMS)
A NEW 16-BITS RISC PROCESSOR ARCHITECTURE: CONTROLLER STATE MACHINES AND FUNCTIONAL VERIFICATION USING VERILOG HDL Ismail Saad, Pukhraj Vaya, Abu Bakar AR Microelectronics & Photonics Group School of Engineering
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationCS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016
CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if
More informationIntroduction to CPU Design
١ Introduction to CPU Design Computer Organization & Assembly Language Programming Dr Adnan Gutub aagutub at uqu.edu.sa [Adapted from slides of Dr. Kip Irvine: Assembly Language for Intel-Based Computers]
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More informationECEN 468 Advanced Logic Design
ECEN 468 Advanced Logic Design Lecture 28: Synthesis of Language Constructs Synthesis of Nets v An explicitly declared net may be eliminated in synthesis v Primary input and output (ports) are always retained
More informationLC-3 Instruction Processing
LC-3 Instruction Processing (Textbookʼs Chapter 4)# Next set of Slides:# Textbook Chapter 10-10.2# Instruction Processing# It is impossible to do all of an instruction in one clock cycle.# Processors break
More informationWhy Should I Learn This Language? VLSI HDL. Verilog-2
Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
More informationﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control
معماري كامپيوتر پيشرفته معماري MIPS data path and control abbasi@basu.ac.ir Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions
More informationNote that none of the above MAY be a VALID ANSWER.
ECE 270 Learning Outcome 4-1 - Practice Exam / Solution OUTCOME #4: An ability to design and implement computer logic circuits. Multiple Choice select the single most appropriate response for each question.
More informationGeneral FSM design procedure
Sequential logic examples Basic design approach: a 4-step design process Hardware description languages and finite state machines Implementation examples and case studies finite-string pattern recognizer
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationProcessor Design. ELEC 418 Advanced Digital Systems Dr. Ron Hayne
Processor Design ELEC 418 Advanced Digital Systems Dr. Ron Hayne 68HC11 Programming Model Motorola 68HC11 Microcomputer (CISC) 7 A 0 7 B 0 8-bit Accumulators A & B 15 D 0 16-bit Double Accumulator D 15
More information5.14 Algorithmic State Machine (ASM) Charts
5.4 Algorithmic State Machine (ASM) Charts An ASM chart is an alternative method for describing a state machine More directly shows the sequential steps of a state machine. Easier to understand input priority
More informationObjective now How are such control statements registers and other components Managed to ensure proper execution of each instruction
Control and Control Components Introduction Software application similar to familiar nested Russian dolls As we ve observed earlier Application written in some high level programming language C, C++, C#,
More informationComputer Architecture 2/26/01 Lecture #
Computer Architecture 2/26/01 Lecture #9 16.070 On a previous lecture, we discussed the software development process and in particular, the development of a software architecture Recall the output of the
More informationLecture 11: Control Unit and Instruction Encoding
CSCI25 Computer Organization Lecture : Control Unit and Instruction Encoding Ming-Chang YANG mcyang@cse.cuhk.edu.hk Reading: Chap. 7.4~7.5 (5 th Ed.) Recall: Components of a Processor Register file: a
More information16.1. Unit 16. Computer Organization Design of a Simple Processor
6. Unit 6 Computer Organization Design of a Simple Processor HW SW 6.2 You Can Do That Cloud & Distributed Computing (CyberPhysical, Databases, Data Mining,etc.) Applications (AI, Robotics, Graphics, Mobile)
More informationThe Processor: Datapath & Control
Chapter Five 1 The Processor: Datapath & Control We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationT F The immediate field of branches is sign extended. T F The immediate field of and immediate (andi) and or immediate (ori) is zero extended.
Problem 1 MIPS Instruction Set Architecture (22 pts, 10 mins) Extending the Immediate Field in MIPS (6 pts) Mark the following statements true or false about executing the MIPS Core instructions from column
More informationCSE 140L Final Exam. Prof. Tajana Simunic Rosing. Spring 2008
CSE 140L Final Exam Prof. Tajana Simunic Rosing Spring 2008 NAME: ID#: Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page.
More informationEECS Components and Design Techniques for Digital Systems. Lec 20 RTL Design Optimization 11/6/2007
EECS 5 - Components and Design Techniques for Digital Systems Lec 2 RTL Design Optimization /6/27 Shauki Elassaad Electrical Engineering and Computer Sciences University of California, Berkeley Slides
More informationECE 545 Lecture 12. Datapath vs. Controller. Structure of a Typical Digital System Data Inputs. Required reading. Design of Controllers
ECE 545 Lecture 12 Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) Charts Required reading P. Chu, using VHDL Chapter 1, Finite State Machine: Principle & Practice Chapter
More information