Control Unit Implementation

Transcription

1 Control Unit Implementation

2 Moore Machine Implementation Reset RES PC IF PC MAR, PC + PC Note capture of MBR in these states IF Wait/ IF2 Wait/ Wait/ MAR Mem, Read/Write, Request, Mem MBR Wait/ IF3 Wait/ MBR IR ID Wait/ LD LD Wait/ Wait/ = = IR MAR ST IR MAR, AC MBR MAR Mem, Wait/ MAR Mem, Read/Write, ST Read/Write, Request, Request, Mem MBR Wait/ MBR Mem = AD AD Wait/ Wait/ = IR MAR MAR Mem, Read/Write, Request, Mem MBR BR = BR = IR PC LD2 MBR AC AD2 MBR + AC AC

3 Moore Machine Implementation Memory-Register Interface Timing IF IF2 IF2 IF2 IF3 CLK WAIT Mem Bus Data Valid Latch MBR Invalid Data Latched Invalid Data Latched Valid Data Latched Valid data latched on IF2 to IF3 transition because data must be valid before Wait can go low

4 Moore Machine Implementation Reset Wait IR<5> IR<4> AC<5> Next State Logic 6 states, 4 bit state register Next State Logic: 9 Inputs, 4 Outputs Output Logic: 4 Inputs, 7 Outputs Clock State Output Logic These can be implemented via ROM or PAL/PLA Next State: 52 x 4 bit ROM Output: 6 x 7 bit ROM Read/Write Request PC PC + PC PC ABUS IR ABUS ABUS MAR ABUS PC MAR Memory Address Bus Memory Data Bus MBR MBR Memory Data Bus MBUS IR RBUS AC RBUS MBR ALU ADD ALU PASS A ALU PASS B

5 Moore Machine Implementation Next State Table Reset Wait IR<5> IR<4> AC<5> Current State Next State X X X X X RES () Register Transfer Ops X X X X RES () IF () > PC X X X X IF () IF () X X X IF () IF () X X X IF () IF2 () X X X IF2 () IF2 () X X X IF2 () IF3 () X X X IF3 () IF3 () X X X IF3 () OD () X X OD () LD () X X OD () ST () X X OD () AD () X X OD () BR () PC > MAR, PC + > PC MAR > Mem,, Read, Request, Mem > MBR MBR > IR

6 Moore Machine Implementation Reset Wait IR<5> IR<4> AC<5> Current State Next State Register Transfer Ops X X X X LD () LD () X X X LD () LD () X X X LD () LD2 () X X X X LD2 () IF () X X X X ST () ST () X X X ST () ST () X X X ST () IF () X X X X AD () AD () X X X AD () AD () X X X AD () AD2 () X X X X AD2 () IF () IR > MAR MAR > Mem,, Read, Request, Mem > MBR MBR > AC IR > MAR, AC > MBR MAR > Mem,, Write, Request, MBR > Mem IR > MAR MAR > Mem,, Read, Request, Mem > MBR MBR + AC > AC X X X BR () IF () X X X BR () BR () X X X X BR () IF () IR > PC

7 Moore Machine Implementation State Table Observations: Extensive use of Don't Cares ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step Inputs used only in a small number of states e.g., AC<5> examined only in BR state IR<5:4> examined only in ID state Some outputs always asserted in a group

8 Synchronous Mealy Machine Implementation Standard Mealy Machine has asynchronous outputs These change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges Synchronizer Circuitry at at Inputs Inputs and and Outputs A D Q A' ƒ D Q ƒ' Output Logic STATE A STATE A STATE A' ƒ D Q Output Logic ƒ D Q ƒ' Output Logic

9 Synchronous Mealy Machine Implementation Case I: Synchronizers at Inputs and Outputs CLK A A' cycle cycle cycle 2 S S A/ƒ ƒ ƒ' S2 A asserted in Cycle, f f becomes asserted after 2 cycle delay! This is clearly overkill!

10 Synchronous Mealy Machine Implementation Case II: Synchronizers on Inputs CLK cycle cycle cycle 2 S A/ƒ S A S S A' A'/ƒ ƒ A asserted in Cycle, f follows in next cycle Same as using delayed signal (A') in Cycle!

11 Synchronous Mealy Machine Implementation Case III: Synchronized Outputs CLK A ƒ cycle cycle cycle 2 S S A/ƒ ƒ' A asserted during Cycle, f f asserted in next cycle Effect of A delayed one cycle

12 Microprogrammed Control Unit present input present output z z2 present state s s s2 s3 s s s s s2 s3 s s x z z2 2-way 2-bit MUX select 2 s s s2 s3 x present input 2 present state 2 possible next state z z2 present output

13 Branch Sequencers Concept Microprogrammed Control Unit Implement Next State Logic via ROM Address ROM with current state and inputs Problem: ROM doubles in size for each additional input Branch Sequencer: Next State stored in ROM Each state limited to small number of next states Always a power of 2 Observe: only a small set of inputs are examined in any state

14 Microprogrammed Control Unit 4 Way Branch Sequencer I n p u t s... Mux Mux β α a a a2 a3 a4 a5 64 Word ROM. C S x Z o i x Y n g x X t n x W r a o l. l s N α β α β α β α β W X Y Z state... Current State selects two inputs to form part of ROM address These select one of four possible next states (and output sets) Every state has exactly four possible next states

15 Microprogrammed Control Unit Alternative Horizontal Implementation α and β MUX Control α β α β α β α β A A A2 A3 n- n- n- n- Datapath Control Signals I N P U T S M U X M U X α β bit n : MUX bit n bit state register 2 3 4: MUX bit Input MUX controlled by encoded signals, not state Much fewer inputs than unique states! In this example, input MUX can be 2:! Adding length to ROM word saves on bits vs.. doubling words Vertical format: (7 + 4) x 64 = 344 ROM bits Horizontal format: (7 + 4 x 4 + 2) x 6 = 56 ROM bits

16 Microprogramming Microprogrammed Control Unit Implement control signals by storing 's and 's in a ROM Horizontal vs.. vertical microprogramming Horizontal: ROM output for each control signal Vertical: encoded control signals in ROM, decoded externally some mutually exclusive signals can be combined helps reduce ROM length Register Transfer/Microoperations 4 Register Transfer operations become 7 Microoperations: PC > ABUS IR > ABUS RBUS > AC ALU ADD ALU PASS A ALU PASS B MAR > Address Bus MBR > Data Bus ABUS > IR > IR ABUS > MAR Data Bus > MBR RBUS > MBR > PC PC + > PC ABUS > PC Read/Write Request

17 Horizontal Branch Sequencer Horizontal Branch Sequencer α, β Mux bits 4 x 4 Next State bits 7 Control operation bits 35 bits total RBUS MBR PC PC + PC ABUS PC Read/Write Next States α mux β mux PC ABUS IR ABUS RBUS AC ALU ADD ALU PASS A ALU PASS B MAR Address Bus MBR Data Bus ABUS IR ABUS MAR Data Bus MBR Request Microprogrammed Control Unit Horizontal Microprogramming A A A2 A3

18 Microprogrammed Control Unit Alpha inputs: = Wait, = IR<5> Beta inputs: = AC<5>, = IR<4> current state (address) α mux β mux next states A A A2 A3 PC ABUS IR ABUS RBUS AC ALU ADD ALU PASS A ALU PASS B MAR Address Bus MBR Data Bus MBUS IR ABUS MAR Data Bus MBR RBUS MBR PC PC + PC ABUS PC Read/Write Request RES () IF () IF () IF2 () IF3 () ID () LD () LD () LD2 () ST () ST () AD () AD () AD2 () BR () BR ()

19 Microprogrammed Control Unit Horizontal Microprogramming Advantages: complete parallel access to datapath control points Disadvantages: very long control words -- + bits for real processors NOTE: Not all microoperation combinations make sense! Output Encodings: Group mutually exclusive signals Use external logic to decode Example: > PC, PC + > PC, ABUS > PC mutually exclusive Save ROM bit with external 2:4 Decoder

20 Microprogrammed Control Unit Partially Encoded Control Outputs C O N T R O L R O M ALU ADD ALU PASS B MAR Address Bus MBR Data Bus ABUS MAR Read/Write Request MBUS IR RBUS AC 2 2:4 DEC RBUS MBR ALU PASS A PC PC + PC ABUS PC 2 2:4 DEC PC ABUS IR ABUS Data Bus MBR

21 Microprogrammed Control Unit Vertical Microprogramming More extensive encoding to reduce ROM word length Typically use multiple microword formats: horizontal microcode -- next state + control bits in same word separate formats for control outputs and "branch jumps" may require several microwords in a sequence to implement same function as single horizontal word in the extreme, very much like assembly language programming

22 Microprogrammed Control Unit Branch Jump Compare indicated signal to or Branch Jump Format Type Condition Select Condition Compare 2 6 Next Address = Wait = AC<5> = IR<5> = IR<4> Register Transfer Source, Destination, Operation Register Transfer Format Source Destination Operation ROM Bits : NO OP : PC ABUS : IR ABUS : MAR M : NO OP : RBUS AC : MBUS IR : ABUS MAR : M MBR : RBUS MBR : ABUS PC : MBR M : NO OP : ALU ADD : ALU PASS A : ALU PASS B : PC : PC + PC : Read,Request : Write,Request

23 Microprogrammed Control Unit ROM Contents ROM ADDRESS RES RT IF IF IF2 RT BJ RT BJ IF3 RT BJ ID BJ BJ LD LD RT RT BJ LD2 RT BJ BJ SYMBOLIC CONTENTS PC > ABUS Wait= MAR > M M > MBR Wait= Wait= IR<5>= IR<4>= IR > ABUS MAR > M M > MBR Wait= Wait= Wait= BINARY CONTENTS PC ABUS MAR PC + > PC IF Read IF2 MBUS IR IF3 ID ST ABUS MAR Read LD RBUS AC ALU PASS B IF IF

24 Microprogrammed Control Unit ROM ADDRESS ST SYMBOLIC CONTENTS RT RT ST RT BJ BJ BJ ID BJ AD RT AD RT BJ AD2 RT BJ BJ BJ BR BJ RT BJ IR > ABUS RBUS > MBR BINARY CONTENTS ABUS MAR ALU PASS A MAR > M MBR > M Write Wait= Wait= Wait= IR<4>= IR > ABUS MAR > M M > MBR Wait= Wait= Wait= Wait= AC<5>= IR > ABUS AC<5>= ST IF IF BR ABUS MAR Read AD RBUS AC ALU ADD AD2 IF IF IF ABUS PC IF 32 words x ROM bits = 32 bits total versus 6 x 35 = 56 bits horizontal

25 Control Unit Block Diagram Microprogrammed Control Unit Address ROM T SRC DST OP 3-bit register Enb 3-bit register Enb 3-bit register Enb 3:8 DEC 3:8 DEC 3:8 DEC ALU ADD ALU PASS A ALU PASS B PC PC + PC Read Write RBUS AC MBUS IR ABUS MAR M MBR RBUS MBR ABUS PC MBR M PC ABUS IR ABUS MAR M Read/Write Request Wait AC<5> IR<5> IR<4> Cond Logic LD CNT µpc CLR Reset Clk

26 Microprogrammed Control Unit Condition Logic Microinstruction Type Condition Selector Condition Comparator LD Wait AC<5> IR<5> IR<4> 4: MUX CNT