Lab 5 Mandelbrot Fractal Viewer

Transcription

1 Lab 5 Mandelbrot Fractal Viewer Your task is to design a digital circuit to plot a Mandelbrot Set Fractal over VGA display. Your circuit must generate all control and data signals driving the VGA output of the NEXYS3 board. The design should have a datapath and control unit to realize the function. You can make use of the DSP units and memory available in your FPGA to achieve full functionality of the design. The Mandelbrot Set and Fractals Background: The Mandelbrot set is made up of points plotted on a complex plane to form a fractal. Fractals are infinitely complex patterns that are self-similar across different scales. They are created by repeating a simple process over and over in an ongoing feedback loop. To generate the Mandelbrot set, a surprisingly simple iterative formula is applied to points in the complex plane.! z! = z!!! + c For a given complex number c, if after a number of iterations the absolute value of z! is found to be greater than 2, c escapes the Mandelbrot set, otherwise c belongs to the set. If the point c belongs to the set, the corresponding pixel has a fractal color, otherwise, it has a background color. Fig. 1. The Mandelbrot Set

2 Pseudocode: Each value of c=cx+i cy, in the pseudocode below, corresponds to one pixel of the display region. Based on Fig.1, the plotted region should have the following limits -2 cx=re[c] 1 and -1 cy=im[c] 1 for cy = -1 to 1, step 2/400 do for cx = -2 to 1, step 3/600 do { zx = 0 zy = 0 iteration = 0 // z = z 2 + c = (zx 2 zy 2 + cx) + i (2 zx zy + cy) } while (zx 2 + zy 2 < 4 && iteration < MAX_ITER ){ zxtemp = zx 2 zy 2 + cx zytemp = 2 zx zy + cy zx = zxtemp zy = zytemp iteration++ } x = x_conv(cx) // conversion to the x-coordinate of a pixel y = y_conv(cy) // conversion to the y-coordinate of a pixel if zx 2 + zy 2 < 4 color(x,y) = fractal_color else color(x,y) = background_color The functions x_conv() and y_conv() are used to convert the coordinates of the complex number into x and y coordinate of the pixel on your VGA screen. The conversion can be done as follows x = x_conv(cx) = 20 + (cx-(-2))*(600/3) = *(cx+2) y = y_conv(cy) = (cy-(-1))*(400/2)= *(cy+1)

3 Fixed Point Arithmetic: Taking into consideration the resources available on the Spartan 6 FPGA, you will have to use fixed point arithmetic. The fixed point representation of a number consists of integer and fractional components. To represent fixed point numbers, Q-notation is used. For example, using Q2.4 fixed point representation means that we have 2 bits for the integer part and 4 bits for the fractional parts. A two s complement can be formed by assigning a negative weigth to the leftmost bit. For your project, you can use Q4.28 representation. All computations will involve 4 integer bits and 28 fractional bits. Thus, to represent each number, 32-bits will be required. For arithmetic using fixed-point representation, addition/subtraction can be performed as usual. However, multiplication would result in an increase in the number of bits of the result. For example, the multiplication of a Q4.28 number with another Q4.28 number would result in a Q8.56 number. The result can be converted back to Q4.28 by shifting the number to right by 28 bits. As a result of this shift, the number will still be Q8.28 (36-bits). As all values are continuously being tested for convergence using the Mandelbrot criterion, we can ignore the most significant 4 bits as well without worrying about an overflow. VGA Display Area Configuration and Input/Output Scheme: For the display area on your VGA monitor, your task is to use a rectangular area of the size (600 x 400) pixels to display the Mandelbrot set fractal. This setting would leave the following room for your screen borders. The left and right borders should be 20-pixel each, while the top and bottom border should be 40-pixel each. The top border should display the text The Mandelbrot Set in the center. The font should have dimensions 16x32 in pixels (twice the size of dimensions of the standard tile). The bottom border should display the following information on the screen: 1. Percentage of the display area (i.e., the percentage of c values) evaluated so far, increasing every 0.5%. 2. Progress bar of the maximum size of 200 x 10 pixels (corresponding to 100%), increasing between 0 and 100%, with the step of 0.5% (1 pixel). 3. Total execution time with the step 0.1 s.

4 Use BTNS as the Start/Pause button to start/pause the computations. The color of the fractal and background should change depending on the settings of switches, as described in the table below: Switches Background Color Fractal Color SW0 White Black SW1 Yellow Red SW2 Blue White SW3 Black Red SW4 White Cyan SW5 Black Green SW6 Red Blue SW7 Blue Yellow Bonus Tasks: 1. Increase the speed of calculations, by evaluating 4 values of c in parallel. 2. Determine the maximum speed-up possible by evaluating N values of c in parallel, where N is limited only by the available FPGA resources. 3. Add colors by assigning a different color to each value of c, based on the number of iterations required for the decision (denoted in the pseudocode as iteration), and based on the following formula: color = iteration mod 8. The maximum size of the memory required would be 600 x 400 x 3 = 720,000 bit, which exceeds the memory available in our chip. The display area can be reduced to 300 x 200 pixels to reduce the memory requirement to half.

5 Important Dates Hands-on Sessions and Introductions to the Experiment Demonstration and Deliverables Due for Schedule A Demonstration and Deliverables Due for Schedule B (-8 point penalty for not attempting Lab 6; no penalty for Lab 5) Monday Wednesday Thursday 04/06/ /01/ /02/ /20/ /15/ /16/ /04/ /29/ /30/2015