Introduction to Field Programmable Gate Arrays

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1 Introduction to Field Programmable Gate Arrays Lecture 2/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT

2 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

3 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

4 Why FPGAs for DSP? (1) Reason 1: FPGAs handle high computational workloads Conventional DSP Device (Von Neumann architecture) FPGA Data In Reg Data In Reg0 Reg1 Reg2 Reg255 MAC unit C0 C1 C2... C255 Data Out Data Out 256 Loops needed to process samples All 256 MAC operations in 1 clock cycle

5 FPGAs are ideal for multi-channel DSP designs 20MHz Samples LPF ch1 80MHz Samples LPF LPF LPF ch2 ch3 ch4 LPF Multi Channel Filter Many low sample rate channels can be multiplexed (e.g. TDM) and processed in the FPGA, at a high rate. Interpolation (using zeros) can also drive sample rates higher.

6 Why FPGAs for DSP? (2) Reason 2: Tremendous Flexibility Q = (A x B) + (C x D) + (E x F) + (G x H) can be implemented in parallel + But is this the only way in the FPGA? A B C D E F G H Q

7 Customize Architectures to Suit Your Ideal Algorithms Parallel Semi-Parallel Serial D Q + + D Q + Speed Optimized for? Cost FPGAs allow Area (cost) / Performance tradeoffs

8 Why FPGAs for DSP? (3) Reason 3: Integration simplifies PCBs AFE A/D A/D DDC DDC D/A D/A DDC DDC DUC DUC SDRAM MACs Control DUC DUC DSP Procs. FPGA MACs Control DSP Card Hundreds of Termination Resistors Quad TRx SDRAM PowerPC FPGA SSTL3 Translators Quad TRx ASSP Network Card A/D SDRAM A/D Control PL4 PowerPC PowerPC Gbps ASSP D/A D/A MACs, DUCs, DDCs, Logic PowerPC Control PowerPC CORBA SDRAM

9 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

10 Unsigned integers: positive values only

11 2 s complement

12 Fixed point binary numbers Example: 3 integer bits and 5 fractional bits

13 Fixed point truncation vs. rounding Note that in 2 s complement, truncation is biased while rounding isn t.

14 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

15 The Full Adder (FA)

16 Add/subtract circuit S = A+B when Control= 0 S = A-B when Control= 1

17 Saturation You can t let the data path become arbitrarily wide. Saturation involves overflow detection and a multiplexer. Useful in accumulators (like the one in the PI controller we use in the lab).

18 Multiplication: pencil & paper approach

19 A 4-bit unsigned multiplier using Full Adders and AND gates Of course, you can use embedded multipliers if your chip has them!

20 Constant coefficient multipliers using ROM For easy coefficients, there are smarter ways. E.g. to multiply a number A by 31, left-shift A by 5 places then subtract A.

21 Division: pencil & paper Uses add/subtract blocks presented earlier. MSB produced first: this will usually imply we have to wait for whole operation to finish before feeding result to another block. Longer combinational delays than in multiplication: an N by N division will always take longer than an N by N multiplication.

22 Pipelining the division array

23 Square root Take a division array, cut it in half (diagonally) and you have square root. Square root is therefore faster than division! Although with less ripple through, this block suffers from the same problems as the division array. Alternative approach: first guess with a ROM, then use an iterative algorithm such as Newton-Raphson.

24 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

25 Distributed Arithmetic (DA) 1/2 = = 1 0 ] [ ] [ N n n x n c y = = = ] [ ] [ N n B b b x b n n c y Digital filtering is about sums of products: Let s assume: c[n] constant (prerequisite to use DA) x[n] input signal B bits wide Then: x b [n] is bit number b of x[n] (either 0 or 1) And after some rearrangement of terms: = = = ] [ ] [ 2 B b N n b b n x n c y This can be implemented with an N-input LUT

26 Distributed Arithmetic (DA) 2/2 y = B 1 b= 0 2 b N 1 n= 0 c[ n] x b [ n] x B [0] x 1 [0] x 0 [0] x B [1] x 1 [1] x 0 [1] LUT + Register y x B [N-1] x 1 [N-1] x 0 [N-1] 2-1 Generates a result every B clock ticks. Replicating logic one can trade off speed vs. area, to the limit of getting one result per clock tick.

27 Outline Digital Signal Processing using FPGAs Introduction. Why FPGAs for DSP? Fixed point and its subtleties. Doing arithmetic in hardware. Distributed Arithmetic (DA). COordinate Rotation DIgital Computer (CORDIC).

28 COrdinate Rotation DIgital Computer

29 Pseudo-rotations

30 Basic CORDIC iterations

31 Angle accumulator

32 The scaling factor

33 Rotation Mode

34 Example: calculate sin and cos of 30º

35 Vectoring Mode Vector magnitude

36 Circular coordinate system

37 Other coordinate systems

38 Generalized CORDIC equations

39 Summary of CORDIC functions

40 Precision and convergence

41 FPGA implementation

42 Iterative bit-serial design

43 Acknowledgements Many thanks to Jeff Weintraub (Xilinx University Program) and Bob Stewart (University of Strathclyde) for many of these slides.

Introduction to Field Programmable Gate Arrays

Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.