CS222: Mid Semester Exam: Model

Transcription

1 CS222: Mid Semester Exam: Model Solution Partial Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1

2 Outline Q1 : Instruction Set & Assembly Language RISC/CISC, AL Subroutine for GCD, Stack Size Q2 : ALU Design: Floating Points Density, Rounding off Q3 : ALU Design: Efficient Constant Divider Constant divider by 500, 100 with Max input Q4 : CPU Design:Single/Multi lti Cycle DtPth DataPath Delay and ALP are given, calculate performance 2

3 Q1:a & b Q1a: What are basic differences between a RISC and a CISC machine? Uniformity it of instructions ti in RISC: all are 32 bit Simple set of operations and addressing modes : Register/Reg Imm/Imm Register based architecture with 3 address instructions Rs=Rd1+Rd2 Load/Store access the memory, arithmetic instruction don't access the memory Q2b: How operands are access in typical RISC and CISC machine? RISC: Register/Reg Imm/Imm, Load/Store access the memory, arithmeticinstruction instruction don't access the memory CISC: R R, R M, M M, R+M (Some operands are in mmeory) 3

4 Q1c Write a MIPS assembly language subroutine to compute GCD of two numbers int gcd(int x, int y) { if (y == 0) return x; } else return gcd(y, x % y); Use stack pointer and recursive call to implement this, also include a small code to track the maximum amount of stack area used by your program. 4

5 GCD Code gcd : addi $sp, $sp, 4 # create a 4 word long stack frame move $t0, $sp #simply track sp sw $ra, 0($sp) # save the return address beq $a1, $zero exit_gcd # if $a1=0 go to exit_gcd div $a0, $a1 # Lo=$a0/$a1 ;Hi=$a0 mod $a1 mfhi $t1 # $t1=hi move $a0,$a1 # $a0=$a1 move $a1,$t1 # $a1=$t1 jal gcd # go to gcd exit_g gcd: move $v0,,$ $a0 # $v0=$a0$ lw $ra, 0($sp) # restore the return address addi $sp, $sp, 4 # adjust stack pointer jr $ra # Move R1 R2 or addi R1, R2, 0 5

6 Q2: Floating point Density ( 1) S x1.mx2 (E 127) A Range of 32 bit Single precision number ±(1 F ) x 2 ( 126 to +127) Density of N bit number with m bit mantissa and e bit exponent ignoring underflow Range/numbers = 2 X ( 2 2 m x 2 (2^e 1) ) / 2 n Density of N bit number with m bit mantissa and e bit exponent without ih ignoring i underflow D= 2 X ( ( 2 2 m x 2 (2^e 1) ) (0.5x2 (2^e 1) ) )/ 2 n Density of floating points are more towards zero and sparse towards higher sides in both + and sides Capable of representation of lower number change the density. This implies toward zero we have many number in smaller ranges 6

7 Q2:Floating points Representing real number with m bit integer part and n bit fractional part. (N=m+n) In this case density will be same all over For integer case it is 2 N /2 N =1 and this case it will be 2(2 m )/2 N. No matters sign bit Rounding off using GRS bit Shift1 four time Vs Shift4 one time If any one mentioned Shift Left: will effect no change is accuracy in both the case. Get full mark 7

8 RShft1 4 times Vs RShft4 1 time Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] Value:[ ] Shift1 4times:[ ] Shift4 1times:[ ] 8

9 Q3 ] Design a circuitry for ATM machine to deliver currency to users where users will enter the amount in multiple of 100. ATM machine have to deliver the currency in the format multiple of Rs 500 and Rs 100 (Amount = 500xN xN 100 ). Maximum amount is Rs 20,000. Assume it give preference to Rs 500 currency and then Rs 100 currency. Example case if user enters Rs 1200, then it wills delivers2x500+2x100 2x500+2x100. Designtakes inputas Amountandgive outputs are N 500 and N 100. Essentially it is integer divider circuit for operations N 500 =(Amount/500) and N 100 =(Amount%500)/100. Either you can use two divider or one divider which can divide by 500 or 100. Design an efficient divider by considering these constant values instead of general value and maximum amount Rs 20,000. Generic divider (A=Q*B+R) have generic values for A and B. [Hint1: divide by 100 then by 5/ divide by 10 unit & shift, Hint2: Naïve algorithm by simple adding 500 each time till it reach the amount takes 20X2=70 unit worst case time. Hint3: X/500= X/512 + ( ( X (X/512) * 500) >=500? 1 :0 ) x/512 is shift, M*500 is M*512 M*8 M*4 ] 9

10 Divider: Thinking N 500 =(Amount/500) and N 100 =(Amount%500)/100 Hint: Divide iid by 100 then by 5, Assume BCD input Amount Multiple of 100 Remove2RightZeros BCD to Binary Divide By 5 //A=Q.B+R step1: i= 0; R = 2 x A; Q = 0; D = B do { step2: if (D R H ) R H = R H D; Q = 2 x Q + 1 else Q = 2 x Q R = 2 x R; i++ } while (i < n) A=Amount/100; B=5; Q will be 6 bit, R will be 3 bit Require a 6 bit substractor QN Q=N 500 RN R=N 100 It will take 6 Cycle to do operation 10

11 Divider: Thinking N 500 =(Amount/500) and N 100 =(Amount%500)/100 Hint: : A/500= A/512 + ( ( A (A/512) * 500) >=500? 1 :0 ) N 100 = (A%500)/100= A (A/500*500)/100, Reuse Previous one, Specialize divider with A (=100, 200,300,400,0 ) and B=100 A/B= Switch (A<<8) { case(0)=0, C(1)=1, C(3)=2,C(4)=3, C(5)=4 } Amount Multiple of 100 M ShLft 9 A/512 (A B) >=500 YES INCREMENT ShLft 9 ShLft3 ShLft2 + 3 ADDER M*500 A/500 11

12 Q4 [10] Assume the given single cycle data path for 9 instruction MIPS processor, it get converted to multi cycle li l data path by merging IM and DM, eliminating two adders and putting registers in between states. [5]Calculate execution time of given assembly program (Q4 ALP in Box given bellow) using delay given in Table for single cycle implementation and multi cycle implementation (10ns clock). [5] If ALU takes 40ns that is four clock cycle than what will beperformance of instructions in single cycle case and multi cycle case. Also calculate the performance of given assembly program. 12

13 Q4a: Single Cycle Case Components Delay Delay for Single Cycle IM 10ns Dm 10ns t lw =t i +t R +t A +t M +t R Register File 7ns Adder 10ns ALU 10ns Register 0ns BitManupualtion 0 ns Mux 0ns la $t1, A //Q4 ALP addi $s2, $t1, 400 L: lw $t2, 0($t1) add $s0, $s0, $t2,, blt $t1, $s2, L //run for 100 times //Assume la=lw, addi=add = =44ns ns Clock is Tc >= 44ns Instruction to execute Lw=101, add=201, blt=100 Timeto execute in single cycle addi $t1, $t1, 4 =( )*44ns = 402*44=17688ns 13

14 Q4a: Multi Cycle Case: with out the Assume 10ns Clock Instruction ti to execute last tr of lw instruction Lw=101, add=201, blt=100 Assume Optional tr. As RF is not used in 1 st cycle we can think of overlapping lw with any other instruction So Lw instruction takes 4 cycle instead of 5 Cycle Time to execute in multicycle =(101*4+201*4+100*2)*10 ns = 14080ns Opt Tr 14

15 Q4a: Multi Cycle Case with last tr of lw Assume 10ns Clock Instruction to execute Lw=101, add=201, blt=100 Time to execute in multicycle =(101*5+201*4+100*2)* 10ns = 1507x10ns=15070ns Opt Tr 15

16 Q4b: Adder 40ns, Single Cycle Case Components Delay IM 10ns Delay for Single Cycle Dm 10ns Register File 7ns t lw =t i +t R +t A +t M +t R Adder ALU 10ns 40ns Register 0ns BitManupualtion t 0 ns Mux 0ns = =74ns ns Clock is Tc >= 74ns Instruction to execute Lw=101, add=201, blt=100 la $t1, A //Q4 ALP Timeto execute in single addi $s2, $t1, 400 L: lw $t2, 0($t1) cycle add $s0, $s0, $t2 addi $t1, $t1, 4 =( )*74ns blt $t1, $s2, L //run for 100 times //Assume la=lw, addi=add = 402*74=29748ns 16

17 Q4b: t A =40, Multi Cycle Case: with out the last tr of lw instruction Assume 10ns Clock Instruction ti to execute Lw=101, add=201, blt=100 Assume Optional tr. As RF is not used in 1 st cycle we can think of overlapping lw with any other instruction Time to execute in multi cycle t i =40ns, t R =10ns, t + =40ns, t m =10ns tlw= =100ns, tadd= =100ns, tbeq=40+40=80ns =(101* * *80)ns = 38000ns Opt Tr 17

18 Q4b: t ALU =40ns, Multi Cycle Case with Assume 10ns Clock Instruction ti to execute Lw=101, add=201, blt=100 Time to execute in multicycle t i =40ns, t R =10ns, t + =40ns, t m =10ns m last t R of lw Opt Tr tlw= =110 ns, tadd= =100ns, tbeq=40+40=80ns =(101* * * )ns = 39010ns 18

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