Single cycle MIPS data path without Forwarding, Control, or Hazard Unit

Transcription

1 Single cycle MIPS data path without Forwarding, Control, or Hazard Unit Figure 1: an Overview of a MIPS datapath without Control and Forwarding (Patterson & Hennessy, 2014, p. 287) A MIPS 1 single cycle data path is a hardware description for a MIPS based processor architecture this is one of the simplest data paths that can still operate. In order for your computer to properly execute a program it brakes the complex process up into smaller, easier to preform instructions. These instructions are then loaded into the memory of the IF 2 stage to later be decoded and executed. The MIPS datapath can be broken into 5 main stages IF, ID 3, EX 4, MEM 5, and WB 6. Each of the stages has to work with the next stage and execute a specific task in order to properly execute an instruction. In order to understand the datapath as a whole you must first understand the pieces that go inside it. One of the main components are the registers, they are fast 32x32 memory locations that take in a 5 bit value from 0-31 and temporarily stores a 32 bit value. However, if a register has more locations then the standard 32 it will take in a larger number of bits. 1 Millions of Instructions Per Second, it is a type of instruction set 2 IF stands for Instruction Fetch 3 ID stands for Instruction Decode 4 EX stands for Execution 5 MEM stands for Memory Access 6 WB stands for Write Back

2 Instruction Fetch The first stage is all about keeping track of where the processor is in the current program s instruction stack and feeding the next instruction through the datapath. Initially the IF stage starts out by pulling an address out of the PC 7. This address is 4 words 8 long and is usually represented as a hexadecimal value. Just like how a house address is used to mail a letter this address used to locate the current instruction. This address is then passed by wire signals to two locations inside the IF stage, the adding unit and the instruction memory register. The adding unit is used to advance the current address to the next address. This new PC value is wired to 2 locations one of which doesn t get used till the EX stage so we will not worry about it for now. The second one goes into a multiplexor 9 as one of the inputs. This Multiplexor decides what the new PC value will be based on the input bit that is derived from the control module in the ID stage. The last component in the IF stage is the Instruction memory register. The instruction memory register first finds the memory location that the address. Then once the memory location is known the register outputs the first instruction. Instruction Decode The first instruction is 32 bits when it is initially read from the register. However, once it gets into the ID stage the instruction is separated so it can be decoded. Instructions come in 3 different formats R-type 10, I-type 11, and J-type 12. Each instruction format starts out with a 6 bit op code, this op code is used to control what gets read, written, when to branch 13, and what alu 14 operation gets executed. This control unit is usually above the registers in the ID stage and will not be covered in this description. Other than the control unit the main components of the ID stage are the registers. They are made up the same as before however we place the two 32x32 registers in one component because in order to perform any calculations two values need to be accessed at the same time. The 5 bit address for both the memory locations are the instructions 16 th 25 th bits, and the first read location is stored in the 21 st 25 th bits. These memory values are then passed along to the EX stage for processing. The registers must also allow for information to be written to the registers. This is handled with the addition of a write register port and a write data port. The write register port specifies where the information will be stored and the write data port holds the information to be stored and is controlled by the control unit. The last component is the sign extend module which takes in the 0-15 th bits from the instruction and all that it does is copy the first bit till the instruction is 32 bits long again. 7 Program Counter register, note this register can be nx32 where n is any positive number 8 A word is 8 bits and takes up one memory locations within the PC 9 It selects one input value out of many based on a sector bit(s) and outputs that value 10 R format 32 bits long and as follows 6 bit opcode, 5 bit first register, 5 bit second register, 5 bit destination register, 5 bit shift amount, 6 bit Function; used for most operations. 11 I-format 32 bits long as follows 6bit opcode, 5 fit first register, 5 bit destination register, 16 bit constant or address; used for immediate and data transfer instructions 12 J-format 32 bits long as follows 6 bit opcode, 26 bit address; used for jumping to an address that is far away 13 This happens when loading an instruction that is not sequentially after the last one. 14 Arithmetic logic unit preforms addition, subtraction, multiplication, and more.

3 Execution This sign extended value is then multiplied by 4 because we are working with words and one word is 4 bytes. By using a base 2 counting system we can just shift the value over by 2 decimals to the left this is the same as multiplying by 4. This value then goes into an adding unit who s other input is the new PC value which comes from the IF stage. The adding unit adds the top 4 bits of the PC value and the 32 bit sign extended value to create a jump 15 from the current instruction to a different one. The sign extended value is also used as an input into a multiplexor that is just before the ALU. The multiplexor s other input comes from the second register s output from the ID stage and is controlled with a selector bit from the control unit. The ALU has 3 inputs and 2 outputs, of the inputs 1 is a control signal that tells the ALU what operation to execute and the 2 other inputs are the values that the operation will be performed on. The first value comes from the first register in the ID stage and the second from the multiplexor. The ALU s outputs are a zero wire 16 and the output of the operation. Memory access and Write Back The MEM stage consists of data memory and an and-gate. The and gate takes the zero wire that comes from the ALU in the previous stage and a control signal from the control unit in the ID stage that indicates if a branch should be taken. Then the output of this and-gate is used as the selector bit for the multiplexor in the IF stage. The Data memory is used for long term information storage and has 4 inputs and 1 output. Two of the inputs are control signals that tell the memory when to read and write. The last of the inputs are the address and write data ports. The address port is used to locate the memory location and the write data port contains the information that will be written into the memory location. The data memory only has one output and that is the information that is stored in the memory location. This value then goes into the WB stage, the WB stage consists of a single multiplexor whose inputs are the data from the data memory in the MEM stage, the ALU result from the EX stage, and a control signal from the control unit. This multiplexor s output is wired up to the write data port of the registers in the ID stage. Conclusion We start in the IF stage, the PC starts by outputting an address to the first instruction this value is then incremented by 4 17 and set as an input to the PC. The address that was output by the PC is then input to the instruction memory and used to find then output the first instruction. We are now in the ID stage, from this instruction we read two memory locations from the registers. At the same time we are also sign extending a different part of the same instruction, because depending on the opcode we may need this part of the instruction. The instruction is now decoded and moves into the EX stage. The sign extended value is then multiplied by 4, gets the first 4 bits of its new PC 18 opcode added to it. This value is then wired to the PC where a multiplexor controlled by a control unit will select what the next instruction should be. The ALU takes in the data read from the first register in the ID stage as one input. The second 15 A Jump is preformed when executing a loop, if, case, and more. 16 This wire is used for comparisons and calculating branch instructions 17 this increments the PC to the next sequential instruction 18 Which came from the IF stage

4 input is selected by a multiplexor whose inputs the sign are extended value before it is multiplied by 4 and the data from the second register in the ID stage. Depending on the opcode the multiplexor will select the correct input and the ALU will perform the correct operation sending the result to the MEM stage where it will be stored in memory or to the WB stage to be stored back in the registers for more operations.

5 Works Cited Patterson, D. A., & Hennessy, J. A. (2014). Computer Organization and Design: The Hardware/Software Interface (5th ed.). (T. Green, Ed.) Burlington, MA, United States of America: Morgan Kaufmann. Retrieved July 21, 2016