Raspberry Pi / ARM Assembly. OrgArch / Fall 2018

Transcription

1 Raspberry Pi / ARM Assembly OrgArch / Fall 2018

2 The Raspberry Pi uses a Broadcom System on a Chip (SoC), which is based on an ARM CPU. The 64-bit ARM processor in the Raspberry Pi 3 B+ can be run in either AARCH32 (32-bit) or AARCH64 (64-bit) state. 2

3 Raspberry Pi 3 B+ / BCM2837B0 / A53 Cortex CPU Quad-Core 1.4 GHz / 1GB SRAM / Dual-band WiFi / BLE / Ethernet 3

4 The R in ARM stands for RISC. RISC = Reduced Instruction Set Computing. The philosophy behind RISC is to create a small, highly-optimized set of instructions. (Do one thing really fast) The is different than CISC (Complex Instruction Set Computer). 4

5 Registers are named memory locations on the CPU chip. Applications programmers have access to 16 integer registers (32- bit) in the AARCH32 state, r0 r15. Register Name Register # Usage r0 - r General Purpose r11 or fp 11 Frame Pointer r12 or ip 12 Intraprocessor Scratch r13 or sp 13 Stack Pointer r14 or lr 14 Link Register r15 or pc 15 Program Counter 5

6 There is also a Current Program Status Register (CPSR), which is a register for holding information about the currently executing program. N Z C V Q IT J r s v d GE IT E A I F T M N: negative condition flag Z: zero condition flag C: carry condition flag V: overflow condition flag GE: greater than or equal flags The condition flags are almost always used indirectly, so you do not need to memorize their location in the status registers. 6

7 Condition Codes cons Mnemonic Integer Float Condition Flags 0000 EQ Equal Equal Z == NE Not Equal Not Equal Z == CS Carry Set Greater than, equal, or unordered C == CC Carry clear Less than C == MI Negative Less than N == PL Positive, or zero Greater than, equal, or unordered N == VS Overflow Unordered V == VC No overflow Not unordered V == HI Unsigned higher Greater than, or unordered C == 1 && Z == LS Unsigned lower or same Less than or equal C == 0 Z == GE Signed greater than or equal Greater than on equal N == V 1011 LT Signed less than Less than, or unordered N!= V 1100 GT Signed greater than Greater than Z == 0 && N == V 1101 LE Signed less than or equal Less than, equal, or unordered Z == 1 N!= V 1110 none (AL) Always Always Any 7

8 The CPU also has a special register called the Instruction Register, whose bit pattern determines what the CPU will do. Since instructions are simply bit patterns, they can be stored in memory. The Program Counter Register always has the memory address of (points to) the next instruction to be executed. 8

9 RAM ir ALU / Control CPU Register r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 fp ip Value (32-bits) Memory Bus Address Value (8-bits) sp 15 lr pc 9

10 1. A sequence of instructions is stored in memory. 2. The memory address where the first instruction is located and copied to the program counter. 3. The CPU sends the address in the program counter to memory via the address bus. 4. Memory responds by sending a copy of the state of the bits at that memory location on the data bus, which the CPU then copies into its instruction register. 5. The program counter is automatically incremented to contain the address of the next instruction in memory. 6. The CPU executes the instruction in the instruction register. 7. Go to step 3. 10

11 Unlike the relationship between assembly language and machine language, there is not a one-to-one relationship between higherlevel languages and assembly language. The assembly language generated by a compiler may differ across different releases of the compiler and different optimization levels will generally affect the code that is generated by the compiler. 11

12 /* donothingprog1.c * The minimum components of a C program. * : Bob Plantz */ int main(void) { return 0; } gcc -S -O0 donothingprog1.c -S create assembly language file -O0 no code optimization 12

13 hello.c Preprocessor (cpp) hello.i Compiler (cc1) hello.s Assembler (as) hello.o Linker (ld) hello Source program (text) Modified source program (text) Assembly program (text) Relocatable object programs (binary) Executable object program (binary) gcc Compilation System 13

14 .arch armv6.eabi_attribute 28, 1.eabi_attribute 20, 1.eabi_attribute 21, 1.eabi_attribute 23, 3.eabi_attribute 24, 1.eabi_attribute 25, 1.eabi_attribute 26, 2.eabi_attribute 30, 6.eabi_attribute 34, 1.eabi_attribute 18, 4.file "donothingprog1.c".text.align 2.global main.syntax unified.arm.fpu vfp.type main, %function args = 0, pretend = 0, frame = frame_needed = 1, uses_anonymous_args = link register save eliminated. str fp, [sp, #-4]! add fp, sp, #0 mov r3, #0 mov r0, r3 add sp, fp, sp needed ldr fp, [sp], #4 bx lr.size main,.-main.ident "GCC: (Raspbian rpi1+deb9u1) ".section.note.GNU-stack,"",%progbits 14 donothingprog1.s

15 mov - moves a value into a register mvn - moves the complement of a value into a register add - adds two integers sub - subtracts two integers bx - branches to another location in the program ldr - loads a word from memory into a register str - stores a word from a register into memory 15

16 @ Minimum components of a C program, in assembly : Bob Define my Raspberry Pi.cpu cortex-a53.fpu neon-fp-armv8.syntax modern Program code.text.align 2.global main.type main, %function main: str fp, [sp, save caller frame pointer add fp, sp, establish our frame pointer mov r3, return 0; mov r0, return values go in r0 sub sp, fp, restore stack pointer ldr fp, [sp], restore caller's frame pointer bx back to caller 16

17 @ Minimum components of a C program, in assembly : Bob Define my Raspberry Pi.cpu cortex-a53.fpu neon-fp-armv8.syntax modern Program code.text.align 2.global main.type main, %function main: str fp, [sp, save caller frame pointer add fp, sp, establish our frame pointer mov r3, return 0; mov r0, return values go in r0 comments sub sp, fp, restore stack pointer ldr fp, [sp], restore caller's frame pointer bx back to caller 17

18 @ Minimum components of a C program, in assembly : Bob Define my Raspberry Pi.cpu cortex-a53.fpu neon-fp-armv8.syntax modern Program code.text.align 2.global main.type main, %function main: str fp, [sp, save caller frame pointer add fp, sp, establish our frame pointer mov r3, return 0; mov r0, return values go in r0 assembler directive: used to direct the way in which the assembler translates the file sub sp, fp, restore stack pointer ldr fp, [sp], restore caller's frame pointer bx back to caller 18

19 @ Minimum components of a C program, in assembly : Bob Plantz Define my Raspberry Pi.cpu cortex-a53.fpu neon-fp-armv8.syntax modern Program code.text.align 2.global main.type main, %function main: str fp, [sp, save caller frame pointer add fp, sp, establish our frame pointer mov r3, return 0; mov r0, return values go in r0 sub sp, fp, restore stack pointer ldr fp, [sp], restore caller's frame pointer bx back to caller 19

20 Many ARM instructions include an option to shift one of the data values during the operation that the instruction performs. lsl - logical shift left n bits (1 n 31) lsr - logical shift right n bits (1 n 32) asr - arithmetic shift right n bits (1 n 32) ror - rotate right n bits (1 n 31) rrx - rotate right one bit, with extend (carry bit) 20

21 add Adds two integers add{s}{<c>} {<Rd>,} <Rn>, #<const> % immediate add{s}{<c>} {<Rd>,} <Rn>, <Rm>{, <shift>} % register add{s}{<c>} {<Rd>,} <Rn>, <type> <Rs> % register-shift register <Rd> specifies the destination register. <Rn> and <Rm> specifies the source registers. <Rs> contains the shift amount. If <Rd> is present the result is stored there and <Rn> is unchanged. Otherwise, the result is stored in <Rn> <= const <= +256, or const = +256, +260, +264,, , or const = -261, -265,,

22 mov r0, 12 mov r1, 60 add r2, r0, r1, lsl 2 Register Value r0? r1? r2? 22

23 mov r0, 12 mov r1, 60 add r2, r0, r1, lsl 2 Register Value r0 12 r1? r2? 23

24 mov r0, 12 mov r1, 60 add r2, r0, r1, lsl 2 Register Value r0 12 r1 60 r2? 24

25 mov r0, 12 mov r1, 60 add r2, r0, r1, lsl 2 Register Value r0 12 r1 60 r2 252 r2 = r0 + (r1 << 2) r2 = 12 + (60 << 2) r2 = 12 + ( << 2) r2 = 12 + ( ) r2 = r2 =