Model to Code, Made Simple and Easy Sebastien Dupertuis Application Engineer Applications Engineering Group MathWorks Switzerland June 11, 2015

Transcription

1 Model to Code, Made Simple and Easy Sebastien Dupertuis Application Engineer Applications Engineering Group MathWorks Switzerland June 11, The MathWorks, Inc. 1

2 Challenges to bring an idea into real hardware Software Developers Tools? Investments? ROI? People Specifications Schematics Diagrams Algorithms Hardware Engineers Manager Mechanical Engineers 2

3 switch(idea) { 3

4 case Applications : 4

5 Toyota engine AirSonea device, which connects to a patient s smartphone Philips Healthcare MRI scanner The HB-SIA aircraft on a test flight over San Francisco Bay Photo Solar Impulse Revillard Rezo.ch Sonova s hearing aid and cochlear implant solutions Alstom Grid s HVDC demonstrator system with power converter modules 5

6 case Programming : 6

7 MATLAB C ASCII C++ ASSEMBLY VHDL 7

8 case Hardware : 8

9 ARM Analog Devices Atmel Freescale ALTERA Xilinx MCU / DSP Infineon Intel Texas Instruments STMicroelectronics Renesas Microchip NXP 9

10 case Operating Systems : 10

11 Android VxWorks OS Embedded Linux OSEK-OS Microsoft Windows Embedded 11

12 case Standards : 12

13 AUTOSAR MISRA AC AGC DO-178B/C STANDARDS IEC EN ISO

14 default : printf( Wrong session? ); } 14

15 MBD_Overview(); 15

16 RESEARCH ACTIVITIES REQUIREMENTS DOCUMENTS ANALYSIS SPECIFICATION- DESIGN MODEL Architecture Algorithms Environment Constraints TEST CASES Schematics IMPLEMENTATION Physical Domains TEST & VERIFICATION C, C++ VHDL, Verilog MCU DSP FPGA ASIC Structured Text PLC PAC TEST CASES INTEGRATION 16

17 RESEARCH ACTIVITIES REQUIREMENTS DOCUMENTS ANALYSIS SPECIFICATION- DESIGN MODEL Architecture Algorithms Environment Constraints TEST CASES Schematics IMPLEMENTATION Physical Domains TEST & VERIFICATION C, C++ VHDL, Verilog MCU DSP FPGA ASIC Structured Text PLC PLCPAC TEST CASES INTEGRATION 17

18 Model2Code(); 18

19 Modelling Languages Simulink MATLAB Stateflow 19

20 Code Generation Common Internal Architecture C Code Simulink Unified representation C++ Code HDL Code PLC Code MATLAB Stateflow Mathematical engines Find design errors Test cases Fixed-point autoscaling 20

21 case Code Generation Top 5 : 21

22 In-the-Loop Verification Methodologies 22

23 Software- and Processor- in-the-loop SIL and PIL Communication Gateway Non-Real-Time Synchronization with Host at Each Time Step Execution History Logged signal results comparison Code coverage Execution timing 23

24 Hardware-in-the-Loop HIL, Rapid Prototyping Code Generation Logging and Tuning via Host Hard Real-Time Execution 24

25 FPGA-in-the-Loop FIL, Test Bench Simulation 25

26 Incremental Build Process 26

27 Incremental Build Process Significantly saves time Only build blocks that have changed Helps with partitioning and componentization Scalability! 27

28 Simulink Data Dictionary 28

29 Code Generation for Simulink Data Dictionary Manage data outside of base workspace Componentization Scalability and performance Change tracking and differencing Integration with Simulink Projects Code generation SLX FileSLX FileSLX File SLDD File SLDD File SLDD File Simulink Model 1 Model 2 Model 3 Global Data 29

30 Profiling of Generated Code 30

31 Measure Execution Time Identify hot spots, worst-case execution Supports SIL and PIL Tasks and functions HTML reports 31

32 Intellectual Property Protection 32

33 Password Protected Models Protect design IP for models and generated code Support options Simulation: Allow Accelerator mode Code generation: Include obfuscated code to support code generation Read-only view: Web view of model Password protection: Access protected by password 33

34 case Targets : 34

35 Hardware Support Packages HW Support Packages are: Downloadable from MathWorks websites Available for free with required base product Supported by technical support HW Support Package manages: Licenses 3 rd -party software installation Hardware setup 35

36 Services Automate compile, build, and download Integrate device drivers and RTOS with Simulink Optimize code replacements to your target Verify and validate code execution results 36

37 case Getting FREEd : } 37

38 Programming an heterogeneous system Zynq Platform AXI FPGA AXI ARM 38