What's new in MATLAB and Simulink for Model-Based Design

Transcription

1 What's new in MATLAB and Simulink for Model-Based Design Magnus Jung Application Engineer 2016 The MathWorks, Inc. 1

2 What s New? 2

3 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 3

4 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 4

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6 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 6

7 Messages, Functions and Scheduling 7

8 New SimEvents Discrete-event simulation engine for multidomain system models 8

9 New SimEvents Discrete-event simulation engine for multidomain system models 9

10 New SimEvents Discrete-event simulation engine for multidomain system models How does communication delays effect your system performance? 10

11 CAN simulation with Simulink and SimEvents 11

12 CAN simulation with Simulink and SimEvents 12

13 CAN simulation with Simulink and SimEvents 13

14 CAN simulation with Simulink and SimEvents 14

15 CAN simulation with Simulink and SimEvents 15

16 CAN simulation with Simulink and SimEvents Without background noise Vehicle stops after 14.2 seconds 16

17 CAN simulation with Simulink and SimEvents Without background noise With background noise Vehicle stops after 14.2 seconds Vehicle stops after 15 seconds 17

18 Scheduler Example 18

19 Scheduler Example 19

20 Scheduler Example 20

21 Scheduler Example 21

22 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 22

23 Fast Restart Run consecutive simulations more quickly 23

24 Fast Restart Run consecutive simulations more quickly 24

25 Fast Restart Run consecutive simulations more quickly 25

26 Simulink - Faster consecutive simulations Fast Restart 26

27 Automatic Solver Selection 27

28 Understanding the selected solver 28

29 Understanding the selected solver 29

30 Understanding the selected solver - Solver Profiler 30

31 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 31

32 Three-Way Model Merge 32

33 Report Generation 33

34 Report Generation 34

35 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 35

36 New Product! Simulink Test Develop, Manage, and execute simulation-based tests 36

37 New Product! Simulink Test Automatically generate Test Harness 37

38 New Product! Simulink Test Automatically generate Test Harness Test Sequence block 38

39 New Product! Simulink Test Automatically generate Test Harness Create Test Sequences Manage and Reporting 39

40 New Product! Simulink Test Automatically generate Test Harness Create Test Sequences Manage and Reporting 40

41 Real-Time testing with Simulink Real-Time 41

42 Real-Time testing with Simulink Real-Time 42

43 Model-Based Design Workflow RESEARCH REQUIREMENTS DESIGN Scheduling Event modeling C, C++ Modeling IMPLEMENTATION VHDL, Verilog Performance Structured Text TEST AND VERIFICATION MANAGEMENT AND REPORTING MCU DSP FPGA ASIC PLC INTEGRATION 43

44 Questions! 44

45 Thanks! 45