COMPUTER ORGANIZATION & ARCHITECTURE

Transcription

1 COMPUTER ORGANIZATION & ARCHITECTURE Instructions Sets Architecture Lesson 5b 1

2 STACKS A stack is an ordered set of elements, only one of which can be accessed at a time. The point of access is called the top of the stack. The number of elements in the stack, or length of the stack, can varies. The last element in the stack is the base of the stack Items may only be added to or deleted from the top of the stack. For this reason, a stack is also known as a pushdown list or a last-in-first-out (LIFO) list 2

3 Stack Implementation The stack is a useful structure that forms part of a processor implementation. Stacks are used to manage procedure calls and returns. Stacks may also be useful to the programmer. An example of this is stack expression Some stack operations are shown below 3

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5 Three addresses are needed for proper operation, and these are often stored in processor registers: Stack pointer (SP): Contains the address of the top of the stack. If an item is appended to or deleted from the stack, the pointer is incremented or decremented to contain the address of the new item. Stack base: Contains the address of the bottom location in the reserved block. If an attempt is made to POP when the stack is empty, an error is reported. Stack limit: Contains the address of the other end of the reserved block. If an attempt is made to PUSH when the block is fully utilized for the stack, an error is reported. 5

6 Stack implementations have two key attributes: Ascending/descending: An ascending stack grows in the direction of ascending addresses, starting from a low address and progressing to a higher address. An ascending stack is one in which the SP is incremented when items are pushed and decremented when items are pulled. A descending stack grows in the direction of descending addresses, starting from a high address and progressing to a lower one. Most machines implement descending stacks as a default. 6

7 Full/empty: This is a misleading terminology, because this does not refer to whether the stack is completely full or completely empty. Rather, the SP can either point to the top item in the stack (full method), or the next free space on the stack (an empty method). For the full method, when the stack is completely full, the SP points to the upper limit of the stack. For the empty method, when the stack is completely empty, the SP points to the base of the stack 7

8 Example of Stack Computation f = (a b) / (c + (d * e)) 8

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10 INSTRUCTION FORMAT Defines the layout of bits in an instruction Includes opcode and includes implicit or explicit operand(s). It must indicate the addressing mode for each operand. For most instruction sets, more than one instruction format is used. Usually there are several instruction formats in an instruction set Huge variety of instruction formats have been designed; they vary widely from processor to processor 10

11 INSTRUCTION LENGTH This is the most basic design issue faced in COA. The decision on the length of instruction is affected by and affects: -Memory size -Memory organization -Bus structure -CPU complexity -CPU speed There are some trade-offs that are related to instruction length. The most basic one is between powerful instruction repertoire and saving space. 11

12 ALLOCATION OF BITS There is a trade-off between the number of opcodes and the power of the bit addressing capability. Below are factors used in determining the addressing bits Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity 12

13 Number of addressing modes An addressing mode can be indicated implicitly. For example, certain opcodes might always call for indexing. Also the addressing modes must be explicit, and one or more bits will be needed. Number of operands We saw earlier that fewer addresses can make for complex programs. Computer systems today provide for two operands. Each operand address in the instruction might require its own mode indicator or may have one limited to just one of the address fields. 13

14 WHAT IS CISC? A complex instruction set computer, CISC, is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. One of the most visible forms of revolution with computers is that of programming languages. As the cost of hardware has dropped the relative cost of software has risen. Complexity of modern software has increased the prevalence of faults(bugs). Hence the major cost in the lifecycle of a system is software. 14

15 RATIONALE FOR CISC The response from researchers and industry has been to develop ever powerful and complex high level languages. These high level languages allow the programmer to express algorithms more concisely, take care of much of the detail and normally support structured programming and objectoriented design This solution gave rise to another problem know as the semantic gap Some problems cause by this gap include: -Execution inefficiency -Excessive program size -Compiler complexity 15

16 RATIONALE FOR CISC CONT Designers responded with architectures intended to close this gap. Some key features they considered are; -Large instruction sets -Dozens of addressing modes -Various HLL statements implemented in hardware. Such complex instruction sets are intended to; -Easy the task of the compiler writer -Improve the execution efficiency, because complex sequence of operations can be implemented in microcode -Provide support for even more complex and sophisticated HLLs 16

17 MOTIVATION FOR CISC Complier simplification: The task of the compiler writer is to generate machine instructions for each HLL statement. Machine instructions that resembles HLL statement simplifies the task to be executed. Smaller Programs: Smaller programs improves performance. They also take up less memory. Smaller programs may mean fewer instructions which implies fewer instruction bytes to be fetched. Improved Performance: A complex HLL operation will execute more quickly as a single machine instruction than as a set of more primitive instructions. This also implies that execution time is increased. 17

18 WHAT IS RISC? RISC, or Reduced Instruction Set Computer, is a type of microprocessor architecture that utilizes a small, highlyoptimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. RISC systems have been defined and designed in a variety of ways the elements used by most designs are: -A limited and simple instruction set -A large number of general purpose registers and the use of technology to optimize register usage -An emphasis on the instruction pipeline. 18

19 CHARACTERISTICS OF RISC One-instruction-per-cycle: RISC machine instructions comprise only one cycle of fetch, execute and store. With simple one-cycle instructions, there is no need for microcode Such instructions should execute faster than comparable machine instructions on CISC machines, as it is not necessary to access a micro program control. Register-to-Register O: If most register operations are register-to-register, this simplifies the instruction set and hence the control unit. It also encourages the optimization of the register use. 19

20 CHARACTERISTICS OF RISC Simple addressing modes: Almost all RISC instructions use simple register addressing. Complex addressing modes can be synthesized in software from simple ones. This again simplifies the instruction set and the control unit Simple instruction formats: Generally only one of the few formats are used. Instruction length is fixed and aligned on word boundaries. 20

21 CHARACTERISTICS OF RISC cont Field locations especially the opcodes are fixed. Some benefits include; Simultaneous occurrence of opcode decoding and register operand accessing Simplified formats simplify the control unit Instruction fetching is optimized because word length units are fetched Alignment on word boundary also means that a single instruction does not cross page boundaries 21

22 These characteristics can be assessed to determine the potential benefits of RISC. They can be grouped into two main categories: performance and VLSI implementation Performance More optimizing compilers can be developed. With more smaller primitive instructions, there are major opportunities for moving functions out of loops, reorganizing codes for efficiency, maximizing register utilization. 22

23 Performance cont With simple instructions, a relatively simple control unit is required. It is likely that a simple control unit could be made to execute faster than a more complex one. Instruction Pipelining: Researchers believe that this technique can be applied much more effectively with reduced instruction set 23

24 VLSI IMPLEMENTATION Chip real estate: A CISC processor typically devotes about half of its area to the control unit. A RISC processor typically uses only about 10% of the area for the control unit, using real estate for registers instead Design and implementation time: the simple control unit and circuitry of RISC result in faster design cycles. 24

25 EXAMPLE OF CISC ISA Intel X86, 386/486/Pentium Has 12 addressing modes Register, immediate, Direct, Base, Base+Displacement, index+displacement etc Operand Sizes Can be 8, 16,32,48,64, 0r 80 bit long. It also support string operations Instruction Encoding Smallest instruction is one byte. Longest instruction is 12 bytes. The first bytes contain opcode, mode specifiers and registers. The reminder bytes caters for address displacement and immediate data 25

26 EXAMPLE OF RISC ISA PowerPC Has 8 addressing modes Register direct, immediate, Register indirect, Register indirect with immediate index (load and store), Register indirect, Register indirect with register index (load and store), Operand Sizes Has four operands sizes: 1, 2, 4 or 8 bytes Instruction Encoding Instruction set has 15 different formats with many minor variations All are 32 bits in length. 26