Symbolically the RS-Latch that is being simulated is the one shown below, it s truth table is also given:
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1 Symbolically the RS-Latch that is being simulated is the one shown below, it s truth table is also given: For this example you will need to create two VHDL (.vhd) files one represents the rslatch itself, while the other will test the rslatch. Below is a step by step procedure for accomplishing this. Step (s): 1. The first step that you will need to do is use a text editor or ModelSim to write your VHDL sources. 2. The following codes need to be typed to a text file and then saved as rslatch.vhd and test_rslatch.vhd. a. rslatch.vhd: Auto-generated entity: RS_Latch library IEEE; use IEEE.std_logic_1164.all; -- use IEEE.numeric_std.all; -- uncommment this if you signed or unsigned types entity rs_latch is port ( R: in std_ulogic; S: in std_ulogic; CLK: in std_ulogic; Q: buffer std_ulogic; QBAR: buffer std_ulogic ); end rs_latch; architecture delta of rs_latch is signal G3: std_ulogic; signal G4: std_ulogic; -1-
2 begin G3 <= S nand CLK; G4 <= R nand CLK; QBAR <= G4 nand Q; Q <= G3 nand QBAR; end delta; b. test_rslatch.vhd: Auto-generated test bench for RS_LATCH -- library IEEE; use IEEE.std_logic_1164.all; -- use IEEE.numeric_std.all; -- uncommment this if you signed or unsigned types use std.textio.all; --use work.rs_latch; entity test_bnch is end test_bnch; architecture stimulus of test_bnch is component rs_latch port ( R: in std_ulogic; S: in std_ulogic; CLK: in std_ulogic; Q: buffer std_ulogic; QBAR: buffer std_ulogic ); end component; constant PERIOD: time := 20 ns; -- Top level signals go here... signal R: std_ulogic; signal S: std_ulogic; signal CLK: std_ulogic; signal Q: std_ulogic; signal QBAR: std_ulogic; signal done: boolean := false; --for DUT: d_latch use entity work.d_latch(delta); begin DUT: rs_latch port map ( R => R, S => S, CLK => CLK, Q => Q, -2-
3 QBAR => QBAR ); CLOCK1: process variable clktmp: std_ulogic := '0'; begin wait for PERIOD/2; clktmp := not clktmp; CLK <= clktmp; --clktmp; -- Attach your clock here if done = true then wait; end if; end process; STIMULUS1: process begin -- Sequential stimulus goes here... S <= '0'; R <= '0'; wait for PERIOD; wait for PERIOD; R <= '1', '0' after 25 ns; wait for PERIOD; wait for PERIOD; S <= '1', '0' after 25 ns; wait for 20 ns; R <= '1' after 60 ns, '0' after 72 ns; S <= '1' after 109 ns, '0' after 111 ns; wait for 200 ns; done <= true; wait; end process; end stimulus; 3. In notepad type the above codes in separate files and save them as stated above. Make sure that when you are saving with notepad it saves as rslatch.vhd and not adder.vhd.txt (this is usually fixed by putting the file name in quotes at the saving screen, i.e., rslatch.vhd ). The same instructions applies to test_rslatch.vhd. 4. You can also use the vhdl text editor that comes with ModelSim. This turns out to be much easier than using the text editor, since it can also check for syntax while you write your code. To do the above step start the ModelSim application and do the following: a. Click on File New Source VHDL. It looks as followed. -3-
4 b. Once you ve done this, type the code the space provided. c. When you have finished placing the code in the space provided, click File Save As and save this first file as rslatch.vhd (yes, you will need to type the.vhd part. Note: saved this file and the other to a directory which you will use as your working directory. d. Repeat steps a thru c to complete test_rslatch.vhd, 5. Now that you have your source files let s create a project in which we will add these two files into our project. 6. Assuming that you already have ModelSim running, do the following: a. Click on File New Project. It looks as followed. b. Once you ve done this, you will get the following screen. -4-
5 For the project name it myrslatch. Note: In Unix the procedures thus followed are the same, but when creating a new project, you will be creating the library s name in your home s directory. c. When you have clicked OK, you will get the following screen. You will now click on Add Existing File you are going to add the two sources which we created earlier. You will need to browse for the file (s) when the following window shows. -5-
6 Clicking on the Browse icon will show the following screen and you will need to go to the directory in which you saved your source files. Below is an example of such a scenario. By selecting both of the files and clicking open, you will add both of the files at the same time. You will then get the following screen where the files are added into the file name section, you will now press OK. 7. You will then come across this view where you will have to compile all of your source files. -6-
7 a. If you get errors in the compilation, check that your syntax is correct for your source files. When the compilation is successful you will be returned with the following information a. At the bottom of the above window you will have to hit the tab (titled library) and you will end up with the following screen: b. Now by double-clicking test_bnch, you will get the following view. c. The Objects window contains all of the signal properties that were declared in the source files. Doing the following: i. Go to Add Wave Signal in Region and you will get the waveform window with the added information. This is shown below. -7-
8 ii. Now we are ready to simulate the rslatch. 8. In the command prompt type the following, run 20 eight times (i.e., until you get a total of 160 ns), with each command press enter. You will get the following see a screen similar to this. 9. To complete the project look at your waveform window to view the rslatch s results; you will get the following result, notice the logic in the waveform shows that the truth table from above corresponds to these as shown: -8-
Symbolically a D-Latch can be represented as so, it s truth table is also given:
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