Bruce s VHDL Tutorial By Bruce Misner Lakehead University

Transcription

1 Bruce s VHDL Tutorial By Bruce Misner Lakehead University First circuit to look at is a simple combinational logic circuit. This circuit is just a demo and has no real application. It is a starting point. Firstly this is the whole code to simulate this circuit. entity mycir is port(a,b,c: in bit; out1,out2: out bit); end mycir; architecture rtl of mycir is out1<=(a and b and c) or c after 2ns; out2<=(a and b and c) or a after 2ns; end rtl; entity test is end test; library STD; use STD.textio.all; architecture behaviour of test is component mycir

2 port(a,b,c: in bit; out1,out2:out bit); for all:mycir use entity work.mycir; signal in1,in2,in3,output1,output2:bit; inst1: mycir port map(in1,in2,in3,output1,output2); p1: process variable l:line; file flush : text is out "out.dat"; file inrush : text is in "in.dat"; variable a,b,c,out1,out2:bit; readline(inrush,l); read(l,a); read(l,b); read(l,c); in1<=a; in2<=b; in3<=c; wait for 5ns; write(l,output1); write(l.string( )); write(l,output2); writeline(flush,l); Now, let s break it down. The first thing we do is create an entity for the whole circuit. There are three inputs and two outputs. All are of type bit. entity mycir is port(a,b,c: in bit; out1,out2: out bit); end mycir; Next we describe the architecture of the circuit. This tells the logic functionality of the circuit. architecture rtl of mycir is out1<=(a and b and c) or c after 2ns;

3 out2<=(a and b and c) or a after 2ns; end rtl; The next part is what they term the test bench. The test bench describes how the circuit is to be simulated. In our example we don t describe anything because we will take our input signals from a file later on. We still need to have this in our code. entity test is end test; Next, we include any libraries required to include all of our data types and basic logic declarations. library STD; use STD.textio.all; Now we need to setup our test bench with all of our components and define how they are interconnected. architecture behaviour of test is component mycir port(a,b,c: in bit; out1,out2:out bit); This first part of the test bench is the definition of the testbench followed by the declaration of all components used in our entire circuit. In this case we have configured our entire circuit into one component. The component declaration must be followed by the description of all the ports into and out of our component. for all:mycir use entity work.mycir; The next line tells the compiler that for all instances of the mycir component, it should find its logic function from the entity and architecture of mycir. signal in1,in2,in3,output1,output2:bit; The definition of signals describe how the circuit is connected together. These in essence are the wires connecting the components. inst1: mycir port map(in1,in2,in3,output1,output2);

4 We declared our component above now we instantiate all components required and use the port map to define how the signals tie our components together. Again, this is simple. There is only one component. p1: process variable l:line; file flush : text is out "out.dat"; file inrush : text is in "in.dat"; variable a,b,c,out1,out2:bit; Now we process the circuit, describing how to simulate. In my case I have a file with input binary data and I save my results to an output file. That takes care of the first three declaration lines. The last line will be our local variable used to get the simulation data in and out of our test circuit. readline(inrush,l); read(l,a); read(l,b); read(l,c); in1<=a; in2<=b; in3<=c; wait for 5ns; write(l,output1); write(l.string( )); write(l,output2); writeline(flush,l); I will provide the input and output data files after this description. However, we read a line of data from our input file. Separate it into three different variables and assign those input values to our input signals. We wait for five nanoseconds for the signals to propagate through our circuit. Then we write out our output values to file. Our input data file looks like this:

5 Essentially we are simulating this circuit for all input combinations. If we simulate for forty nanoseconds it will loop in the process and read each input combination and provide the output as follows: Successfully simulated. There are other ways of providing simulation data. This way requires the fewest lines of code which is important if you are using demo software that only allows you forty lines of code. You can gang lines together on one line to help stay within the boundary. Second circuit is a D latch example -- D Latch Example entity dlatch is port(d,clk:in bit;q:out bit); end dlatch; architecture rtl of dlatch is

6 signal dbar,rin,sin,qin,qnin:bit; dbar <= not d; rin <= dbar nand clk; sin <= d nand clk; qnin <= rin nand qin; qin <= sin nand qnin; q <= qin; entity test is end test; library STD; use STD.textio.all; architecture behaviour of test is component dlatch port(d,clk:in bit;q:out bit); for all:dlatch use entity work.dlatch; signal din,clkin,qout:bit; inst1: dlatch port map(din,clkin,qout); p1: process variable l:line; file flush: text is out "out.dat"; file inrush: text is in "in.dat"; variable d,clk,q:bit; readline(inrush,l); read(l,d); read(l,clk); din <= d; clkin <= clk; wait for 5ns; write(l,qout); writeline(flush,l);

7 Now how about this for an edge triggered d latch. This is different from declaring all the gates and connections. Functionally this is a little different being edge triggered not level triggered. architecture rtl of dlatch is process(d,clk) if (clk'event and clk = '1') then q <= d; end if; That is a little better. Now, to make everything complete let us add a set and reset and we will be done. architecture dffarch of dff is process(d,clk,rst,set) if clk'event and clk = '1' then qout <= d;end if; if rst = '1' then qout <= '0';end if; if set = '1' then qout <= '1';end if; Another thing we should briefly touch on is the fact that there are more logic states than just high and low. There is a don t care, weak low, weak high, and a high impedance state for bus logic compatibility. The following is an example of a tristate buffer. LIBRARY ieee; USE ieee.std_logic_1164.all; entity tribuf is port(inp,en:in std_logic;outp:out std_logic); end tribuf; architecture tribuffarch of tribuf is signal input,enable,output:bit; process(inp,en) if en = '1' then outp <= 'Z';

8 else outp <= inp; end if; The high impedance state as well as these other input output types are defined in the ieee library. They are also of the type std_logic. These types will not work with simple bit type. For a tristate input the port must be declared as inout and not just in. The last example is of an four bit latch made of d flip flops. This will show how to create and connect multiple components. entity shift is port (sin,clk:in bit;sout:out bit); end shift; entity dff is port(d,clk:in bit;q:out bit); end dff; architecture rtl of dff is process(d,clk) if (clk'event and clk = '1') then q <= d; end if; architecture genshift of shift is component dff port (d,clk:in bit;q:out bit); signal x:bit_vector(0 to 4); x(0) <= sin; gen1: for i in 0 to 3 generate u:dff port map(x(i),clk,x(i+1)); end generate; sout <= x(4); end genshift; entity test is end test;

9 library STD; use STD.textio.all; architecture behaviour of test is component shift port(d,clk:in bit;q:out bit); for all:shift use entity work.shift; signal din,qout:bit; signal clkin:bit; u1: shift port map(din,clkin,qout); p1: process variable l:line; file flush: text is out "shiftout.dat"; file inrush: text is in "shiftin.dat"; variable d,clk,q:bit; readline(inrush,l); read(l,d); read(l,clk); din <= d; clkin <= clk; wait for 5ns; write(l,qout); writeline(flush,l); We can see in the following that is extracted from above how we generate four d flip flops and string them together with signals that we defined as X. x(0) <= sin; gen1: for i in 0 to 3 generate u:dff port map(x(i),clk,x(i+1)); end generate; sout <= x(4); I hope that this gives you a start on the road to learning VHDL. There is certainly a lot more to it than this. This is just a starter.