Introduction to VHDL. Main language concepts

Transcription

1 Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab support VHDL-93 ADA like syntax, strictly typed language, concurrent Feature rich language for modeling digital systems at system level down to gate level. Only a subset of the language is supported for synthesis. Only RTL VHDL code is synthesizable with most tools The goal with this course is not that you should learn the complete language. ou should learn how to write RTL VHDL code, but also some behavioral stuff for test benches SMD098 Computation Structures Lecture 2 1 Main language concepts Concurrency VHDL can describe activities that are happening in parallel Structure, hierarchy VHDL allows to structure a design in a hierarchical manner Sequential statements VHDL also allows sequential execution of statements. Just like any other programming language Time VHDL allows modeling of time SMD098 Computation Structures Lecture 2 2

2 VHDL design units entity Ent1 is end Ent1; configuration CFG of Ent1 is end CFG; Common design data package PKG is end PKG; architecture A1 of Ex is architecture A2 of Ex is end A; architecture A3 of Ex is end A; end A3; package body PKG is end PKG; Entity declaration Specifies the interface of an entity Architecture body Describes the function of an entity. An entity can have more than one architectures. Configuration declaration Used to bind entity statements to particular architecture bodies. Package declaration Used to store a set of common declarations such as components, types, procedures and functions Package body Used to store the definition of functions and procedures declared in the package declaration SMD098 Computation Structures Lecture 2 3 The entity declaration The entity specifies the interface of a design unit. May be seen as a black box description Entity name library ieee; use ieee.std_logic_1164. all ; Library statement and use clause entity Adder is port ( A, B : in std_ulogic_vector(3 downto 0); Cin : in std_ulogic; Sum : out std_ulogic_vector(3 downto 0); Cout : out std_ulogic); end Adder; Port signal name Port mode Adder Port type A[3:0] B[3:0] Sum[3:0] Cout Cin SMD098 Computation Structures Lecture 2 4

3 Three most often used port modes: Port modes in out inout Entity Driver S Entity Driver I S Signal can not be read inside entity Port signal Signal I can be read inside entity I Port signal Mode out Mode out with internal signal I, The port signal S is assigned to the internal Signal I Entity Entity Driver S Driver S Driver Port signal Signal can be read inside entity Port signal Mode in Mode inout SMD098 Computation Structures Lecture 2 5 The architecture The architecture defines the contents of the black box Port declarations entity Adder is end Adder; Entity name Architecture declarations Architecture body architecture Demo of Adder is end Demo; Architecture name SMD098 Computation Structures Lecture 2 6

4 Modeling styles - sequential library ieee; use ieee.std_logic_1164.all; entity eqcomp4 is port (A, B : in std_logic_vector(3 downto 0); Equals : out std_logic); end eqcomp4; A B A=B Equals architecture seq1 of eqcomp4 is process(a, B) if A = B then Equals <= 1 ; else Equals <= 0 ; end if; end process; end seq1; architecture seq2 of eqcomp4 is process(a, B) Equals <= 0 ; if A = B then Equals <= 1 ; end if; end process; end seq2; If two architectures exist for one entity, the default architecture is used. The default architecture is the architecture that is compiled last. A configuration can explicatively specify which architecture to use. Read more about this in Zwolinsky chapter 3.8. ou will use a configuration in the last lab. SMD098 Computation Structures Lecture 2 7 Modeling styles - concurrent architecture concurrent of eqcomp4 is Equals <= 1 when (A = B) else 0 ; end concurrent; architecture concurrent_bool of eqcomp4 is Equals <= not(a(0) xor B(0)) and not(a(1) xor B(1)) and not(a(2) xor B(2)) and not(a(3) xor B(3)); end concurrent_bool; SMD098 Computation Structures Lecture 2 8

5 Modeling styles - structural library ieee; use ieee.std_logic_1164.all; use work.gates.all; -- component declarations found in package gates entity eqcomp4 is port (A, B : in std_logic_vector(3 downto 0); Equals : out std_logic); end eqcomp4; architecture structure of eqcomp4 is signal X : std_logic_vector(3 downto 0); u0 : xnor2 port map (A => A(0), B => B(0), O => X(0)); u1 : xnor2 port map (A => A(1), B => B(1), O => X(1)); u2 : xnor2 port map (A => A(2), B => B(2), O => X(2)); u3 : xnor2 port map (A => A(3), B => B(3), O => X(3)); u4 : and4 port map (A => X(0), B => X(2), C => X(3), D => X(4), O => Equals); end structure; SMD098 Computation Structures Lecture 2 9 A simple example of a hierarchical/structural VHDL code We want to model the following and-or structure ( = AB + CD) First we create two VHDL files, containing the description of an or-gate and an andgate. Name the files the same name as the name of the entity. File Or2.vhd entity Or2 is port ( A, B : in bit; : out bit); end Or2; architecture Gate of Or2 is <= A or B; end Gate; File And2.vhd entity And2 is port ( A, B : in bit; : out bit); end And2; architecture Gate of And2 is <= A and B; end Gate; SMD098 Computation Structures Lecture 2 10

6 Example cont. Next we create a third file, the top-level in the hierarchy. The top-level instantiates the gate models. A component declaration tells the compiler what each gate looks like The signal declaration creates architecture internal signals U2: And2 port map ( A => C, B => D, => B1); Create an instance named U2 of entity And2. Connect input A of U2 to input C of AndOr. Connect input B of U2 to input C of AndOr. Connect output of U2 to internal signal B1 File AndOr.vhd entity AndOr is port ( A, B, C, D : in bit; : out bit); end AndOr; architecture struct of AndOr is -- Component declarations component Or2 port ( A, B : in bit; : out bit); end component; component And2 port ( A, B : in bit; : out bit); end component; signal A1, B1 : bit; -- Instances U1: And2 port map ( A => A, B => B, => A1); U2: And2 port map ( A => C, B => D, => B1); U3: Or2 port map ( A => A1, B => B1, => ); end struct; SMD098 Computation Structures Lecture 2 11 Example cont. A more compact way to instantiate entities is direct instantiation. With this approach there is no need for a component declaration (note that this is new for VHDL 93 and some tools may not support it) Syntax is similar to the previous instantiation, the keyword entity is added and the full name of the library path where the instantiated component can be found. U2: entity work.and2(gate) port map( A => C, B => D, => B1); The library work is the current working library. gate is the architecture name. Modified file AndOr.vhd entity AndOr is port ( A, B, C, D : in bit; : out bit); end AndOr; architecture struct of AndOr is signal A1, B1 : bit; -- Direct instantiation U1: entity work.and2(gate) port map( A => A, B => B, => A1); U2: entity work.and2(gate) port map( A => C, B => D, => B1); U3: entity work.and2(gate) port map( A => A1, B => B1, => ); end struct; SMD098 Computation Structures Lecture 2 12

7 Example cont. But this is much simpler entity AndOr is port ( A, B, C, D : in bit; : out bit); end AndOr; architecture struct of AndOr is <= (A and B) or (C and D); end struct; SMD098 Computation Structures Lecture 2 13 A generic parameter may be used to pass a value of a specified type to an entity and its architecture. Generics library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Adder is generic ( Width : integer range 2 to 32 := 16); port ( A, B : in unsigned(width-1 downto 0); : out unsigned(width-1 downto 0)); end Adder; architecture RTL of Adder is <= A + B; end RTL ; The instantiation determines the value of the generic parameter. A configuration may also be used to specify generic parameters. If the parameter is not specified it will take its default value (16 in this case) Adder_1: Adder generic map (Width => 22) port map (A => A, B => B, => ); SMD098 Computation Structures Lecture 2 14

8 Signal assignments and delays A signal may be assigned future values using the following construct X <= 0, 1 after 1 ns, 0 after 3 ns, 1 after 8 ns, 0 after 13 ns; <= X after 4 ns; This is an inertial delay any pulse shorter than the delay is suppressed. A delay may specifically be defined as a transport delay where no pulses are suppressed. <= transport X after 4 ns; SMD098 Computation Structures Lecture 2 15 Delayed signal assignments are not synthesizable! Consider the following <= ((A and B) or (C and D)) after 4 ns; How can we before synthesis know the delay? Not possible! An estimate of the delay will be known after synthesis. Routing (wiring) delays will be known after place and route. Never model delays for synthesis! Delays are only suitable for simulation. ou may however think that the zero-delay model confusing when you look at the waveforms in simulation SMD098 Computation Structures Lecture 2 16

9 Zero-delay model Zero-delay Nonzero-delay SMD098 Computation Structures Lecture 2 17 Concurrent statements The architecture body contains concurrent statements. Sequential statements are not allowed in the architecture body. Two concurrent statements. Order is unimportant library ieee; use ieee.std_logic_1164. all ; entity Test is port ( A, B : in std_logic; X, : out std_logic); end Test; A B architecture Concurrent of Test is X <= A xor B; with A select <= B when 1, Z when 0, - when others ; Signal assignment operator X end Concurrent; Covers all cases SMD098 Computation Structures Lecture 2 18

10 Internal signals Internal signals can be declared in the declarative region of the architecture library ieee; use ieee.std_logic_1164. all ; entity Test is port ( A, B : in std_logic; X, : out std_logic); end Test; A B Int Signal declaration architecture Internal of Test is signal Int : std_logic; X Int <= A xor B; X <= not Int ; <= Int and A; end Internal; Internal signal can be read and be assigned new values. X and is not readable! SMD098 Computation Structures Lecture 2 19 Processes and sequential statements library ieee; use ieee.std_logic_1164. all ; entity Test is port ( A, B : in std_logic; X, : out std_logic); end Test; A B 0 1 X Process label Process declarative region architecture Proc of Test is P1: process (A, B) -- signal declarations not allowed Sensitivity list Process is activated whenever an event occurs on signal A or B Process body if A = 1 and X <= A; <= 1 ; else X <= B; <= 0 ; end if; B = 0 then Statements in the process body are executed sequentially! end process P1; end Proc; SMD098 Computation Structures Lecture 2 20

11 library ieee; use ieee.std_logic_1164.all; entity Test is port ( A, B : in std_logic; X, : out std_logic); end Test; Multiple processes interact concurrently A B 0 1 architecture Proc of Test is signal Internal : std_logic; 0 1 X P1 : process (A, B) if A = 1 and B = 0 then X <= A; Internal <= 0 ; else X <= B; Internal <= 1 ; end if; end process P1; P2 : process (A, B, Internal) if Internal = 1 then <= A; else <= B; end if; end process P2; end Proc; Process 1 Process 2 Each process execute its statements sequentially. Each process execute when there is an event on one of the signals on its sensitivity list. This may cause an event on another signal that triggers another process SMD098 Computation Structures Lecture 2 21 Concurrent vs. sequential execution architecture Concurrent of Test is <= A or B; <= C and D; end Concurrent; architecture Sequential of Test is process (A, B, C, D) <= A or B; <= C and D; end process ; end Sequential; A B C D? Resolution function C D Synplify will report errors! Multiple non-tristate drivers for net The signal is updated with the last value assigned to it A signal that is assigned to within a process is not updated until the process is suspended. SMD098 Computation Structures Lecture 2 22

12 Sensitivity lists For a process that models combinational logic, the sensitivity list must be complete! All signals that are read ( inputs to the process) must be in the sensitivity list. What does this process model? process(a) <= A or B or C or D; end process; Our synthesis tool Synplify will assume that the sensitivity list is complete. The function of the synthesized logic will not match the function of the VHDL model you simulated. SMD098 Computation Structures Lecture 2 23 Event based simulation Simulation delta cycle Delta Signal Update Process Execution Time Delta "time" is orthogonal to simulation time Advance in time when no more processes are scheduled to execute at current simulation time SMD098 Computation Structures Lecture 2 24

13 Simulation - an example architecture sim of Test is signal A, B, C, D : std_logic := 0 ; signal S1, S2, : std_logic; 1 10ns 0 5ns 1 5ns 0 0 A B A <= 0 after 5 ns, 1 after 10 ns; B <= 1 after 5 ns; C <= 0 after 5 ns, 1 after 10 ns; D <= 1 after 5 ns; S1 <= A xor B; S2 <= C xor D; <= S1 and S2; A B S1 1 10ns 0 5ns 1 5ns 0 0 C D end Sim; C D S2 t (ns) A B C D S1 S U U U U SMD098 Computation Structures Lecture 2 25 Combinational feedback loops In a synchronous design combinational feedback loops must be avoided. (There are some rare exceptions though.) Assume S = 0 and A = 1. What will happen in simulation? Simulation will never advance in time! A S <= S xor A; S SMD098 Computation Structures Lecture 2 26

14 Data objects - constants A constant can hold a single value of a given type. Must be declared in package, entity, architecture or process declarative region. Can improve maintainability and readability of code. constant Mult : std_logic_vector := 0001 ; -- Opcode multiply constant Width : integer := 12; SMD098 Computation Structures Lecture 2 27 Data objects - signals Holds a list of values, which include the current value, past value and a set of possible scheduled values that are to appear on the signal. Future values can be assigned to the signal using the signal assignment operator. signal shiftreg : std_logic_vector(7 downto 0); shiftreg <= shiftreg(6 downto 0) & Input; May be assigned initial values when declared: signal Count : std_logic_vector(3 downto 0) := 0101 ; But this is not meaningful for synthesis! Signals can represent wires and memory holders. SMD098 Computation Structures Lecture 2 28

15 Data objects - variables Can hold a single value of a given type, but different values can be assigned to the variable at different times using a variable assignment statement. A variable is locally declared in a process or subprograms and can only be used locally. Variables are more abstract compared to signals. Variable assignments are immediately and not scheduled. variable ShiftReg : std_logic_vector(7 downto 0); shíftreg := shiftreg(6 downto 0) & Input; Use variable whenever possible since a variable uses less simulation resources than a signal. A ner may however find working with signals easier. SMD098 Computation Structures Lecture 2 29 Variables in processes A variable is declared inside the process and is not visible outside the process. A variable is updated immediately. Retains its value through the simulation Variable declaration D architecture Var of Test is process(a, B, C, D) variable Temp : std_logic; temp := 0 ; temp := temp xor A; temp := temp xor B; temp := temp xor C; temp := temp xor D; <= temp; end process; end Var; A B C SMD098 Computation Structures Lecture 2 30

16 Data objects - files Files are only useful for simulation. Obviously a file data object does not belong in synthesis. ou will learn more about files when you write your own test benches in future labs. file StimFile: TEXT open read_mode is "stim.txt"; file ResultFile: TEXT open write_mode is Result.txt"; SMD098 Computation Structures Lecture 2 31 Data types (some of them) Enumeration data type: Contains a set of user defined values type MyBit is ( 0, 1 ); type Beer is (Pripps, Falcon, KeyBeer, Guiness); Integer data type: Defines a range of integer numbers. Default is a 32-bit integer type Count is integer range 0 to 10; Array data type: type MyBitVector is array (natural range <>) of Mybit; type MyByte is array (natural range 7 downto 0) of Mybit; Record data type: type FloatType is record Sign : MyBit; Mantissa : MyBitVector(7 downto 0); Exponent : MyBitVector(15 downto 0); end record; Subtype: subtype Byte is std_ulogic_vector 7 downto 0; SMD098 Computation Structures Lecture 2 32

17 package STANDARD is type boolean is (false, true); type bit is ( 0, 1 ); type character is ( ASCII chars... ); type severity_level is (note, warning, error, failure); type integer is range to ; type real is range -1.0E308 to 1.0E308; type time is range to units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; subtype delay_length is time range 0 fs to time high; impure function now return delay_length; subtype natural is integer range 0 to integer high; subtype positive is integer range 1 to integer high; type string is array (positive range <>) of character; type bit_vector is array (natural range <>) of bit; type file_open_kind is ( read_mode, write_mode, append_mode); type file_open_status is ( open_ok, status_error, name_error, mode_error); attribute foreign : string; end STANDARD; Predefined types What types are meaningful for synthesis? SMD098 Computation Structures Lecture 2 33 Attributes There are many predefined attributes defined in VHDL. Not all can be used for synthesis. Attributes not supported for synthesis either relate to timing or are not necessary to model the physical structure of logic. Some attributes useful for synthesis: clock event returns true if an event occurred on the signal clock signal A : unsigned(3 downto 0) A left returns 3 A right returns 0 A range returns 3 downto 0 A length returns 4 SMD098 Computation Structures Lecture 2 34

18 The std_logic_1164 package The predefined type bit is defined as type bit is ( 0, 1 ); Can not model, high impedance, don t cares etc. So in std_logic_1164 a new type, std_ulogic, is defined: type std_ulogic is ( U, -- Uninitialized X, -- Forcing Unknown 0, -- Forcing 0 1, -- Forcing 1 Z, -- High Impedance W, -- Weak Unknown L, -- Weak 0 H, -- Weak Don t care ); std_ulogic_vector is defined as type std_ulogic_vector is array ( natural range <> ) of std_ulogic; SMD098 Computation Structures Lecture 2 35 The resolved type std_logic A signal that has multiple drivers must be of a resolved type. std_ulogic is not resolved but std_logic is a resolved type that is derived from std_ulogic. The resolved vector type is called std_logic_vector Driver 1 Resolution Function 1? 1 Driver 2 Z Resolution table for std_logic U X 0 1 Z W L H ( U, U, U, U, U, U, U, U, U ), -- U ( U, X, X, X, X, X, X, X, X ), -- X ( U, X, 0, X, 0, 0, 0, 0, X ), -- 0 ( U, X, X, 1, 1, 1, 1, 1, X ), -- 1 ( U, X, 0, 1, Z, W, L, H, X ), -- Z ( U, X, 0, 1, W, W, W, W, X ), -- W ( U, X, 0, 1, L, W, L, W, X ), -- L ( U, X, 0, 1, H, W, W, H, X ), -- H ( U, X, X, X, X, X, X, X, X ) -- - SMD098 Computation Structures Lecture 2 36

19 Functions in std_logic_1164 A set of overloaded logic functions and conversion functions are defined in std_logic_1164. The logic functions are overloaded so they can be used for the std_logic and std_ulogic (and vector) types Logic functions: and, nand, or, xor, xnor, not Conversion functions: To_bit, To_bitvector, To_StdULogic, To_StdULogicVector, ToStdLogicVector Also in the package, edge detecting functions: rising_edge() and falling_edge() The std_logic_1164 package does not contain any functions for arithmetic operations SMD098 Computation Structures Lecture 2 37 The numeric_std package In the IEEE synthesis package, numeric_std, the types unsigned and signed are defined. type unsigned is array (natural range <>) of std_logic; type signed is array (natural range <>) of std_logic; In the package a set of arithmetic functions are defined as well as conversion functions. Both std_logic_1164 and numeric_std will be used in the labs. ou will see examples in the first lab. A quick reference card for the packages can be found at the course webpages. SMD098 Computation Structures Lecture 2 38

20 Type conversions Because VHDL is a strongly typed language type conversions are unavoidable. Closely related types may be converted using the syntax: target_type_name(expr) Types that are not closely related need a type conversion function Closely related contain same elements architecture of X is signal S : std_logic_vector(7 downto 0); signal A, B : unsigned(7 downto 0); signal MyInt : integer; -- This will cause type error S <= B; -- Type conversion, target is a std_logic_vector S <= std_logic_vector(a); -- The + operator is defined for unsigned, -- signed and integer in numeric_std. -- A + B will result in unsiged since the -- operators are of unsigned type S <= std_logic_vector(a + B); -- to_integer is a type conversion fucntion -- in numeric_std. Note that integer(a + B) -- will result in type error. MyInt <= to_integer(a + B); -- The + operator is overloaded in -- numeric_std. A <= unsigned(s) + MyInt; end ; SMD098 Computation Structures Lecture 2 39 Assigning values to arrays architecture assign of Examples is signal Byte : std_logic_vector(7 downto 0) := " "; signal Word : std_logic_vector(15 downto 0); Byte <= " "; Initialization not supported for synthesis Byte <= ( 1, 0, 1, 0, 1, 0, 1, 0 ); Positional association Byte <= X"0F"; Hexadecimal Byte <= (others => 1 ); Byte <= (7 6 => 1, others => 0 ); Named association Byte <= (7 => 1, 4 => 1, 3 downto 1 => 0, others => 0 ); Word <= X"FF" & Byte; Concatenation Word(15 downto 8) <= (others => Byte(7)); Word(7 downto 0) <= Byte; end Examples; Sign extend (can be done with a single statement) SMD098 Computation Structures Lecture 2 40