Amrita Vishwa Vidyapeetham. EC429 VLSI System Design Answer Key

Transcription

1 Time: Two Hours Amrita Vishwa Vidyapeetham B.Tech Second Assessment March 2013 Eighth Semester Electrical and Electronics Engineering EC429 VLSI System Design Answer Key Answer all Questions Roll No: Maximum: 50 Marks 1. An engineer has chosen the following way to model a sequential pipeline register in Verilog. When code segment is implemented in Xilinx tools, a warning message is issued. The engineer observed a race condition in simulated output. Correct the code so that, it simulate correctly and synthesize the desired pipeline logic. State your reasons. (4 marks) module pipeline (q3, d, clk); output [7:0] q3; input [7:0] d; input clk; reg [7:0] q3, q2, q1; clk) clk) q1 = d; clk) q2 = q1; clk) q3 = q2; Block diagram of sequential pipeline register Verilog simulates the "always" blocks in any order, which might cause this pipeline simulation to be wrong. This leads to a Verilog race condition. Executing the always blocks in a different order yields a different result. Replacing the blocking statements by non-blocking statements will simulate and synthesize the code correctly. module pipeline (q3, d, clk); output [7:0] q3; input [7:0] d; input clk; reg [7:0] q3, q2, q1; clk) q1 <= d; clk) q2 <= q1; clk) q3 <= q2; (2 marks) (2 marks) 2. Generate a clock pulse of following pattern using forever statement in Verilog. (4 marks)

2 module Clock_gen (Clk) output Clk; reg Clk; initial Clk = 0; # 7; forever # 3 Clk = 1; # 5 Clk = 0; 3. The following segment of Verilog code is supposed to describe a circuit. Identify and draw the circuit that the code synthesizes to. (2 marks) assign a = (g)? x : y; 2 x 1 Multiplexer 4. Consider the following fragment of the Verilog code. Draw the waveform produced on wave. Also rewrite the code using non-blocking procedural assignment and draw the waveform. (3 marks) initial wave = #5 0; wave = #4 1; wave = #10 0; initial wave <= #5 0; wave <= #4 1; wave <= #10 0;

3 5. Write the Verilog description of a counter with an asynchronous reset (active high) signal. The counter should count from 9 to 99 on a negative edge of the clock and then restart at 9. (5 marks) module counter(clk, reset, C) input clk, reset; output reg [6:0] C; clk or posedge reset) if (reset) C<=9; else if (C == 99) C <= 9; else C <= C+1; 6. Develop a Verilog model for 4-bit priority encoder using casex statements. Let the input be represented as D and output as Y. A valid output indicator V is set to 1 only when one or more of the inputs is equal to 1. If all the inputs are 0, V is equal to 0 and two outputs of the circuit are not used. (5 marks) module priority_encoder (D, Y, V); input [3:0] D; output reg[1:0] Y; output reg V; V= 1; casex (D) 4'b1xxx: Y = 3; 4'b01xx: Y = 2; 4'b001x: Y = 1; 4'b0001: Y = 0; default: V= 0; Y = 2'bx; case 7. Examine the Verilog code below and identify any errors that would prevent this code from compiling and synthesizing properly. (3 marks)

4 wire a,b,c; wire y; or b) if (a=1 && b=1 && c = 0) y = 0; else if (a = 1 && b=1 && c = 1) y = 1; # missing c in sensitivity list # if conditions should use ==, not =. # Y should be declared as a reg 8. A NOR gate can be realized using PMOS and NMOS switches as shown below in figure8.1. Use this realization to build a SR latch shown in figure8.2 using PMOS and NMOS switches. Write the switch level Verilog code for the SR latch realization using pmos and nmos switches. (7 marks) (3 marks)

5 module SRlatch_cmos (R, S, Q, Qbar) (4 marks) input R, S; output Q, Qbar; wire c1, c2; supply1 pwr; supply0 gnd; pmos p1(c1, pwr, R); pmos p2(q, c1, Qbar); pmos p3(c2, pwr, Q); pmos p4(qbar, c2, S); nmos n1(q, gnd, R); nmos n2(q, gnd, Qbar); nmos n3(qbar, gnd, Q); nmos n4(qbar, gnd, S); 9. Develop a Verilog code for an unsigned 8x4-bit multiplier. (4 marks) module multiplier (a, b, mul); input [7:0] a; input [3:0] b; output [11:0] mul; assign mul = a * b; 10. Develop a Verilog model of a counter and seven-segment display as shown below. The counter increments while Enable is asserted. The display is blank while Blanking is asserted. If Blanking is not asserted the display shows only even-valued numbers, and remains latched if BCD is the code of an odd number or an invalid number. (6 marks) module 7_Display (Display_L, Display_R, Blanking, Enable, clock, reset); output [6: 0] Display_L, Display_R; input Blanking, Enable, clock, reset; reg [6: 0] Display_L, Display_R; reg [3: 0] count; // abc_defg

6 parameter BLANK = 7'b111_1111; parameter ZERO = 7'b000_0001; // h01 parameter ONE = 7'b100_1111; // h4f parameter TWO = 7'b001_0010; // h12 parameter THREE = 7'b000_0110; // h06 parameter FOUR = 7'b100_1100; // h4c parameter FIVE = 7'b010_0100; // h24 parameter SIX = 7'b010_0000; // h20 parameter SEVEN = 7'b000_1111; // h0f parameter EIGHT = 7'b000_0000; // h00 parameter NINE = 7'b000_0100; // h04 (posedge clock) if (reset) count <= 0; else if (Enable) count <= count +1; (count or Blanking) if (Blanking) Display_L = BLANK; Display_R = BLANK; else case (count) 0: Display_L = ZERO; Display_R = ZERO; 2: Display_L = ZERO; Display_R = TWO; 4: Display_L = ZERO; Display_R = FOUR; 6: Display_L = ZERO; Display_R = SIX; 8: Display_L = ZERO; Display_R = EIGHT; 10: Display_L = ONE; Display_R = ZERO; 12: Display_L = ONE; Display_R = TWO; 14: Display_L = ONE; Display_R = FOUR; default: Display_L = BLANK; Display_R = BLANK; case 11. Digital signal processors has barrel shifter module which implements a circular shift, that is, the value shifted out on one of the vector shifts in on the other. Write a Verilog module which implements a barrel shifter with ports as shown in the provided port list and truth table. Consider the shift right to have priority over shift left. Take x in the truth tables as don t care. Also give the stimulus block to verify the module. (7 marks)

7 module bshift (din, shift_right, shift_left, numshift, dout); input [3:0] din; input shift_right, shift_left; input [1:0] num_shift; output reg[3:0] dout; if (shift_right == 1 b1) case (num_shift) 0: dout = din; 1: dout = {din[2:0], din[3]}; 2: dout = {din[1:0], din[3:2]}; default: = {din[0], din[3:1]}; case else if (shift_left == 1 b1) case (num_shift) 0: dout = din; 1: dout = {din[0], din[3:1]}; 2: dout = {din[1:0], din[3:2]}; default: dout = {din[2:0], din[3]}; case else dout = din;