AccuCore. Product Overview of Block Characterization, Modeling and STA
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1 AccuCore Product Overview of Block Characterization, Modeling and STA
2 What is AccuCore? AccuCore performs timing characterization of multi-million device circuits with SmartSpice accuracy and performs block and full-chip Static Timing Analysis (STA) on multi-million gate designs - 2 -
3 AccuCore Inputs and Outputs - 3 -
4 Key Features Generates Liberty (.lib) timing models, generates a gate-level verilog netlist and generates or reads DSPF files for STA Exports fully sensitized SPICE deck for selected critical paths and clocktrees with measurements Automatically partitions blocks into cells Automatically extracts cell functions and generates vectors required for accurate SPICE characterization Includes fast API-based SmartSpice characterization engine Complete block and full-chip gate-level STA environment for rapid bottleneck analysis and timing verification Powerful command set enables mixing both custom and ASIC/SoC functions in a single analysis environment - 4 -
5 Setup & Scripting Capabilities Automated.lib to.cfg import for easy setup and scripting with various.cfg validation options Supports full case sensitivity flows Supports both flat and hierarchical design flow Advanced RC mode for efficient handling of large designs Advanced slope propagation and threshold management options Supports various user defined loading methods Automatic hierarchical and flat netlist partitioning of blocks to cells with advanced user override options Dedicated RAM/CAM partitioning with sense amp and read/write cycle options Advanced strength and state-based function extraction features Automatic clock propagation with advanced user overrides Supports user defined input vector constraints Advanced debugging and design reporting options for quick root-cause analysis - 5 -
6 AccuCore Process - 6 -
7 Block-level STA Capabilities Enables gate-level timing checks of custom transistor level designs Utilizes advanced path tracing algorithms of longest and shortest paths Performs both critical and sub-critical method tracing to avoid multi-layer timing problems Automatic false path elimination Numerous path limiting and pin, net and arc based blocking options Performs function-based clock and constraint propagation reducing ECO re-analysis ripple-effects Supports various design styles of both static and dynamic logic, latches, flip-flops, muxes, and tristate circuits - 7 -
8 Block-level STA Capabilities (cont d) Built-in timing checks simplify constraint specification Analyzes gated and multi-frequency clocks across multi-cycle paths Permits customized gated clock, data-to-data and clock-to-data path timing checks Supports DSPF and SDF back-annotation Performs bottleneck analysis of arrival and required path net and pin based timing requirements Permits separate multiple rise and fall edge timing specifications common in footless logic - 8 -
9 Output Example AccuCore Output Files pin (icount[0]) { direction : input; capacitance : 0.282; clock : false; timing() { related_pin : phi ; timing_type : setup_falling ; rise_constraint (InSlopeClkSlope_3) { } values ( 1.302, 1.286, 1.250, 1.212, 1.136, \ 1.342, 1.326, 1.290, 1.252, 1.176, \ 1.365, 1.349, 1.313, 1.275, 1.199, \ 1.374, 1.358, 1.322, 1.284, 1.208, \ 1.376, 1.360, 1.324, 1.286, ); fall_constraint (InSlopeClkSlope_3) { } values ( 1.290, 1.274, 1.238, 1.200, 1.124, \ 1.340, 1.324, 1.288, 1.250, 1.174, \ } timing() { 1.385, 1.369, 1.333, 1.295, 1.219, \ 1.423, 1.407, 1.371, 1.333, 1.257, \ 1.456, 1.440, 1.404, 1.366, ); related_pin : phi ; timing_type : hold_rising ; rise_constraint (InSlopeClkSlope_3) { values ( , , , , , \ , , , , , \ , , , , , \ , , , , , \ , , , , ); -- Data Path -- Time(ns) Net SigType Edge Inst(Cell) InPin OutPin Delay(ns) Slope(ns) shift_64/\mode[0] PrimData r shift_64/i_dc_1435(dc_1435) I0(ucd) O0(ucd) shift_64/\seam/bmode_n[0] PrimData f shift_64/i_dc_1436(dc_1436) I0(ucd) O0(ucd) shift_64/\seam/bmode[0] PrimData r shift_64/i_dc_1461(dc_1461) I0(ucd) O0(ucd) shift_64/\seam/left_n PrimData f shift_64/i_dc_1635(dc_1635) I0(ucd) O0(ucd) shift_64/\seam/left PrimData r shift_64/i_dc_1636(dc_1636) I0(ucd) O0(ucd) shift_64/\seam/bleft_n PrimData f shift_64/i_dc_1838(dc_1838) I0(ucd) O0(ucd) shift_64/\cnt_bleft[1] PrimData r shift_64/i_dc_1919(dc_1919) I1(ucd) O0(ucd) shift_64/\cnt17/u0/u0/z_n PrimData r shift_64/i_dc_1920(dc_1920) I0(ucd) O0(ucd) shift_64/\cnt17/u0/bcnt[0] PrimData f shift_64/i_dc_1923(dc_1923) I0(ucd) O0(ucd) shift_64/\cnt17/u0/u2/2 PrimData r shift_64/i_dc_1924(dc_1924) I0(ucd) O0(ucd) shift_64/\cnt17/u0/c1 PrimData f shift_64/i_dc_1925(dc_1925) I1(ucd) O0(ucd) shift_64/\cnt17/u0/u3/2 PrimData r shift_64/i_dc_1926(dc_1926) I0(ucd) O0(ucd) shift_64/\cnt17/c2 PrimData f shift_64/i_dc_1929(dc_1929) I1(ucd) O0(ucd) shift_64/\cnt17/u1/u2/2 PrimData r shift_64/i_dc_1930(dc_1930) I0(ucd) O0(ucd) shift_64/\cnt17/u1/c1 PrimData f shift_64/i_dc_1933(dc_1933) I0(ucd) O0(ucd) shift_64/\cnt17/u1/u3/2 PrimData r shift_64/i_dc_1934(dc_1934) I0(ucd) O0(ucd) shift_64/\cnt17/c4 PrimData f shift_64/i_dc_1937(dc_1937) I0(ucd) O0(ucd) shift_64/\cnt17/u2/u1/sum_n PrimData f shift_64/i_dc_1938(dc_1938) I0(ucd) O0(ucd) shift_64/count17 PrimData r shift_64/i_dc_2895(dc_2895) I0(ucd) O0(ucd) shift_64/\mx17/z_n PrimData r shift_64/i_dc_2896(dc_2896) I0(ucd) O0(ucd) shift_64/\q[17] PrimData f shift_64/i_dc_2897(dc_2897) I2(ucd) O0(ucd) shift_64/\msk17/dq_n PrimData r shift_64/i_dc_2898(dc_2898) I1(ucd) O0(ucd) shift_64/\result[17] PrimData f Total path delay without offset:2.662ns Check:30 setup(0.200ns) ns ---- shift_64/phi r shift_64/\result[13] f Margin (RefTime(RefPath)-DataTime(DataPath)-setupConstraint): 2.700ns-2.861ns-0.200ns=-0.361ns Example.lib pin timing for one pin of a 64 bit shift block using a 5 X 5 slope/load matrix. Example path report for a black box model
10 Full-chip STA Capabilities Concurrently performs both block-level and full-chip STA Generates compressed, ring/interface and blackbox timing models Supports hierarchical verilog and mode-based multi-corner analysis Supports both DSPF and SDF back-annotation Enables constraint management, block-level constraint generation and slack allocation for hierarchical design methods Permits user-specified uncertainty and skew relationship driven timing analysis with common path optimization Advanced debugging features for clock waveform and clock propagation Advanced debugging features for netlist, library and analysis verification Tcl API interface for custom reporting and analysis functions
11 Summary Accuracy Dynamic Simulation Propagation of Slopes Tables throughout Design Easy to use - Setup, Maintenance Simple.tcl script-based config file Automatic function extraction Automatic Vector generation for Dynamic Simulation runs No manual transistor direction setting Automatic false path removal Supports aggressive design styles High performance designs - dynamic logic Complex mixed level static timing analysis tool built in Critical Paths, Sub-critical paths, timing checks, Slack reports SPICE deck creation of Critical paths (ready-to-run in SPICE simulations) Various types of Model generation for hierarchical design and full-chip STA Quicker timing convergence Incremental characterization Reduces Design Cycle Improves Design Quality
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